CN114385535A - Adaptive impedance matching circuit of PHY chip and working method thereof - Google Patents

Adaptive impedance matching circuit of PHY chip and working method thereof Download PDF

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CN114385535A
CN114385535A CN202111479974.9A CN202111479974A CN114385535A CN 114385535 A CN114385535 A CN 114385535A CN 202111479974 A CN202111479974 A CN 202111479974A CN 114385535 A CN114385535 A CN 114385535A
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signal
control signal
impedance matching
impedance
nmos
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田晓成
刘博�
曾耀庆
车文毅
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Yutai Microelectronics Co ltd
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Yutai Microelectronics Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/28—Impedance matching networks

Abstract

The invention relates to a self-adaptive impedance matching circuit of a PHY chip and a working method thereof.A transmitting end of the PHY chip is connected with an MAC chip interface through a transmission line, the PHY chip comprises a variable impedance transmitting circuit, a variable impedance main driver and a control signal sequence, wherein an output signal is transmitted from an output end after passing through the variable impedance main driver, and the main driver adjusts the impedance value of the variable impedance under the action of the control signal sequence; the impedance matching detection circuit converts the impedance matching state of the signal of the output end and the transmission line into a count value under the action of an enable signal and a clock signal, and selects a control signal sequence according to the count value. The invention obtains the control signal sequence under the optimal matching state by detecting the signal waveform of the output end of the sending end so as to control and adjust the impedance value of the variable impedance of the sending end, thereby realizing the impedance matching of the source end and enabling the chip to be capable of adapting to transmission lines with different impedance values.

Description

Adaptive impedance matching circuit of PHY chip and working method thereof
Technical Field
The invention relates to the technical field of Ethernet chips, in particular to a self-adaptive impedance matching circuit and a working method thereof.
Background
In a currently common ethernet communication device, PHY (Physical Layer) Layer communication and MAC (Media Access Control) Layer communication are implemented using two independent chips. Commonly used communication protocols between the PHY chip and the MAC chip include MII (Media Independent Interface), RMII (Reduced Media Independent Interface), GMII (Gigabit Media Independent Interface), RGMII (Reduced Gigabit Media Independent Interface), and the like, and communication Media thereof are microstrip transmission lines on a PCB (Printed Circuit Board).
Fig. 1 shows an example of the PHY chip 1 transmitting an RXC clock to the MAC chip 2, where ZS is an equivalent output impedance of the transmitting terminal Tx, ZL is an equivalent input impedance of the receiving terminal Rx, and ZT is a characteristic impedance of the transmission line. In the MII, RMII, GMII, RGMII and other communication protocols, the equivalent input impedance ZL of the receiving end Rx is often designed to be high impedance to meet the requirement of the signal amplitude reaching the receiving end Rx, and at the transmitting end Tx, ZS is made equal to ZT to realize source-end impedance matching so as to reduce reflection and standing waves in microstrip signal transmission. In many application scenarios, a PCB is often developed before a chip is developed, in the prior art, the output impedance of a Tx circuit at a transmitting end is usually designed to be a fixed value in the chip development process, and when such a chip is applied to devices with different characteristic impedance values of microstrip transmission lines, a transmission/reception signal between an ethernet PHY chip and an MAC chip interface is negatively affected by impedance mismatch, thereby deteriorating the signal transmission quality between the PHY chip and the MAC chip.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide an adaptive impedance matching circuit of a PHY chip; the present invention also provides a method for operating an adaptive impedance matching circuit of a PHY chip.
The self-adaptive impedance matching circuit of the PHY chip, the output end of the transmitting end of the PHY chip is connected with the MAC chip interface through a transmission line, the PHY chip comprises,
the variable impedance transmitting circuit transmits an output signal from the output end after passing through a main driver of variable impedance, and the main driver adjusts the impedance value of the variable impedance under the action of a control signal sequence;
and the impedance matching detection circuit is connected with the output end of the variable impedance sending circuit, converts the impedance matching state of the signal of the output end and the transmission line into a count value under the action of an enable signal and a clock signal, and selects the control signal sequence according to the count value.
The adaptive impedance matching circuit of the present invention, the main driver includes,
the N PMOS tube branches are controllably connected between a power supply voltage end and the output end in parallel and comprise N PMOS driving tubes and N PMOS switching tubes, and each PMOS driving tube is connected with one PMOS switching tube;
the N NMOS tube branches are controllably connected between the output end and the grounding end in parallel and comprise N NMOS driving tubes and N NMOS switch tubes, and each NMOS driving tube is connected with one NMOS switch tube;
the grid electrode of each PMOS switching tube and the grid electrode of each NMOS switching tube are connected with a control signal, the grid electrode of the ith NMOS switching tube is connected with the ith control signal, the grid electrode of the ith PMOS switching tube is connected with the negation signal of the ith control signal, i belongs to [1, N ], and the control signal sequence is formed by the 1 st control signal connected with the grid electrode of the 1 st NMOS switching tube and the Nth control signal connected with the grid electrode of the Nth NMOS switching tube.
The self-adaptive impedance matching circuit further comprises a pre-driving-stage phase inverter, wherein the input end of the pre-driving-stage phase inverter is connected with the output signal, and the output end of the pre-driving-stage phase inverter is connected with the grid electrodes of the PMOS driving tube and the NMOS driving tube.
The adaptive impedance matching circuit of the present invention,
the source end of each PMOS driving tube is connected with the power supply voltage end, the drain end of each PMOS driving tube is connected with the source end of the PMOS switching tube, and the drain end of each PMOS switching tube is connected with the output end;
the drain end of each NMOS switch tube is connected with the output end, the source end of each NMOS switch tube is connected with the drain end of each NMOS driving tube, and the source end of each NMOS switch tube is connected with the grounding end.
The adaptive impedance matching circuit of the present invention, the impedance matching detection circuit includes,
the resistance voltage division circuit comprises a preset number of voltage division resistors connected between the power supply voltage end and the grounding end, and a first reference voltage division, a second reference voltage division and a third reference voltage division are respectively led out from different points connected among the voltage division resistors;
the first comparator compares the voltage of the output end with the first reference divided voltage to generate a first comparison signal;
the second comparator compares the voltage of the output end with the second reference divided voltage to generate a second comparison signal;
and the exclusive-OR gate is used for carrying out exclusive-OR operation on the first comparison signal and the second comparison signal and outputting an impedance matching detection signal.
The adaptive impedance matching circuit of the present invention, the impedance matching detection circuit includes,
a first MOS transistor controllably connected between a current source and a first reference node under control of the impedance matching detection signal;
a first capacitor connected between the first reference node and a ground terminal;
the second MOS tube is controllably connected between the first reference node and a grounding end under the action of a first control signal;
a third comparator for comparing the third reference divided voltage with the voltage of the first reference node to generate a third comparison signal;
a nor gate for performing a nor logic operation on the third comparison signal and the first control signal to generate a first logic signal;
the AND gate is used for carrying out AND logic operation on the first logic signal and the clock signal to generate a second logic signal;
and the clock end of the counter is connected with the second logic signal, the trigger end of the counter is connected with an enabling signal, and the counter outputs a count value.
The self-adaptive impedance matching circuit comprises a first phase inverter, and the first phase inverter is connected with the enable signal to the control end of the second MOS tube.
According to the self-adaptive impedance matching circuit, the transmission line is a microstrip transmission line, and the characteristic impedance of the transmission line is 50 ohms, or 75 ohms, or 100 ohms.
In the adaptive impedance matching circuit, the output end of the PHY chip is a port for transmitting MII and/or RMII and/or GMII and/or RGMII signals.
The working method of the self-adaptive impedance matching circuit of the PHY chip comprises the following steps:
step S1, setting all control signal sequences formed by the 1 st control signal to the Nth control signal to be zero;
step S2, adding 1 to the control signal sequence,
step S3, the output signal is sent out through the output end of the PHY chip;
step S4, enabling the impedance matching detection circuit through the enabling signal, and recording the corresponding count value output by the counter;
step S5, judging whether all the control signal sequences are 1, if all the control signal sequences are 1, executing step S6, if not all the control signal sequences are 1, repeating step S2;
in step S6, a control signal sequence corresponding to the minimum count value is selected from all the count values and sent to the variable impedance transmission circuit.
Has the advantages that: according to the invention, the signal waveform of the output end SIG _ pad of the sending end TX is detected, and the control signal sequence in the optimal matching state is obtained to control and adjust the impedance value of the variable impedance VZS of the sending end TX, so that the source end impedance matching is realized, and the chip can be adapted to transmission lines with different impedance values.
Drawings
FIG. 1 is a schematic diagram of prior art connections for a PHY chip to send an RXC clock to a MAC chip;
FIG. 2 is a schematic diagram of a PHY chip interface circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a variable impedance transmission circuit in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of an impedance match detection circuit according to an embodiment of the present invention;
FIG. 5 is a waveform diagram of the important node of FIG. 4 according to the present invention;
fig. 6 is a flow chart of a method of operation of an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
Referring to fig. 2, an adaptive impedance matching circuit of a PHY chip, an output terminal SIG _ pad of a transmitting terminal TX of the PHY chip 1 is connected to an MAC chip interface through a transmission line, the PHY chip 1 includes,
the variable impedance transmitting circuit 11 transmits an output signal SIG _ tx from the output terminal SIG _ pad after passing through a main driver DR of a variable impedance VZS, the main driver DR adjusting the impedance value of the variable impedance VZS under the action of a control signal sequence K < N:1 >;
the impedance matching detection circuit 12 is connected to the output terminal SIG _ pad of the variable impedance transmitting circuit 11, converts the impedance matching state of the signal of the output terminal SIG _ pad and the transmission line into a count value under the action of an enable signal EN and a clock signal CLK, and selects the control signal sequence K < N:1> according to the count value.
According to the invention, the signal waveform of the output end SIG _ pad of the sending end TX is detected, and the control signal sequence in the optimal matching state is obtained to control and adjust the impedance value of the variable impedance VZS of the sending end TX, so that the source end impedance matching is realized, and the chip can be adapted to transmission lines with different impedance values.
The adaptive impedance matching circuit of the present invention, referring to fig. 3, the main driver DR includes,
the PMOS tube branches are controllably connected between a power supply voltage end VDD and an output end SIG _ pad in parallel and comprise N PMOS driving tubes and N PMOS switching tubes, and each PMOS driving tube is connected with one PMOS switching tube;
the N NMOS tube branches are controllably connected between the output end SIG _ pad and a ground end GND in parallel and comprise N NMOS driving tubes and N NMOS switching tubes, and each NMOS driving tube is connected with one NMOS switching tube;
the grid electrodes of each PMOS switching tube and each NMOS switching tube are connected with a control signal, the grid electrode of the ith NMOS switching tube is connected with the ith control signal, the grid electrode of the ith PMOS switching tube is connected with the negation signal of the ith control signal, i belongs to [1, N ], the control signal sequence K < N:1> is formed by the control signal from the 1 st control signal connected with the grid electrode of the 1 st NMOS switching tube to the Nth control signal connected with the grid electrode of the Nth NMOS switching tube.
The adaptive impedance matching circuit, the variable impedance transmission circuit of the present invention further comprises
The input end of the pre-drive stage inverter INV _ PDR is connected with the output signal SIG _ tx, and the output end of the pre-drive stage inverter INV _ PDR is connected with the grids of the PMOS driving tube and the NMOS driving tube.
The source end of each PMOS driving tube is connected with a power supply voltage end VDD, the drain end of each PMOS driving tube is connected with the source end of a PMOS switching tube, and the drain end of each PMOS switching tube is connected with an output end SIG _ pad;
the drain terminal of each NMOS switching tube is connected with the output terminal SIG _ pad, the source terminal of each NMOS switching tube is connected with the drain terminal of each NMOS driving tube, and the source terminal of each NMOS switching tube is connected with the ground terminal GND.
The traditional fixed impedance sending circuit comprises a PMOS driving tube and an NMOS driving tube which are connected with a power supply voltage and a grounding end, wherein the output impedance of the PMOS driving tube and the NMOS driving tube is determined by the size of the PMOS driving tube and the NMOS driving tube and the power supply voltage together.
Referring to fig. 3, the N PMOS transistors are MP1, MP2, …, and MPN, the N PMOS transistors are MU1, MU2, …, and MU, the N NMOS transistors are MN1, MN2, …, and MNN, the N NMOS transistors are MD1, MD2, …, and MDN, and the gate of the 1 st NMOS transistor MD1 is connected to the 1 st control signal K<1>The grid of the 1 st PMOS switch tube is connected with the inverted signal Kb of the 1 st control signal<1>The gate of the 2 nd NMOS switch tube MD2 is connected to the 2 nd control signal K<2>The grid of the 2 nd PMOS switch tube is connected with the inverted signal Kb of the 2 nd control signal<2>The gate of the Nth NMOS switch tube MDN is connected with the Nth control signal K<N>The grid of the Nth PMOS switching tube is connected with the inverted signal Kb of the Nth control signal<N>The 1 st to Nth control signals form a control signal sequence K<N:1>The inverted signal from the 1 st control signal to the N th control signal constitutes the inverted control signal sequence Kb<N:1>，
Figure BDA0003394569470000081
Referring to fig. 4, the impedance matching detection circuit 12 of the adaptive impedance matching circuit of the present invention includes,
the resistance voltage division circuit comprises a preset number of voltage division resistors connected between a power supply voltage end VDD and a ground end GND, and a first reference voltage division Vr _ up, a second reference voltage division Vr _ dn and a third reference voltage division Vr _ md are respectively led out from points connected among different voltage division resistors;
a first comparator CMP1 for comparing the signal at the output terminal SIG _ pad with the first reference divided voltage Vr _ up to generate a first comparison signal SU;
a second comparator CMP2 comparing the signal at the output terminal SIG _ pad with the second reference divided voltage Vr _ dn to generate a second comparison signal SD;
and an exclusive or gate XOR1 for performing exclusive or operation on the first comparison signal SU and the second comparison signal SD to output an impedance matching detection signal SO.
The impedance match detection circuit 12 further includes,
a first MOS transistor M1 controllably connected between a current source IB1 and a first reference node J1 under control of an impedance match detection signal SO;
a first capacitor C1 connected between the first reference node J1 and the ground GND;
a second MOS transistor M2 controllably connected between the first reference node J1 and the ground GND under the action of a first control signal;
a third comparator CMP3 comparing the third reference divided voltage Vr _ md with the voltage of the first reference node VC1 to generate a third comparison signal SM;
a nor gate OR1 for performing a nor logic operation on the third comparison signal SM and the first control signal to generate a first logic signal;
an AND gate AND1 for performing an AND operation on the first logic signal AND the clock signal CLK to generate a second logic signal CKC;
a counter 121, a clock terminal CK of the counter 121 is connected to the second logic signal CKC and the trigger terminal
Figure BDA0003394569470000091
Connecting an enable signal EN, and outputting a count value Nout by the counter 121;
the first inverter INV1 connects the enable signal EN to the control terminal of the second MOS transistor M2.
For the condition of poor matching, the impedance matching detection circuit of the invention has undershoot or overshoot of the time domain signal of the output end SIG _ pad, at this time, the change of the first comparison signal SU and the second comparison signal SD is almost synchronous, and the impedance matching detection signal SO output by the XOR gate is a signal with the length of 0; for a good matching situation, the first comparison signal SU and the second comparison signal SD have a precedence relationship in their transitions, the signal SO output after the time difference passes through the XOR gate is a pulse signal, the first MOS transistor M1 is turned on when the impedance matching detection signal SO is a pulse signal, and the current source IB1 charges the first capacitor C1. With reference to fig. 4 and 5, the counter counts from 0 to 6 as an example of an important node waveform diagram, the enable signal EN controls the impedance matching detection circuit to be reset and enabled, when the enable signal EN is equal to 0, the second MOS transistor M2 is turned on, charges on the first capacitor C1 are all discharged to the ground GND, the voltage VC1 of the first reference node J1 is 0, when the enable signal EN is equal to 1, the current source IB1 is allowed to charge the first capacitor C1 through the first MOS transistor M1, the enable signal EN is also used for resetting the counter 121 and controlling the input clock of the counter 121 at the same time, when the enable signal EN is equal to 0, the counter 121 is reset to 0, when EN jumps from 0 to 1, the external clock CLK can be transmitted to the clock input terminal CK of the counter 121, the counter can count, the count time of the counter 121 from 0, depending on how long the voltage 1 of the first reference node J1 needs to reach the third reference voltage Vr, when VC1< Vr _ md, counter 121 continues to receive the second logic signal CKC and counts. When the first capacitor C1 is gradually charged, and the voltage VC1 of the first reference node J1 rises to the third reference voltage Vr _ md, the counter 121 stops counting, at this time, the count value Nout of the counter 121 reflects the charging time, and the larger the count value Nout is, the longer the charging time is, and the narrower the impedance matching detection signal SO is; conversely, the smaller Nout, the shorter the charging time, and the wider the impedance matching detection signal SO. The magnitude of the count value Nout is equivalent to how well the impedance matching is performed.
In fig. 4, four voltage dividing resistors R1, R2, R3 and R4 are connected between a power supply voltage terminal VDD and a ground terminal GND, a first reference voltage divider Vr _ up is led out from a point where the first voltage dividing resistor R1 is connected with the second voltage dividing resistor R2, a second reference voltage divider Vr _ dn is led out from a point where the third voltage dividing resistor R3 is connected with the fourth voltage dividing resistor R4, and a third reference voltage divider Vr _ md is led out from a point where the second voltage dividing resistor R2 is connected with the third voltage dividing resistor R3; preferably, the first reference divided voltage Vr _ up is VDD × 2/5, the second reference divided voltage Vr _ dn is VDD × 3/5, and the third reference divided voltage Vr _ md is VDD × 1/2.
The input clock of the invention is CLK, through traversing all combinations of control signal sequences K < N:1> -00 … 0-11 … 1, the impedance matching detection circuit 12 sequentially judges the matching condition of the impedance of the transmitting end and the impedance of the transmission line, selects the optimal value of the control signal sequence K < N:1>, and finally gives the optimal value to the variable impedance transmitting circuit, thereby realizing the purpose of automatic impedance adjustment.
The transmission line of the present invention is a microstrip transmission line having a characteristic impedance of 50 ohms, or 75 ohms, or 100 ohms. The output of the PHY chip is a port that transmits MII and/or RMII and/or GMII and/or RGMII signals.
Fig. 6 is a working method of the adaptive impedance matching circuit of the PHY chip of the present invention, including the following steps:
step S1, setting all control signal sequences formed by the 1 st control signal to the Nth control signal to be zero;
step S2, adding 1 to the control signal sequence,
step S3, the output signal SIG _ tx is sent out through the output terminal SIG _ pad of the PHY chip;
step S4, enabling the impedance matching detection circuit through the enabling signal, and recording the corresponding count value output by the counter;
step S5, judging whether all the control signal sequences are 1, if all the control signal sequences are 1, executing step S6, if not all the control signal sequences are 1, repeating step S2;
in step S6, a control signal sequence having the smallest count value is selected from all the count values and transmitted to the variable impedance transmission circuit.
The variable impedance transmitting circuit and the impedance matching detection circuit are matched with each other, after the operation is started, the control signal sequence K < N:1> is firstly set to 00 … 0, then the addition operation of thermometer coding is carried out, namely the control signal sequence K < N:1> is equal to 00 … 1, and the output signal SIG _ tx transmits signals to the outside through the output end SIG _ pad of the PHY chip; enabling the impedance matching detection circuit by the enable signal, allowing the counter to start counting, recording a corresponding count value Nout output by the counter, determining whether the control signal sequence K < N:1> is equal to 11 … 1, if not, repeating step S2, when the control signal sequence K < N:1> is equal to 11 … 1, that is, the control signal sequence K < N:1, finding a control signal sequence with the minimum count value Nout after traversing all numerical combinations, and giving the control signal sequence to the variable impedance transmitting circuit as an output impedance control value in the optimal matching state. The invention can adaptively match microstrip transmission lines with different characteristic impedances and optimize the signal transmission quality between the PHY chip and the MAC chip.
While the specification concludes with claims defining exemplary embodiments of particular structures for practicing the invention, it is believed that other modifications will be made in the spirit of the invention. While the above invention sets forth presently preferred embodiments, these are not intended as limitations.
Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above description. Therefore, the appended claims should be construed to cover all such variations and modifications as fall within the true spirit and scope of the invention. Any and all equivalent ranges and contents within the scope of the claims should be considered to be within the intent and scope of the present invention.

Claims (10)

  1. The self-adaptive impedance matching circuit of the PHY chip is characterized in that the output end of the transmitting end of the PHY chip is connected with an MAC chip interface through a transmission line, the PHY chip comprises,
    the variable impedance transmitting circuit transmits an output signal from the output end after passing through a main driver of variable impedance, and the main driver adjusts the impedance value of the variable impedance under the action of a control signal sequence;
    and the impedance matching detection circuit is connected with the output end of the variable impedance sending circuit, converts the impedance matching state of the signal of the output end and the transmission line into a count value under the action of an enable signal and a clock signal, and selects the control signal sequence according to the count value.
  2. 2. The adaptive impedance matching circuit of claim 1, wherein the main driver comprises,
    the N PMOS tube branches are controllably connected between a power supply voltage end and the output end in parallel and comprise N PMOS driving tubes and N PMOS switching tubes, and each PMOS driving tube is connected with one PMOS switching tube;
    the N NMOS tube branches are controllably connected between the output end and a grounding end in parallel and comprise N NMOS driving tubes and N NMOS switch tubes, and each NMOS driving tube is connected with one NMOS switch tube;
    the grid electrode of each PMOS switching tube and the grid electrode of each NMOS switching tube are connected with a control signal, the grid electrode of the ith NMOS switching tube is connected with the ith control signal, the grid electrode of the ith PMOS switching tube is connected with the negation signal of the ith control signal, i belongs to [1, N ], and the control signal sequence is formed by the 1 st control signal connected with the grid electrode of the 1 st NMOS switching tube and the Nth control signal connected with the grid electrode of the Nth NMOS switching tube.
  3. 3. The adaptive impedance matching circuit of claim 2, wherein the variable impedance transmitting circuit further comprises a pre-driver inverter, an input terminal of the pre-driver inverter is connected to the output signal, and an output terminal of the pre-driver inverter is connected to the gates of the PMOS driver transistor and the NMOS driver transistor.
  4. 4. The adaptive impedance matching circuit of claim 2,
    the source end of each PMOS driving tube is connected with the power supply voltage end, the drain end of each PMOS driving tube is connected with the source end of the PMOS switching tube, and the drain end of each PMOS switching tube is connected with the output end;
    the drain end of each NMOS switch tube is connected with the output end, the source end of each NMOS switch tube is connected with the drain end of each NMOS driving tube, and the source end of each NMOS switch tube is connected with the grounding end.
  5. 5. The adaptive impedance matching circuit of claim 2, wherein the impedance match detection circuit comprises,
    the resistance voltage division circuit comprises a preset number of voltage division resistors connected between the power supply voltage end and the grounding end, and a first reference voltage division, a second reference voltage division and a third reference voltage division are respectively led out from different points connected among the voltage division resistors;
    the first comparator compares the voltage of the output end with the first reference divided voltage to generate a first comparison signal;
    the second comparator compares the voltage of the output end with the second reference divided voltage to generate a second comparison signal;
    and the exclusive-OR gate is used for carrying out exclusive-OR operation on the first comparison signal and the second comparison signal and outputting an impedance matching detection signal.
  6. 6. The adaptive impedance matching circuit of claim 5, wherein the impedance match detection circuit comprises,
    a first MOS transistor controllably connected between a current source and a first reference node under control of the impedance matching detection signal;
    a first capacitor connected between the first reference node and a ground terminal;
    the second MOS tube is controllably connected between the first reference node and a grounding end under the action of a first control signal;
    a third comparator for comparing the third reference divided voltage with the voltage of the first reference node to generate a third comparison signal;
    a nor gate for performing a nor logic operation on the third comparison signal and the first control signal to generate a first logic signal;
    the AND gate is used for carrying out AND logic operation on the first logic signal and the clock signal to generate a second logic signal;
    and the clock end of the counter is connected with the second logic signal, the trigger end of the counter is connected with an enabling signal, and the counter outputs a count value.
  7. 7. The adaptive impedance matching circuit of claim 6, comprising a first inverter connecting the enable signal to the control terminal of the second MOS transistor.
  8. 8. The adaptive impedance matching circuit of claim 1, wherein the transmission line is a microstrip transmission line, and wherein the transmission line has a characteristic impedance of 50 ohms, or 75 ohms, or 100 ohms.
  9. 9. The adaptive impedance matching circuit of claim 1, wherein the output of the PHY chip is a port that transmits MII and/or RMII and/or GMII and/or RGMII signals.
  10. A method for operating an adaptive impedance matching circuit of a PHY chip, the adaptive impedance matching circuit being used in the PHY chip of any one of claims 1 to 9, the method comprising the steps of:
    step S1, setting all control signal sequences formed by the 1 st control signal to the Nth control signal to be zero;
    step S2, adding 1 to the control signal sequence,
    step S3, the output signal is sent out through the output end of the PHY chip;
    step S4, enabling the impedance matching detection circuit through the enabling signal, and recording the corresponding count value output by the counter;
    step S5, judging whether all the control signal sequences are 1, if all the control signal sequences are 1, executing step S6, if not all the control signal sequences are 1, repeating step S2;
    in step S6, a control signal sequence corresponding to the minimum count value is selected from all the count values and sent to the variable impedance transmission circuit.
CN202111479974.9A 2021-12-06 2021-12-06 Adaptive impedance matching circuit of PHY chip and working method thereof Pending CN114385535A (en)

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CN115001878A (en) * 2022-05-07 2022-09-02 联芸科技(杭州)股份有限公司 Driver of Ethernet transceiver, control method thereof and Ethernet transceiver

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CN115001878A (en) * 2022-05-07 2022-09-02 联芸科技(杭州)股份有限公司 Driver of Ethernet transceiver, control method thereof and Ethernet transceiver

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