CN115000157A - Thin film transistor, display panel, display device and preparation method - Google Patents

Thin film transistor, display panel, display device and preparation method Download PDF

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Publication number
CN115000157A
CN115000157A CN202210693368.5A CN202210693368A CN115000157A CN 115000157 A CN115000157 A CN 115000157A CN 202210693368 A CN202210693368 A CN 202210693368A CN 115000157 A CN115000157 A CN 115000157A
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substrate
layer
metal oxide
pole
oxide layer
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刘凤娟
王东方
卢昱行
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

The embodiment of the application provides a thin film transistor, a display panel, a display device and a preparation method, wherein the thin film transistor comprises: a substrate; a first pole disposed at one side of the substrate; the first metal oxide layer is arranged on one side of the first pole, which is far away from the substrate; the active layer is arranged on one side, away from the substrate, of the first metal oxide layer and comprises a channel region, a drain region and a source region, the drain region and the source region are located at two ends of the channel region, and the drain region is in contact with the first metal oxide layer; the grid electrode is arranged on one side of the active layer, which is far away from the substrate, and an orthographic projection area of the grid electrode on the substrate corresponds to an orthographic projection area of the channel region on the substrate; and the second pole is arranged on one side of the active layer, which is far away from the substrate, and is in contact with the source region. According to the technical scheme, the bottom metal in the first pole can be prevented from being exposed in the over-etching process, so that the surface oxidation of the first pole is avoided, and the good lap joint of the active layer and the first pole is realized.

Description

Thin film transistor, display panel, display device and preparation method
Technical Field
The application relates to the technical field of display, in particular to a thin film transistor, a display panel, a display device and a preparation method.
Background
In the related art, as shown in fig. 1, in order to enable the active layer 1 to contact the metal electrode 2, the insulating layer 3 needs to be dry-etched. In order to ensure the etching effect, a certain degree of over-etching is performed. However, over-etching may cause copper or aluminum of the metal electrode 2 to be exposed, and direct contact of copper or aluminum of the metal electrode 2 with the active layer 1 may cause interface oxidation. In addition, in the process of converting the active layer 1 into a conductor, only the upper portion of the active layer 1 is usually converted into a conductor, and the lower portion of the active layer 1 still has a large resistance, so that it is difficult to achieve good bonding between the active layer 1 and the metal electrode 2.
Disclosure of Invention
Embodiments of the present application provide a thin film transistor, a display panel, a display device and a manufacturing method, so as to solve or alleviate one or more technical problems in the prior art.
As a first aspect of embodiments of the present application, an embodiment of the present application provides a thin film transistor, including:
a substrate;
a first pole disposed at one side of the substrate;
the first metal oxide layer is arranged on one side of the first pole, which is far away from the substrate;
the active layer is arranged on one side, away from the substrate, of the first metal oxide layer and comprises a channel region, a drain region and a source region, wherein the drain region and the source region are located at two ends of the channel region;
the grid electrode is arranged on one side of the active layer, which is far away from the substrate, and an orthographic projection area of the grid electrode on the substrate corresponds to an orthographic projection area of the channel region on the substrate;
and the second pole is arranged on one side of the active layer, which is far away from the substrate, and is in contact with the source region.
In one embodiment, the first metal oxide layer includes at least one of indium tin oxide, indium zinc oxide, indium gallium zinc oxide, and indium gallium tin oxide.
In one embodiment, the resistance between the end of the drain region remote from the source region and the second pole is R, wherein R is 1000 Ω ≦ 2000 Ω.
In one embodiment, the thin film transistor further includes: the dielectric layer is arranged on one side, away from the substrate, of the first metal oxide layer and covers the first metal oxide layer and the substrate, at least one first through hole is formed in the dielectric layer, at least part of the first metal oxide layer is exposed through the first through hole, and the drain region is in contact with the first metal oxide layer through the first through hole; and the grid insulating layer is arranged between the active layer and the grid electrode.
In one embodiment, an orthographic projection area of the gate insulating layer on the substrate corresponds to an orthographic projection area of the gate electrode on the substrate, and the gate insulating layer is spaced from both the first via hole and the second electrode.
In one embodiment, the gate insulating layer covers the dielectric layer, the drain region and the channel region, a second via hole is formed in the gate insulating layer, at least a portion of the source region is exposed through the second via hole, and the second electrode is in contact with the source region through the second via hole.
In one embodiment, the thin film transistor further includes: the metal part is arranged at intervals with the same layer of the first electrode, and an orthographic projection area of the metal part on the substrate corresponds to an orthographic projection area of the channel region on the substrate; and the second metal oxide layer is arranged on one side of the corresponding metal part, which is far away from the substrate, and is arranged on the same layer as the first metal oxide layer.
In one embodiment, the first pole comprises a layer of pure metallic material arranged on one side of the substrate and a layer of alloying material arranged on the side of the layer of pure metallic material facing away from the substrate.
As a second aspect of the present application, embodiments of the present application provide a display panel including a thin film transistor according to any one of the above-described aspects of the present application.
As a third aspect of the present application, embodiments of the present application provide a display device including the display panel according to the above-described second aspect of the present application.
As a fourth aspect of the present application, an embodiment of the present application provides a method for manufacturing a thin film transistor, including:
forming a substrate;
forming a first pole on one side of a substrate;
forming a first metal oxide layer on one side of the first pole, which is far away from the substrate;
forming an active layer on one side of the first metal oxide layer, which is far away from the substrate, wherein the active layer comprises a channel region, a drain region and a source region, the drain region and the source region are positioned at two ends of the channel region, and the drain region is in contact with the first metal oxide layer;
forming a grid on one side of the active layer, which is far away from the substrate, wherein an orthographic projection area of the grid on the substrate corresponds to an orthographic projection area of the channel region on the substrate;
a second pole is formed on the side of the active layer facing away from the substrate, and the second pole is in contact with the source region.
In one embodiment, forming a first pole on a side of the substrate and a first metal oxide layer on a side of the first pole facing away from the substrate includes:
depositing a metal layer on one side of the substrate;
depositing a metal oxide layer on the side of the metal layer facing away from the substrate;
etching the metal oxide layer to form a first metal oxide layer;
the metal layer is etched to form a first pole.
In one embodiment, the method of making further comprises:
forming a metal part, wherein the metal part and the first electrode are arranged at intervals on the same layer, and an orthographic projection area of the metal part on the substrate corresponds to an orthographic projection area of the channel area on the substrate;
and forming a second metal oxide layer on one side of the metal part, which is far away from the substrate, wherein the second metal oxide layer and the first metal oxide layer are arranged on the same layer.
By adopting the technical scheme, the embodiment of the application can avoid exposing the bottom metal in the first pole in the over-etching process, thereby avoiding the surface oxidation of the first pole caused by the direct contact of the active layer and the bottom metal in the first pole and realizing the good lap joint of the active layer and the first pole.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present application will be readily apparent by reference to the drawings and the following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.
Fig. 1 is a schematic view showing a structure of a related art thin film transistor;
fig. 2 is a schematic view showing a process of measuring a resistance of a thin film transistor according to the related art;
FIG. 3 is a schematic view showing a distribution of thin film transistors on glass in the related art;
FIG. 4 is a table showing the lap resistance of a plurality of test points in three glass panels according to the related art;
fig. 5 shows a schematic structural diagram of a thin film transistor according to a first embodiment of the present application;
fig. 6 is a schematic structural view showing a thin film transistor according to a second embodiment of the present application;
fig. 7 is a schematic structural view showing a thin film transistor according to a third embodiment of the present application;
fig. 8 is a schematic structural diagram of a thin film transistor according to a fourth embodiment of the present application.
Description of reference numerals:
100: a thin film transistor;
110: a substrate; 120: a first pole; 130: a first metal oxide layer; 140: an active layer; 150: a gate electrode; 160: a second pole; 170: a gate insulating layer; 180: a dielectric layer; 190: a metal part; 101: a second metal oxide layer; 102: a first insulating layer; 103: an organic planarization layer.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present application. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
In the related art, as shown in fig. 1, an active layer 1 of a thin film transistor is overlapped on an upper surface of a metal electrode 2, so that a footprint of the thin film transistor can be reduced. The metal electrode 2 generally has a composite structure of molybdenum (Mo) alloy/copper (Cu), molybdenum alloy/copper/molybdenum alloy, or molybdenum alloy/aluminum (Al). During the via etching, the insulating layer 3 such as silicon oxide and silicon nitride is dry etched. In order to ensure the etching effect, a certain degree of over-etching is set. During the over-etching process, the molybdenum alloy on the top layer of the metal electrode 2 is etched away, and copper or aluminum is exposed. Copper or aluminum is in direct contact with an oxide such as Indium Gallium Zinc Oxide (IGZO) of the active layer 1, and a large amount of oxygen is introduced during the deposition of IGZO, which causes the interface of the metal electrode 2 to be oxidized. The active layer 1 is made conductive by making the IGZO conductive through the upper insulating layer, and the portion made conductive is the upper half portion of the IGZO and has a thickness of about 150A to 200A. The lower half of the IGZO still has the potential to be more resistive and more difficult to achieve a good lap joint.
Fig. 2 is a schematic diagram illustrating a process of measuring the overlap resistance of the thin film transistor shown in fig. 1. As shown in fig. 2, the following steps may be included:
the method comprises the following steps: and depositing a metal layer on the front surface of the substrate by magnetron sputtering and other processes, and then coating, exposing, developing and etching the photoresist to form the metal electrode.
Step two: and depositing a dielectric layer on the metal electrode.
Step three: a plurality of via holes are formed in the dielectric layer.
Step four: and depositing an organic semiconductor thin film layer on the whole surface of the dielectric layer, enabling the organic semiconductor thin film layer to be in contact with the metal electrode through the through hole, and then coating, exposing, developing and etching the photoresist to form an active layer.
Step five: the source electrode is lapped on the metal layer.
Step six: and testing the resistance between the source electrode and the active layer, wherein the conduction path is the upper surface of the active layer → the lower surface of the active layer → the metal electrode → the source electrode.
The metal electrode and the source electrode are both metal layers, contact resistance is small, and resistance between the source electrode and the active layer mainly depends on resistance between the active layer and the metal electrode.
Illustratively, three glass panels (numbered 11, 12 and 13, respectively) can be tested, each glass panel tests nine points, and the specific data is shown in fig. 4, where the resistance between the source electrode and the active layer is too large, which indicates that the overlap resistance of the active layer and the metal electrode is too large and much larger than the standard value (the standard resistance value is less than 5000 Ω).
In order to solve the above technical problem, the present application provides a thin film transistor. As shown in fig. 5, the thin film transistor 100 according to the embodiment of the first aspect of the present application includes: a substrate 110, a first pole 120, a first metal oxide layer 130, an active layer 140, a gate 150, and a second pole 160.
Specifically, the first pole 120 is disposed on one side of the substrate 110, the first metal oxide layer 130 is disposed on one side of the first pole 120 away from the substrate 110, the active layer 140 is disposed on one side of the first metal oxide layer 130 away from the substrate 110, the active layer 140 includes a channel region and a drain region and a source region located at two ends of the channel region, and the drain region is in contact with the first metal oxide layer 130. The gate 150 is disposed on a side of the active layer 140 facing away from the substrate 110, an orthographic projection area of the gate 150 on the substrate 110 corresponds to an orthographic projection area of the channel region on the substrate 110, the second electrode 160 is disposed on a side of the active layer 140 facing away from the substrate 110, and the second electrode 160 contacts the source region.
Exemplarily, in conjunction with fig. 5, the thin film transistor 100 may be a top gate type thin film transistor. The first pole 120 is located on the upper surface of the substrate 110, and the first metal oxide layer 130 is located on the upper surface of the first pole 120. The thin film transistor 100 may further include a first insulating layer 102 and an organic planarization layer 103 stacked, the first insulating layer 102 being between the active layer 140 and the organic planarization layer 103, and the first insulating layer 102 covering the gate electrode 150 and the active layer 140. Through insulating vias are formed on the first insulating layer 102 and the organic planarization layer 103, and the active region of the active layer 140 may be exposed through the insulating vias such that the second electrode 160 contacts the active region. One of the first pole 120 and the second pole 160 is a drain, and the other of the first pole 120 and the second pole 160 is a source, for example, the first pole 120 may be a drain, and the second pole 160 may be a source. The drain and source regions of the active layer 140 may be conductive regions, and the channel region may be a semiconductor region.
According to the thin film transistor 100 of the embodiment of the application, the first metal oxide layer 130 is disposed on the side of the first electrode 120 away from the substrate 110, so that the electrical connection between the active layer 140 and the first electrode 120 is ensured, an effective protection effect is achieved, and the bottom metal in the first electrode 120 is prevented from being exposed in the over-etching process, so that the surface oxidation of the first electrode 120 caused by the direct contact between the active layer 140 and the bottom metal in the first electrode 120 is avoided, and the good overlapping between the active layer 140 and the first electrode 120 is realized.
In one embodiment, the first metal oxide layer 130 may include Indium Tin Oxide (ITO), indium zinc oxide ((IZO), indium oxide (In) 2 O 3 ) At least one of Indium Gallium Zinc Oxide (IGZO) and Indium Gallium Tin Oxide (IGTO). With such an arrangement, the first metal oxide layer 130 is a metal oxide layer with high indium content and low oxygen content, and in the process of performing a post-annealing process after the active layer 140 is deposited, since the drain region of the active layer 140 is in contact with the first metal oxide layer 130, oxygen and carriers in the film layer can be diffused after a temperature process, so that the oxygen content in the lower layer of the active layer 140 is reduced, and the carrier concentration is increased, thereby effectively reducing the resistance at the lower part of the active layer 140 and realizing good lap joint of the active layer 140 and the first pole 120.
In one embodiment, the resistance between the end of the drain region remote from the source region and the second pole 160 is R, where 1000 Ω R2000 Ω. For example, in the case where the thin film transistor 100 is applied to a display panel, in a display stage of the display panel, when a voltage is applied, the channel region is controlled to be turned on, and an applied electrical signal may be transferred from one of the first and second electrodes 120 and 160 to the active layer 140, then transferred to the other of the first and second electrodes 120 and 160 through the active layer 140, and finally transferred to the pixel electrode layer, thereby implementing a display function of the display panel.
Therefore, by making R1000 Ω ≦ R2000 Ω, the overlap resistance between the active layer 140 and the first electrode 120 is small, and the conduction reliability between the active layer 140 and the first electrode 120 and between the active layer 140 and the second electrode 160 can be ensured, thereby ensuring the fast and normal operation of the thin film transistor 100.
In one embodiment, as shown in fig. 5, the thin film transistor 100 further includes a dielectric layer 180 and a gate insulating layer 170. The dielectric layer 180 is disposed on one side of the first metal oxide layer 130, and the dielectric layer 180 covers the first metal oxide layer 130 and the substrate 110. At least one first via hole is formed on the dielectric layer 180, at least a portion of the first metal oxide layer 130 is exposed through the first via hole, and the drain region is in contact with the first metal oxide layer 130 through the first via hole. The gate insulating layer 170 is disposed between the active layer 140 and the gate electrode 150.
Illustratively, the drain region may include a first sub-region, a second sub-region and a third sub-region, the first sub-region and the third sub-region are respectively located at two ends of the second sub-region, wherein the first sub-region and the third sub-region overlap the upper surface of the dielectric layer 180, and the third sub-region is connected to the channel region. The second sub-region is located at the first via and overlaps the first metal oxide layer 130. Wherein the dielectric layer 180 and the gate insulating layer 170 may independently include a material selected from the group consisting of SiO x 、SiN x SiON, and SiON, but not limited thereto.
Therefore, through the arrangement, the dielectric layer 180 can enable the film layer structure to be more flat and stable, deposition of the active layer 140 is achieved, the gate insulating layer 170 can separate the gate 150 from the channel region, and reliability of the thin film transistor 100 is improved.
In one embodiment, as shown in fig. 5 and 6, an orthographic projection area of the gate insulating layer 170 on the substrate 110 corresponds to an orthographic projection area of the gate electrode 150 on the substrate. For example, the orthographic projection of the gate electrode 150 on the substrate 110 may be within the orthographic projection of the gate insulating layer 170 on the substrate 110, the gate insulating layer 170 being spaced apart from the first via and the second pole 160. In the example of fig. 5 and 6, in the preparation process, after the gate electrode 150 is etched, the gate insulating layer 170 is etched away together, so that the orthographic projection range of the gate insulating layer 170 on the substrate 110 is substantially equal to the orthographic projection range of the gate electrode 150 on the substrate 110, and at this time, the first insulating layer 102 may cover the gate electrode 150, the active layer 140 and the dielectric layer 180. Thus, the film structure of the thin film transistor 100 is simplified while the overlap resistance between the active layer 140 and the first electrode 120 is kept small.
In another embodiment, referring to fig. 7 and 8, the gate insulating layer 170 covers the dielectric layer 180, the drain region and the channel region, a second via hole is formed on the gate insulating layer 170, at least a portion of the source region is exposed through the second via hole, and the second electrode 160 contacts the source region through the second via hole. The difference from the above embodiment is that, except for the second via hole region, the gate insulating layer 170 is disposed over the entire surface, for example, during the preparation process, the etching step of the gate insulating layer 170 is omitted, the outer dimension of the gate insulating layer 170 may be equal to the outer dimension of the substrate 110, and the orthographic projection range of the gate insulating layer 170 on the substrate 110 is much larger than the orthographic projection range of the gate electrode 150 on the substrate 110. The drain and source regions may be conductively formed by a deposition process or an ion implantation process. Wherein the second via is in communication with the insulated via and the second pole 160 contacts the source region through the insulated via and the second via.
Therefore, the manufacturing process of the thin film transistor 100 can be simplified, and the production efficiency can be effectively improved while the excellent performance of the thin film transistor 100 is ensured.
In one embodiment, in conjunction with fig. 6 and 8, the thin film transistor 100 may further include a metal part 190 and a second metal oxide layer 101. The metal parts 190 and the first electrodes 120 are disposed at intervals in the same layer, an orthogonal projection area of the metal part 190 on the substrate 110 corresponds to an orthogonal projection area of the channel region on the substrate 110, the second metal oxide layer 101 is disposed on a side of the corresponding metal part 190 away from the substrate 110, and the second metal oxide layer 101 and the first metal oxide layer 130 are disposed in the same layer. With this configuration, on one hand, the metal portion 190 and the channel region may face each other, and the metal portion 190 and the gate 150 may be respectively located at two sides of the channel region, so that a dual gate structure may be formed. On the other hand, the metal part 190 can play an effective role in shading light to prevent the light from directly irradiating the channel region, thereby further improving the performance of the thin film transistor 100.
In an alternative embodiment, the first pole 120 includes a layer of pure metal material and a layer of alloy material, and the layer of pure metal material may be disposed on a side of the substrate 110 and the layer of alloy material is disposed on a side of the layer of pure metal material facing away from the substrate 110.
Illustratively, the layer of alloy material may be located on an upper surface of the layer of pure metallic material. The alloy material layer may be a molybdenum alloy layer, in which case the pure metal material layer may be a copper layer, an aluminum layer, etc., in which case the first electrode 120 is a molybdenum alloy/copper or molybdenum alloy/aluminum composite layer. Alternatively, the alloy material layer may be an aluminum alloy layer, in which case the pure metal material layer may be an aluminum layer, and in which case the first pole 120 is an aluminum alloy/aluminum. The first pole 120 can also include a third material layer between the layer of material that can be a pure metal and the substrate 110, for example where the first pole 120 can be a molybdenum alloy/copper/molybdenum alloy composite layer. Of course, the pure metal material layer and the alloy material layer may be other materials, and the present invention is not limited thereto.
Therefore, the first metal oxide layer 130 can be disposed on the alloy material layer, so that a dual protection effect can be achieved, and metals such as aluminum or copper in the first pole 120 are thoroughly prevented from being exposed in an etching process, so that the interface oxidation of the first pole 120 is avoided, and the overlap resistance between the active layer 140 and the first pole 120 is effectively reduced.
A display panel according to an embodiment of the second aspect of the present application comprises a thin film transistor 100 according to any of the above-described embodiments of the first aspect of the present application. For example, the Display panel may be an LCD (Liquid Crystal Display), an AMOLED (Active-matrix organic light-emitting diode), or the like.
According to the display panel of the embodiment of the application, by using the thin film transistor 100, the surface oxidation of the first electrode 120 caused by the direct contact between the active layer 140 and the bottom metal in the first electrode 120 can be avoided, and the good overlapping between the active layer 140 and the first electrode 120 is realized, so that the display effect of the display panel is improved.
A display device according to an embodiment of the third aspect of the present application comprises a display panel according to an embodiment of the second aspect of the present application described above.
According to the display device of the embodiment of the application, by adopting the display panel, the overlap resistance between the active layer 140 and the first pole 120 can be reduced, so that the long-term reliability of the display device is improved.
The method for manufacturing the thin film transistor 100 according to the fourth aspect of the present application includes:
forming a substrate 110;
forming a first pole 120 on one side of the substrate 110;
forming a first metal oxide layer 130 on a side of the first pole 120 facing away from the substrate 110;
forming an active layer 140 on a side of the first metal oxide layer 130 facing away from the substrate 110, the active layer 140 including a channel region and a drain region and a source region at both ends of the channel region, the drain region being in contact with the first metal oxide layer 130;
forming a gate 150 on a side of the active layer 140 facing away from the substrate 110, wherein an orthographic projection area of the gate 150 on the substrate 110 corresponds to an orthographic projection area of the channel region on the substrate 110;
a second pole 160 is formed on the side of the active layer 140 facing away from the substrate 110, the second pole 160 being in contact with the source region.
Therefore, by forming the first metal oxide layer 130 on the side of the first pole 120 away from the substrate 110, while the electrical connection between the active layer 140 and the first pole 120 is ensured, an effective protection effect can be achieved, and the bottom metal in the first pole 120 is prevented from being exposed in the over-etching process, so that the surface oxidation of the first pole 120 caused by the direct contact between the active layer 140 and the bottom metal in the first pole 120 is avoided, and the good lap joint between the active layer 140 and the first pole 120 is realized.
In one embodiment, forming the first pole 120 on a side of the substrate 110 and forming the first metal oxide layer 130 on a side of the first pole 120 facing away from the substrate 110 includes:
depositing a metal layer on one side of the substrate 110;
oxygen-free deposition of a metal oxide layer on the side of the metal layer facing away from the substrate 110;
etching the metal oxide layer to form a first metal oxide layer 130;
the metal layer is etched to form a first pole 120.
Illustratively, the first metal oxide layer 130 includes at least one of indium tin oxide, indium zinc oxide, indium gallium zinc oxide, and indium gallium tin oxide. Patterning, photoresist coating, and photoresist stripping may be performed before etching the first metal oxide layer 130, after etching the first metal oxide. Then, a dielectric layer 180 is deposited, photoresist coating is performed, and first via dry etching is performed.
During the dry etching process, the selectivity of etching the dielectric layer 180 (e.g., silicon oxide layer, silicon nitride layer, etc.) and etching the first metal oxide layer 130 is relatively high, so that the first metal oxide layer 130 can remain on top of the first electrode 120, and the active layer 140 is prevented from directly contacting the metal under the first metal oxide layer 130. Then, an active layer 140 (e.g., an oxide semiconductor layer such as IGZO) is deposited, patterning, photoresist coating, and wet etching are performed, and a post annealing process is performed in which the active layer 140 at the first via hole is brought into contact with the first metal oxide layer 130. After the temperature process, oxygen and carriers in the film layer are diffused, the oxygen content at the lower portion of the active layer 140 is reduced, defects are increased, and the carrier concentration is increased. Then, the gate insulating layer 170 and the gate electrode 150 are deposited, and patterning, photoresist coating, etching of the gate electrode 150, and etching of the gate insulating layer 170 are performed. The first insulating layer 102 and the organic planarization layer 103 are then deposited and patterned. Finally, an electrode layer is deposited and patterned to form the second pole 160.
Therefore, under the condition of not increasing a mask, the risk of exposing bottom metal can be avoided, the overall resistance of the lap joint of the active layer 140 is ensured, and the overall design of the thin film transistor 100 is optimized.
In one embodiment, the method of making further comprises:
forming a metal part 190, wherein the metal part 190 and the first electrode 120 are arranged at intervals on the same layer, and an orthographic projection area of the metal part 190 on the substrate 110 corresponds to an orthographic projection area of the channel region on the substrate 110;
a second metal oxide layer 101 is formed on a side of the metal part 190 facing away from the substrate 110, and the second metal oxide layer 101 is disposed in the same layer as the first metal oxide layer 130.
Other configurations of the thin film transistor 100, the display panel, the display device, and the method for manufacturing the thin film transistor 100 of the above embodiments may be adopted in various technical solutions known to those skilled in the art now and in the future, and will not be described in detail herein.
In the description of the present specification, it is to be understood that the terms "central," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and to simplify the description, but are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are not to be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and encompass, for example, both fixed and removable connections or integral parts thereof; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
The above disclosure provides many different embodiments or examples for implementing different structures of the application. The components and arrangements of specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present application, and these should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (13)

1. A thin film transistor, comprising:
a substrate;
a first pole disposed on one side of the substrate;
the first metal oxide layer is arranged on one side of the first pole, which is far away from the substrate;
the active layer is arranged on one side, away from the substrate, of the first metal oxide layer and comprises a channel region, a drain region and a source region, wherein the drain region and the source region are located at two ends of the channel region, and the drain region is in contact with the first metal oxide layer;
the grid electrode is arranged on one side of the active layer, which is far away from the substrate, and the orthographic projection area of the grid electrode on the substrate corresponds to the orthographic projection area of the channel region on the substrate;
and the second pole is arranged on one side of the active layer, which is far away from the substrate, and the second pole is in contact with the source region.
2. The thin film transistor of claim 1, wherein the first metal oxide layer comprises at least one of indium tin oxide, indium zinc oxide, indium gallium zinc oxide, and indium gallium tin oxide.
3. The thin film transistor according to claim 1, wherein a resistance between an end of the drain region remote from the source region and the second electrode is R, wherein R is 1000 Ω -2000 Ω.
4. The thin film transistor according to claim 1, further comprising:
the dielectric layer is arranged on one side, away from the substrate, of the first metal oxide layer and covers the first metal oxide layer and the substrate, at least one first through hole is formed in the dielectric layer, at least part of the first metal oxide layer is exposed through the first through hole, and the drain region is in contact with the first metal oxide layer through the first through hole;
and the grid insulating layer is arranged between the active layer and the grid electrode.
5. The thin film transistor according to claim 4, wherein an orthogonal projection region of the gate insulating layer on the substrate corresponds to an orthogonal projection region of the gate electrode on the substrate, and the gate insulating layer is spaced apart from both the first via hole and the second electrode.
6. The thin film transistor according to claim 4, wherein the gate insulating layer covers the dielectric layer, the drain region, and the channel region, a second via hole is formed in the gate insulating layer, at least a portion of the source region is exposed through the second via hole, and the second electrode is in contact with the source region through the second via hole.
7. The thin film transistor according to claim 1, further comprising:
the metal part and the first electrode layer are arranged at intervals, and an orthographic projection area of the metal part on the substrate corresponds to an orthographic projection area of the channel area on the substrate;
and the second metal oxide layer is arranged on one side of the metal part, which is far away from the substrate, and is arranged on the same layer as the first metal oxide layer.
8. The thin film transistor according to any of claims 1 to 7, wherein the first electrode comprises a layer of pure metal material and a layer of alloy material, the layer of pure metal material being provided on a side of the substrate and the layer of alloy material being provided on a side of the layer of pure metal material facing away from the substrate.
9. A display panel comprising the thin film transistor according to any one of claims 1 to 8.
10. A display device characterized by comprising the display panel according to claim 9.
11. A method for manufacturing a thin film transistor includes:
forming a substrate;
forming a first pole on one side of the substrate;
forming a first metal oxide layer on the side of the first pole facing away from the substrate;
forming an active layer on one side of the first metal oxide layer, which is far away from the substrate, wherein the active layer comprises a channel region, a drain region and a source region, the drain region and the source region are positioned at two ends of the channel region, and the drain region is in contact with the first metal oxide layer;
forming a grid electrode on one side of the active layer, which is far away from the substrate, wherein an orthographic projection area of the grid electrode on the substrate corresponds to an orthographic projection area of the channel area on the substrate;
forming a second pole on a side of the active layer facing away from the substrate, the second pole contacting the source region.
12. The method of claim 11, wherein forming a first pole on a side of the substrate and forming a first metal oxide layer on a side of the first pole facing away from the substrate comprises:
depositing a metal layer on one side of the substrate;
depositing a metal oxide layer on the side of the metal layer facing away from the substrate;
etching the metal oxide layer to form the first metal oxide layer;
and etching the metal layer to form the first pole.
13. The method of manufacturing according to claim 11, further comprising:
forming a metal part, wherein the metal part and the first electrode layer are arranged at intervals, and an orthographic projection area of the metal part on the substrate corresponds to an orthographic projection area of the channel region on the substrate;
and forming a second metal oxide layer on one side of the metal part, which is far away from the substrate, wherein the second metal oxide layer and the first metal oxide layer are arranged on the same layer.
CN202210693368.5A 2022-06-17 2022-06-17 Thin film transistor, display panel, display device and preparation method Pending CN115000157A (en)

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CN202210693368.5A CN115000157A (en) 2022-06-17 2022-06-17 Thin film transistor, display panel, display device and preparation method

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