CN115000121A - Phase change memory and preparation method thereof - Google Patents

Abstract

The application provides a phase change memory and a preparation method thereof, wherein the method comprises the following steps: forming a gating layer and a phase change storage layer connected with the gating layer in series; the gating layer comprises a first sublayer and a second sublayer; wherein the elements of the first sub-layer are selected from at least one gating layer element in a first element set, and the elements of the second sub-layer are selected from at least one gating layer element in a second element set; the mobility of each gating layer element in the first type element set is smaller than the mobility of each gating layer element in the second type element set. In the method provided by the application, the gate layer comprising the first sublayer and the second sublayer is formed, so that the mobility of each element in the first sublayer is smaller than that of each element in the second sublayer, and by utilizing the interface effect between the first sublayer and the second sublayer, local phase splitting and even crystallization caused by material diffusion are relieved, so that the high-temperature stability of the gate layer is improved, and the high-temperature stability of the phase change memory is improved.

Description

Phase change memory and preparation method thereof

Technical Field

The embodiment of the application relates to the technical field of semiconductor manufacturing, in particular to a phase change memory and a preparation method thereof.

Background

Phase-change Random Access Memory (PCRAM) utilizes joule heat generated under the action of electric pulses to make a storage medium mutually converted between a crystalline state (low resistance state) and an amorphous state (high resistance state), the resistance difference between the low resistance state and the high resistance state is obvious, so that information writing and erasing are realized, and information reading is realized by measuring the change of resistance.

The gate is a core component of the phase change memory and comprises a gate layer and electrodes positioned on the upper side and the lower side of the gate layer. The principle of the gate is that when an electric signal is applied, the gate layer is changed from a high-resistance state to a low-resistance state, and the gate is in an open state at the moment; when the electric signal is removed, the gating layer is changed from a low-resistance state to a high-resistance state, and the gating device is in a closed state at the moment. Currently, an Ovonic Threshold Switching (OTS) based on an amorphous chalcogenide material is commonly used as a gate layer of a phase change memory.

Therefore, it is still necessary to further improve the structure of the pass layer to improve the performance of the ovonic threshold switch, and thus the performance of the phase change memory.

Disclosure of Invention

In view of the above, embodiments of the present application provide a phase change memory and a method for manufacturing the same to solve at least one technical problem in the prior art.

In order to achieve the purpose, the technical scheme of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a method for manufacturing a phase change memory, where the method includes:

forming a gating layer and a phase change storage layer connected with the gating layer in series;

the gating layer comprises a first sublayer and a second sublayer; wherein the elements of the first sub-layer are selected from at least one gating layer element in a first element set, and the elements of the second sub-layer are selected from at least one gating layer element in a second element set; the mobility of each gating layer element in the first type element set is smaller than the mobility of each gating layer element in the second type element set.

In some embodiments, the number of layers of the first sublayer is greater than the number of layers of the second sublayer; the second sub-layer is located between two adjacent first sub-layers.

In some embodiments, the gating layer further comprises a third sublayer; wherein the elements of the third sublayer are selected from at least one gating layer element in a third class of element set; the mobility of each gating layer element in the first type element set and the mobility of each gating layer element in the third type element set are both smaller than the mobility of each gating layer element in the second type element set.

In some embodiments, the second sublayer is located between the first sublayer and the third sublayer.

In some embodiments, the gate layer elements include germanium, Ge, antimony, Sb, silicon, Si, selenium, Se, arsenic, As, tellurium, Te.

In a second aspect, an embodiment of the present application provides a phase change memory, including: the phase change memory device comprises a gating layer and a phase change memory layer connected with the gating layer in series;

the gating layer comprises a first sublayer and a second sublayer; the mobility of each element in the first sublayer is less than the mobility of each element in the second sublayer.

In some embodiments, the first sub-layers and the second sub-layers are alternately stacked.

In some embodiments, the gating layer further comprises a third sublayer; the mobility of each element in the third sublayer is less than the mobility of each element in the second sublayer; the second sublayer is located between the first sublayer and the third sublayer.

In some embodiments, the first sub-layer, the second sub-layer, and the third sub-layer are alternately stacked.

In some embodiments, the material of the first sub-layer comprises at least one element of germanium, Ge, antimony, Sb, silicon, Si;

the material of the second sub-layer comprises at least one element of selenium Se, arsenic As and tellurium Te.

The embodiment of the application provides a phase change memory and a preparation method thereof, wherein the method comprises the following steps: forming a gating layer and a phase change storage layer connected with the gating layer in series; the gating layer comprises a first sublayer and a second sublayer; wherein the elements of the first sub-layer are selected from at least one gating layer element in a first element set, and the elements of the second sub-layer are selected from at least one gating layer element in a second element set; the mobility of each gating layer element in the first type element set is smaller than that of each gating layer element in the second type element set. In the preparation method of the phase change memory provided by the embodiment of the application, the gating layer comprising the first sublayer and the second sublayer is formed, so that the mobility of each element in the first sublayer is smaller than that of each element in the second sublayer, and by utilizing the interface effect between the first sublayer and the second sublayer, the partial phase splitting and even crystallization caused by material diffusion are relieved, so that the high-temperature stability of the gating layer is improved, the high-temperature stability of the phase change memory is improved, the phase change memory has better cycle durability, and the reliability of the phase change memory is further improved.

Drawings

Fig. 1 is a schematic structural diagram of a phase change memory according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart illustrating a method for manufacturing a phase change memory according to an embodiment of the present disclosure;

fig. 3 is a schematic cross-sectional structure diagram of a phase change memory according to an embodiment of the present disclosure;

FIG. 4 is a schematic cross-sectional view of another phase change memory according to an embodiment of the present disclosure;

FIG. 5 is a schematic cross-sectional view illustrating another phase change memory according to an embodiment of the present disclosure;

FIG. 6 is a schematic cross-sectional view of a gate layer including a third sub-layer according to an embodiment of the present disclosure;

fig. 7 is a schematic cross-sectional structure diagram of a gate layer including a fourth sublayer provided in an embodiment of the present application;

the figure includes: 10. a gating layer; 11. a first sublayer; 12. a second sublayer; 13. a third sublayer; 14. a fourth sublayer; 20. a phase change memory layer; 31. a first electrode layer; 32. a second electrode layer; 33. a third electrode layer; 41a, a first conductive line; 41b, a second first conductive line; 42a, a first second conductive line; 42b, a second electrically conductive line; 51. a first phase change memory cell; 52. a second phase change memory cell.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the embodiments of the present application and the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.

Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a phase change memory according to an embodiment of the present disclosure. As shown in fig. 1, the phase change memory sequentially includes, from top to bottom: a first conductive line 41a, a first phase change memory array, a first second conductive line 42a, a second conductive line 42b, a second phase change memory array, and a second first conductive line 41 b. The first phase change memory array includes a plurality of first phase change memory cells 51 arranged in parallel, and the second phase change memory array includes a plurality of second phase change memory cells 52 arranged in parallel. To illustrate the structure of the phase change memory cells in the phase change memory more clearly, fig. 1 shows only one first phase change memory cell and one second phase change memory cell.

In some embodiments, the first second conductive line 42a and the second conductive line 42b may also be merged into the same second conductive line in the phase change memory. In other words, one second conductive line may be formed through one second conductive line forming process.

Note that the first plane in which the first conductive line is provided and the second plane in which the second conductive line is provided are parallel to each other. The phase change memory cell is located between the first plane and the second plane, and the phase change memory cell is perpendicular to both the first conductive line and the second conductive line.

Here, the first conductive line may be a bit line corresponding to a first phase change memory array, and the second first conductive line may be a bit line corresponding to a second phase change memory array; the first second conductive line may be a word line of the first phase change memory array, and the second conductive line may be a word line of the second phase change memory array.

Here, the material of the first and second conductive lines may include a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped polysilicon, or any combination thereof. The first conductive line and the second conductive line may have the same conductive material or may have different conductive materials.

Still referring to fig. 1, the structures of the first phase change memory cell 51 and the second phase change memory cell 52 may be the same. Taking the structure of the first phase change memory cell as an example for illustration, the first phase change memory cell 51 sequentially includes from top to bottom: a third electrode layer 33, a phase change memory layer 20, a second electrode layer 32, a gate layer 10, and a first electrode layer 31.

Still referring to fig. 1, the first electrode layer 31 is located between the gate layer 10 and the first second conductive line 42a, and the gate layer 10 is located between the first electrode layer 31 and the second electrode layer 32. It should be noted that the first electrode layer 31, the second electrode layer 32, and the third electrode layer 33 are electrode layers in a phase change memory cell, and the electrode layers may be made of the same or different materials, and different reference numerals are only used to distinguish the difference in the positions of the electrode layers, and are not used to describe a specific order or sequence.

Here, the material of the first electrode layer, the second electrode layer, and the third electrode layer may include amorphous carbon, for example, α -phase carbon. Here, the electrode layer may be used to conduct an electrical signal.

Here, the gate layer is a core component of the phase change memory, and an Ovonic Threshold Switching (OTS) based on an amorphous chalcogenide material may be used as the gate layer of the phase change memory. When an electric signal is applied, the gating layer is changed from a high-resistance state to a low-resistance state, and the bidirectional threshold switch is in an opening state; when the electric signal is removed, the gating layer is changed from a low-resistance state to a high-resistance state, and the bidirectional threshold switch is in a closed state at the moment.

In a phase change memory, a gating layer based on an amorphous chalcogenide material is often formed as an ovonic threshold switch by a one-time growth method, and such an ovonic threshold switch has many advantages, for example, the gating layer of a chalcogenide system can be well compatible with a phase change memory layer of a chalcogenide system; the chalcogenide compound has advantages in switching speed compared with other systems due to the fast low-resistance state-high-resistance state conversion capability of the chalcogenide compound; the gating layer process for preparing the chalcogenide system is simpler and is compatible with the back-end process of the phase change memory.

However, after a certain number of switching cycles, the gate layer formed by the one-time growth method is affected by joule heat generated during the read/write operation, and the material of the gate layer may undergo local phase splitting or even crystallization, which degrades the switching characteristics of the ovonic threshold switch, and further affects the reliability of the phase change memory or even causes failure of the phase change memory.

In view of this, the present disclosure provides a phase change memory and a method for manufacturing the same. In the preparation method of the phase change memory provided by the embodiment of the application, the gating layer comprising the first sublayer and the second sublayer is formed, so that the mobility of each element in the first sublayer is smaller than that of each element in the second sublayer, and by utilizing the interface effect between the first sublayer and the second sublayer, the partial phase splitting and even crystallization caused by material diffusion are relieved, so that the high-temperature stability of the gating layer is improved, the high-temperature stability of the phase change memory is improved, the phase change memory has better cycle durability, and the reliability of the phase change memory is further improved.

Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a method for manufacturing a phase change memory according to an embodiment of the present disclosure. As shown in fig. 2, an embodiment of the present application provides a method for manufacturing a phase change memory, where the method includes:

step S100, forming a gating layer and a phase change storage layer connected with the gating layer in series; the gating layer comprises a first sublayer and a second sublayer; wherein the elements of the first sub-layer are selected from at least one gating layer element in a first element set, and the elements of the second sub-layer are selected from at least one gating layer element in a second element set; the mobility of each gating layer element in the first type element set is smaller than that of each gating layer element in the second type element set.

Referring to fig. 3, fig. 3 is a schematic cross-sectional structure diagram of a phase change memory according to an embodiment of the present disclosure. As shown in fig. 3, a gate layer 10 and a phase change memory layer 20 connected in series with the gate layer 10 are formed; wherein, the gate layer 10 includes a first sublayer 11 and a second sublayer 12; wherein, the elements of the first sub-layer 11 are selected from at least one gating layer element in the first element group, and the elements of the second sub-layer 12 are selected from at least one gating layer element in the second element group; the mobility of each gating layer element in the first type element set is smaller than that of each gating layer element in the second type element set.

Here, mobility refers to an electrical mobility, and a difference in mobility of materials means that an atomic mobility or a diffusion rate of a material is different when an electrical signal is applied. Generally, the greater the electronegativity of the element, the greater the mobility. By utilizing the interface effect between the sublayers with different mobilities, the local phase splitting and even crystallization caused by diffusion of the gating layer material can be relieved, so that the gating layer can still keep stable after a certain number of switching cycles, the phase change memory has better cycle durability, and the reliability of the phase change memory is further improved.

Here, the gating layer elements may be divided into a first type element set and a second type element set according to mobility of the elements, wherein mobility of each gating layer element in the first type element set is smaller than mobility of each gating layer element in the second type element set. Further, at least one gating layer element in the first element set is arbitrarily selected to form a first sub-layer, and at least one gating layer element in the second element set is arbitrarily selected to form a second sub-layer.

Still referring to fig. 3, the mobility of each element in the first sub-layer 11 is smaller than the mobility of each element in the second sub-layer 12, the first sub-layer 11 is in contact with the second electrode layer 32, and the second sub-layer 12 is in contact with the first electrode layer 31. That is, the first sublayer having smaller element mobility of the gate layer is in contact with the second electrode layer, and the second sublayer having larger element mobility of the gate layer is in contact with the first electrode layer. Of course, the first sublayer in the gate layer may also be in contact with the first electrode layer, and the second sublayer in the gate layer may also be in contact with the second electrode layer, that is, the first sublayer with smaller element mobility in the gate layer is in contact with the first electrode layer, and the second sublayer with larger element mobility in the gate layer is in contact with the second electrode layer.

In some embodiments, the thicknesses of the first and second sub-layers may be the same or different.

Here, the thickness of the first sub-layer (or, the second sub-layer) refers to a dimension of the first sub-layer (or, the second sub-layer) in the stacking direction.

In some embodiments, the thickness of the gate layer ranges from 5nm to 100 nm.

In some embodiments, the number of layers of the first sub-layer may be equal to or greater than 1, and the number of layers of the second sub-layer may be equal to or greater than 1. The gate layer shown in fig. 3 only includes one first sublayer and one second sublayer, which does not limit the scope of protection of the present application. The number of layers of the first sub-layer and the second sub-layer is not particularly limited in the embodiments of the present application.

Here, a is used to denote the first sublayer and B is used to denote the second sublayer, and the structural arrangement of the pass layers shown in fig. 3 may be denoted AB. If the gate layer includes a plurality of first sublayers and a plurality of second sublayers, the number of layers of the first sublayers is the same as that of the second sublayers, the first sublayers and the second sublayers are alternately stacked, the material of the plurality of first sublayers is the same, and the material of the plurality of second sublayers is the same, the structural arrangement of the gate layer may be represented as ABAB … … AB, the gate layer includes a plurality of repeating units, and the structural arrangement of each repeating unit may be represented as AB.

In some embodiments, the number of layers of the first sublayer and the second sublayer may be the same or different. As an example, the gate layer includes three first sublayers and two second sublayers.

In some embodiments, the gating layer includes at least two first sublayers and at least two second sublayers, and the material of each first sublayer may be the same or different and the material of each second sublayer may be the same or different. For example, the gate layer includes three first sublayers and two second sublayers, wherein the materials of the three first sublayers may be the same, and the materials of the two second sublayers may be the same; alternatively, the materials of the three first sublayers may be different and the materials of the two second sublayers may be different.

In some embodiments, the first sub-layer may be disposed adjacent to the first sub-layer and/or the second sub-layer. For example, the first sub-layer is disposed adjacent to the second sub-layer, and the second sub-layer is also disposed adjacent to the first sub-layer, i.e., the first sub-layer and the second sub-layer are alternately stacked. For another example, one first sub-layer may be disposed adjacent to another first sub-layer, and the mobility of elements forming the two first sub-layers may be the same, but the materials forming the two first sub-layers may be different.

In the embodiment of the present application, the number of layers of the first sub-layer is greater than that of the second sub-layer; the second sub-layer is located between two adjacent first sub-layers.

Referring to fig. 4, fig. 4 is a schematic cross-sectional structure diagram of another phase change memory according to an embodiment of the disclosure. As shown in fig. 4, the gate layer 10 includes two first sublayers 11 and one second sublayer 12, and the second sublayer 12 is located between two adjacent first sublayers 11; the phase change memory further comprises a first electrode layer 31 and a second electrode layer 32 which are respectively arranged at two opposite sides of the gate layer 10, wherein the second electrode layer 32 is positioned between the gate layer 10 and the phase change memory layer 20; wherein the first electrode layer 31 and the second electrode layer 32 are both arranged adjacent to the first sub-layer 11.

Here, the gate layer 10 shown in fig. 4 includes two first sublayers 11 and one second sublayer 12, and the second sublayer 12 is located between two adjacent first sublayers 11.

It should be noted that, the gate layer is driven to generate a phase change by applying a voltage, and a process of mutual transition between a high resistance state and a low resistance state is generated, so as to control the on and off of the ovonic threshold switch. However, during the on and off cycles of the ovonic threshold switch, the constituent material of the pass layer may diffuse into the first and second electrode layers.

The elements of the first sub-layer are selected from at least one gating layer element in the first element group, the elements of the second sub-layer are selected from at least one gating layer element in the second element group, and the mobility of each gating layer element in the first element group is smaller than that of each gating layer element in the second element group; the second sublayer with the larger element mobility of the gating layer is arranged between the first sublayers with the smaller element mobility of the two adjacent gating layers, namely the second sublayer with the larger element mobility of the gating layer is positioned in the middle, the first sublayer with the smaller element mobility of the gating layer is positioned on the outer side, and the first sublayer with the smaller element mobility of the gating layer is in contact with the first electrode layer and the second electrode layer.

In an embodiment of the present application, the first sub-layers and the second sub-layers are alternately stacked.

Here, the mobility of each element in the first sublayer is smaller than that of each element in the second sublayer, and the first sublayers and the second sublayers are alternately stacked. Therefore, the gating layer comprises the interfaces of the first sub-layer and the second sub-layer with different element mobility of the gating layer, and partial phase splitting and even crystallization caused by outward diffusion of elements of the gating layer with higher mobility can be effectively relieved, so that the high-temperature stability of the gating layer is improved.

Referring to fig. 5, fig. 5 is a schematic cross-sectional structure diagram of another phase change memory provided in an embodiment of the present application, and for convenience of explaining a structure of a gate layer, a phase change memory layer and a third electrode layer are omitted in fig. 5. As shown in fig. 5, the gate layer 10 includes a plurality of first sub-layers 11 and a plurality of second sub-layers 12 alternately stacked; wherein the first electrode layer 31 and the second electrode layer 32 are both arranged adjacent to the first sublayer 11.

In the preferred embodiment of the present application, the mobility of each element in the first sub-layer 11 is smaller than that of each element in the second sub-layer 12; the first sub-layers 11 and the second sub-layers 12 are alternately stacked.

Here, first sublayers having smaller element mobility of the gate layer and second sublayers having higher element mobility of the gate layer are alternately stacked to form a gate layer of a multilayer stack. The gate layer is formed in a multi-layer stacking mode, and the interface effect introduced between the first sub-layers and the second sub-layers can effectively relieve local phase splitting and even crystallization caused by material diffusion, so that the high-temperature stability of the gate layer is improved, the gate layer has better cycle durability, and the reliability of the phase change memory is improved.

In the embodiment of the application, the gating layer elements comprise germanium Ge, antimony Sb, silicon Si, selenium Se, arsenic As and tellurium Te.

In the embodiment of the application, the material of the first sub-layer comprises at least one element of germanium Ge, antimony Sb and silicon Si; the material of the second sub-layer comprises at least one element of selenium Se, arsenic As and tellurium Te.

Dividing according to the size of the element migration rate, and dividing the gating layer elements into a first element set and a second element set; the first element set comprises germanium Ge, antimony Sb and silicon Si, the second element set comprises selenium Se, arsenic As and tellurium Te, and the mobility of each gating layer element in the first element set is smaller than that of each element in the second element set. Of course, the materials of the first sub-layer and the second sub-layer include elements not limited to the above listed elements, and the materials of the first sub-layer and the second sub-layer may include any other elements having phase change characteristics in the periodic table.

In a specific example of the present application, taking the material of the gate layer As Ge-Se-Te-As-Si system As an example for illustration, the gate layer may be divided into a first sub-layer including Ge and Si elements and a second sub-layer including Se, Te and As elements, and the first sub-layer and the second sub-layer are alternately stacked, so that the Se, Te and As elements with higher electromigration rate may be limited between the two first sub-layers of Ge and Si elements with lower electromigration rate As the second sub-layer, and local phase separation caused by diffusion of the Se, Te or As elements in the gate layer may be delayed, and even crystallization may be performed, thereby improving amorphous integrity of the gate layer after multiple switching cycles. For example, the gate layers of the multi-layer stacked arrangement are annealed at 400 ℃ for 30 minutes, and the integrity of the amorphous structure can still be maintained, so that the high-temperature stability of the gate layers is ensured, the gate layers have better cycle durability, and finally better phase change memory performance is obtained.

In addition, the phase change memory provided by the embodiment of the application comprises the gating layer formed by the multi-layer stack, the gating layer formed by the multi-layer stack has lower sensitivity to size reduction, and electrical performance parameter variability (electrical parameters variability) between devices with different sizes is smaller. In other words, even if the size of the phase change memory is reduced, the electrical properties of the phase change memory using such a gate layer can be maintained stably.

In an embodiment of the present application, the gate layer further includes a third sublayer; wherein the elements of the third sublayer are selected from at least one gating layer element in a third class of element set; the mobility of each gating layer element in the first type element set and the mobility of each gating layer element in the third type element set are both smaller than the mobility of each gating layer element in the second type element set.

Referring to fig. 6, fig. 6 is a schematic cross-sectional structure diagram of a pass layer including a third sub-layer according to an embodiment of the present application. As shown in fig. 6, the gating layer 10 includes a first sublayer 11, a second sublayer 12 and a third sublayer 13, wherein elements of the first sublayer are selected from at least one gating layer element in a first element set, elements of the second sublayer are selected from at least one gating layer element in a second element set, and elements of the third sublayer are selected from at least one gating layer element in a third element set; and the mobility of each gating layer element in the first element set and the mobility of each gating layer element in the third element set are both smaller than the mobility of each gating layer element in the second element set.

Here, two cases are included in which the mobility of each gating layer element in the first type element set and the mobility of each gating layer element in the third type element set are both smaller than the mobility of each gating layer element in the second type element set. In the first case, the mobility of each gating layer element in the third type element set is smaller than the mobility of each gating layer element in the first type element set, and the mobility of each gating layer element in the first type element set is smaller than the mobility of each gating layer element in the second type element set. In a second case, the mobility of each gating layer element in the first set of elements is less than the mobility of each gating layer element in the third set of elements, and the mobility of each gating layer element in the third set of elements is less than the mobility of each gating layer element in the second set of elements. In other words, the mobility of each element in the third sublayer is less than the mobility of each element in the first sublayer, which is less than the mobility of each element in the second sublayer; or the mobility of each element in the first sublayer is smaller than that of each element in the third sublayer, and the mobility of each element in the third sublayer is smaller than that of each element in the second sublayer.

In an embodiment of the application, the second sublayer is located between the first sublayer and the third sublayer.

Here, a is used to denote the first sub-layer, B is used to denote the second sub-layer, and C is used to denote the third sub-layer, so the structural arrangement of the gated layers shown in fig. 6 can be denoted abcabcabc … … ABC. If the gating layer comprises a plurality of first sublayers, a plurality of second sublayers and a plurality of third sublayers, the number of layers of the first sublayers, the number of layers of the second sublayers and the number of layers of the third sublayers are the same, and the first sublayers, the second sublayers and the third sublayers are alternately stacked. If the materials of the first sub-layers are the same, the materials of the second sub-layers are the same, and the materials of the third sub-layers are the same, then the gate layer shown in fig. 6 includes a plurality of repeating units, and the structural arrangement of each repeating unit may be denoted as ABC.

The mobility of each gating layer element in the first element set and the mobility of each gating layer element in the third element set are both smaller than the mobility of each gating layer element in the second element set; the second sublayer with higher element mobility of the gating layer is arranged between the first sublayer and the third sublayer with lower element mobility of the gating layer, namely the second sublayer with higher element mobility of the gating layer is arranged in the middle, the first sublayer and the third sublayer with lower element mobility of the gating layer are arranged on the outer sides, and the first sublayer and the third sublayer with lower element mobility of the gating layer are respectively contacted with the first electrode layer and the second electrode layer, so that elements of the gating layer with higher element mobility can be limited in the middle layer of the gating layer, diffusion of the composition materials of the gating layer into the first electrode layer and the second electrode layer is effectively reduced, interface effects introduced among the first sublayer, the second sublayer and the third sublayer can effectively relieve local phase splitting and even crystallization caused by material diffusion, the high-temperature stability of the gating layer is improved, and the gating layer has better cycle durability, thereby improving the reliability of the phase change memory.

In an embodiment of the present application, the first sub-layer, the second sub-layer, and the third sub-layer are alternately stacked.

Here, the mobility of each element in the first sublayer and the mobility of each element in the third sublayer are both smaller than the mobility of each element in the second sublayer, and the first sublayer, the second sublayer and the third sublayer, which have different element mobilities of the gate layer, are alternately stacked to form a gate layer of a multilayer stack. The gate layer is formed in a multi-layer stacking mode, and the interface effect introduced among the first sub-layers, the second sub-layers and the third sub-layers can effectively relieve local phase splitting and even crystallization caused by material diffusion, so that the high-temperature stability of the gate layer is improved, the gate layer has better cycle durability, and the reliability of the phase change memory is improved.

As previously described, the gate layer shown in fig. 6 includes a plurality of repeating units, and the structural arrangement of each repeating unit may be denoted as ABC. Of course, the arrangement of the first sublayer, the second sublayer and the third sublayer in the gate layer is not limited thereto.

Here, the first sublayer is also denoted by a, the second sublayer is denoted by B, and the third sublayer is denoted by C. If the mobility of each element in the third sublayer is smaller than that of each element in the first sublayer, the mobility of each element in the first sublayer is smaller than that of each element in the second sublayer.

In some embodiments, the number of layers of the first, second, and third sub-layers in the gating layer is the same, and the structural arrangement of the gating layer may be denoted as CAB … … CAB. Thus, the gating layer includes a plurality of repeating units, each of which may be represented by a structural arrangement CAB whose gating layer element mobility exhibits an increasing regularity. In this way, the third sublayer and the second sublayer in the gate layer are in contact with the first electrode layer and the second electrode layer, respectively. In the embodiment of the present application, the number of layers of the first sublayer, the second sublayer and the third sublayer may also be different.

In other embodiments, the number of layers in the gate layer for the first sublayer, the second sublayer, and the third sublayer are all the same, and the structural arrangement of the gate layer may be represented as BACBAC … … BAC. Thus, the gate layer comprises a plurality of repeating units, the structural arrangement of each repeating unit can be represented as BAC, and the gate layer element mobility of the repeating unit BAC is in a decreasing rule. In this way, the second sublayer and the third sublayer in the gate layer are in contact with the first electrode layer and the second electrode layer, respectively. In the embodiment of the present application, the number of layers of the first sublayer, the second sublayer and the third sublayer may also be different.

Here, the first sublayer is also denoted by a, the second sublayer is denoted by B, and the third sublayer is denoted by C. If the mobility of each element in the first sublayer is smaller than that of each element in the third sublayer, the mobility of each element in the third sublayer is smaller than that of each element in the second sublayer.

In some embodiments, the number of layers in the gate layer is the same for the first sublayer, the second sublayer, and the third sublayer, and the structural arrangement of the gate layer may be represented as ACBACB … … ACB. Thus, the gating layer comprises a plurality of repeating units, the structural arrangement of each repeating unit can be represented as ACB, and the gating layer element mobility of the repeating unit ACB presents an increasing law. In this way, the first sublayer and the second sublayer in the gate layer are in contact with the first electrode layer and the second electrode layer, respectively.

In other embodiments, the number of layers in the gating layer, which is the same for the first sublayer, the second sublayer, and the third sublayer, may be represented by the structural arrangement of the gating layer as bcabcaca … … BCA. Thus, the gating layer comprises a plurality of repeating units, the structural arrangement of each repeating unit can be represented as BCA, and the mobility of the gating layer element of the BCA of the repeating units is in a decreasing rule. In this way, the first sublayer and the second sublayer in the gate layer are in contact with the first electrode layer and the second electrode layer, respectively. In the embodiment of the present application, the number of layers of the first sub-layer, the second sub-layer and the third sub-layer may also be different

In an embodiment of the present application, the gate layer further includes a fourth sublayer; wherein the elements of the fourth sublayer are selected from at least one gating layer element in a fourth class of element set; the mobility of each gating layer element in the first type element set, the mobility of each gating layer element in the third type element set, and the mobility of each gating layer element in the fourth type element set are all smaller than the mobility of each gating layer element in the second type element set.

Referring to fig. 7, fig. 7 is a schematic cross-sectional structure diagram of a gate layer including a fourth sub-layer according to an embodiment of the present application. As shown in fig. 7, the gating layer 10 includes a first sublayer 11, a second sublayer 12, a third sublayer 13, and a fourth sublayer 14, where elements of the first sublayer are selected from at least one gating layer element in the first kind of element set, elements of the second sublayer are selected from at least one gating layer element in the second kind of element set, elements of the third sublayer are selected from at least one gating layer element in the third kind of element set, and elements of the fourth sublayer are selected from at least one gating layer element in the fourth kind of element set; the mobility of each gating layer element in the first element set, the mobility of each gating layer element in the third element set and the mobility of each gating layer element in the fourth element set are all smaller than the mobility of each gating layer element in the second element set.

Here, the mobility of each gating layer element in the first type element set, the mobility of each gating layer element in the third type element set, and the mobility of each gating layer element in the fourth type element set are all smaller than the mobility of each gating layer element in the second type element set. Using V _A The mobility of each element in the first sublayer is represented separately, using V _B The mobility of each element in the second sublayer is expressed using V _C Indicating the mobility of the respective elements in the third sublayer, using V _D Indicating the mobility of each element in the fourth sublayer. Then, V in the first case can be cited _D <V _C <V _A <V _B (ii) a Second oneIn this case, V _C <V _D <V _A <V _B (ii) a In the third case, V _C <V _A <V _D <V _B (ii) a In the fourth case, V _D <V _A <V _C <V _B (ii) a In the fifth case, V _A <V _D <V _C <V _B (ii) a In the sixth case, V _A <V _C <V _D <V _B 。

In an embodiment of the present application, the second sublayer is located between the first sublayer and the third sublayer; and/or the second sublayer is located between the first sublayer and the fourth sublayer; alternatively, the second sublayer is located between the third sublayer and the fourth sublayer.

Here, a denotes the first sublayer, B denotes the second sublayer, C denotes the third sublayer, and D denotes the fourth sublayer, so that the structural arrangement of the gate layer shown in fig. 7 may be denoted as ABCDABCD … … ABCD. If the gating layer comprises a plurality of first sublayers, a plurality of second sublayers, a plurality of third sublayers and a plurality of fourth sublayers, the number of layers of the first sublayers, the number of layers of the second sublayers, the number of layers of the third sublayers and the number of layers of the fourth sublayers are the same. If the materials of the first sub-layers are the same, the materials of the second sub-layers are the same, the materials of the third sub-layers are the same, and the materials of the fourth sub-layers are the same, the gate layer shown in fig. 7 includes a plurality of repeating units, and the structural arrangement of each repeating unit may be represented as ABCD.

Here, the mobility of each gating layer element in the first type element set, the mobility of each gating layer element in the third type element set, and the mobility of each gating layer element in the fourth type element set are all less than the mobility of each gating layer element in the second type element set. The second sublayer with higher element mobility of the gating layer is arranged between the first sublayer and the third sublayer with lower element mobility of the gating layer, namely the second sublayer with higher element mobility of the gating layer is positioned in the middle, the first sublayer, the third sublayer and the fourth sublayer with lower element mobility of the gating layer are positioned on the outer sides, and the first sublayer and the fourth sublayer with lower element mobility of the gating layer are respectively contacted with the first electrode layer and the second electrode layer, so that elements of the gating layer with higher element mobility can be limited in the middle layer of the gating layer, diffusion of constituent materials of the gating layer into the first electrode layer and the second electrode layer is effectively reduced, interface effects introduced among the first sublayer, the second sublayer, the third sublayer and the fourth sublayer can effectively relieve local phase splitting and even crystallization caused by material diffusion, and the high-temperature stability of the gating layer is improved, therefore, the gating layer has better cycle durability, and the reliability of the phase change memory is improved.

In an embodiment of the present application, the first sub-layer, the second sub-layer, the third sub-layer, and the fourth sub-layer are alternately stacked.

Here, the first sub-layer, the second sub-layer, the third sub-layer, and the fourth sub-layer, which have different element mobilities of the gate layer, are alternately stacked to form a multi-layered stacked gate layer. The gate layer is formed in a multi-layer stacking mode, and interface effects introduced among the first sub-layers, the second sub-layers, the third sub-layers and the fourth sub-layers can effectively relieve local phase splitting and even crystallization caused by material diffusion, so that the high-temperature stability of the gate layer is improved, the gate layer has better cyclic durability, and the reliability of the phase change memory is improved.

As previously described, the gate layer shown in fig. 7 includes a plurality of repeating units, and the structural arrangement of each repeating unit may be denoted as ABCD. Of course, the arrangement of the first sublayer, the second sublayer, the third sublayer and the fourth sublayer in the gate layer is not limited thereto.

Here, a is used to denote the first sublayer, B is used to denote the second sublayer, C is used to denote the third sublayer, and D is used to denote the fourth sublayer. If the mobility of each element in the fourth sublayer is smaller than that of each element in the third sublayer, the mobility of each element in the third sublayer is smaller than that of each element in the first sublayer, and the mobility of each element in the first sublayer is smaller than that of each element in the second sublayer, that is, V _D <V _C <V _A <V _B 。

In some embodiments, the number of layers in the gate layer is the same for the first, second, third, and fourth sub-layers, and the structural arrangement of the gate layer may be denoted as dcabdcabab … … DCAB. Thus, the gating layer includes a plurality of repeating units, each of which may be represented by a structural arrangement DCAB whose gating layer element mobility exhibits an increasing regularity. In this way, the fourth sublayer and the second sublayer in the gate layer are in contact with the first electrode layer and the second electrode layer, respectively. In the embodiment of the present application, the number of the first sub-layer, the second sub-layer, the third sub-layer, and the fourth sub-layer may also be different.

In other embodiments, the number of layers of the first sublayer, the second sublayer, the third sublayer and the fourth sublayer in the gating layer is the same, and the structural arrangement of the gating layer may be represented as BACDBACD … … BACD. Thus, the gating layer comprises a plurality of repeating units, the structural arrangement of each repeating unit can be represented as a BACD, and the gating layer element mobility of the repeating units BACD is in a decreasing rule. In this way, the second sublayer and the fourth sublayer in the gate layer are in contact with the first electrode layer and the second electrode layer, respectively. In the embodiment of the present application, the number of layers of the first sublayer, the second sublayer, the third sublayer and the fourth sublayer may also be different.

In the embodiment of the present application, any one of a physical vapor deposition method, a chemical vapor deposition method, and an atomic layer deposition method may be used to form the gate layer and the phase change memory layer. As an example, magnetron sputtering in physical vapor deposition can be used for the formation of the gate layer.

In a specific embodiment of the present application, the gate layer can be prepared using a magnetron sputtering method. The sputtering system includes a chamber holding a sputtering target and a substrate. The sputtering target and substrate are coupled to a power supply and controller for biasing the device during the sputtering process. The applied bias voltage can be direct current, pulsed direct current, radio frequency, and combinations thereof, and the sputtering process is turned on, off, and regulated by a controller. The sputtering chamber is provided with a vacuum pump for vacuumizing the chamber; the chamber is also provided with a gas inlet for an inert gas (e.g. nitrogen or argon) or a reactive gas (e.g. oxygen).

In a specific example of the present application, taking the example that the material of the gate layer is Ge-Se-As-Si system As an example, the gate layer may be divided into a first sublayer including Ge and Si elements and a second sublayer including Se and As elements, and the first sublayer and the second sublayer may be alternately stacked. Specifically, a Ge target, a Si target, a Se target and an As target can be selected and fixed on the sputtering target in the sputtering chamber; vacuumizing the sputtering cavity, and introducing argon to adjust the pressure in the sputtering cavity; adjusting power knobs of the Ge target and the Si target to carry out co-sputtering, and forming a Ge-Si layer, namely a first sublayer, on the substrate; and adjusting power knobs of the Se target and the As target to carry out co-sputtering, and forming a Se-As layer, namely a second sublayer, on the first sublayer. And repeating the steps to obtain the first sub-layer and the second sub-layer which are alternately stacked.

According to the preparation method of the phase change memory, the gating layer is formed in a multi-layer stacking mode, and the components and the thicknesses of different sub-layers are convenient to control.

In an embodiment of the present application, before forming the gate layer, the method further includes: a first electrode layer is formed.

In an embodiment of the present application, after forming the gate layer and before forming the phase change memory layer in series with the gate layer, the method further includes: and forming a second electrode layer.

In an embodiment of the present application, after forming the phase change memory layer in series with the pass layer, the method further includes: and forming a third electrode layer.

The embodiment of the present application further provides a phase change memory, still referring to fig. 3, the phase change memory includes: a gate 10 and a phase change memory layer 20 connected in series with the gate layer 10;

the gate layer 10 includes a first sublayer 11 and a second sublayer 12; the mobility of each element in the first sub-layer 11 is smaller than the mobility of each element in the second sub-layer 12.

In an embodiment of the present application, the first sub-layers and the second sub-layers are alternately stacked.

In an embodiment of the present application, the gate layer further includes a third sublayer; the mobility of each element in the third sublayer is less than the mobility of each element in the second sublayer; the second sublayer is located between the first sublayer and the third sublayer.

In an embodiment of the present application, the first sub-layer, the second sub-layer, and the third sub-layer are alternately stacked.

In the embodiment of the application, the material of the first sub-layer comprises at least one element of germanium Ge, antimony Sb and silicon Si;

the material of the second sub-layer comprises at least one element of selenium Se, arsenic As and tellurium Te.

The embodiment of the application provides a phase change memory and a preparation method thereof, wherein the method comprises the following steps: forming a gating layer and a phase change storage layer connected with the gating layer in series; the gating layer comprises a first sublayer and a second sublayer; wherein the elements of the first sub-layer are selected from at least one gating layer element in a first element set, and the elements of the second sub-layer are selected from at least one gating layer element in a second element set; the mobility of each gating layer element in the first type element set is smaller than that of each gating layer element in the second type element set. In the preparation method of the phase change memory provided by the embodiment of the application, the gating layer comprising the first sublayer and the second sublayer is formed, so that the mobility of each element in the first sublayer is smaller than that of each element in the second sublayer, and by utilizing the interface effect between the first sublayer and the second sublayer, the local phase splitting and even crystallization caused by material diffusion are relieved, and the high-temperature stability of the gating layer is improved, so that the high-temperature stability of the phase change memory is improved, the phase change memory has better cycle durability, and the reliability of the phase change memory is further improved.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications and equivalents of the technical solutions that are included in the present application, which are made by the present specification and the accompanying drawings, or are directly/indirectly applied to other related technical fields, are included in the scope of the present application.

Claims (10)

1. A method for manufacturing a phase change memory, the method comprising:

forming a gating layer and a phase change storage layer connected with the gating layer in series;

the gating layer comprises a first sublayer and a second sublayer; wherein the elements of the first sub-layer are selected from at least one gating layer element in a first element set, and the elements of the second sub-layer are selected from at least one gating layer element in a second element set; the mobility of each gating layer element in the first type element set is smaller than that of each gating layer element in the second type element set.

2. The method of manufacturing a phase change memory according to claim 1,

the number of layers of the first sub-layer is greater than that of the second sub-layer; the second sub-layer is located between two adjacent first sub-layers.

3. The method of manufacturing a phase change memory according to claim 1,

the gate layer further comprises a third sublayer; wherein the elements of the third sublayer are selected from at least one gating layer element in a third class of element set; the mobility of each gating layer element in the first type element set and the mobility of each gating layer element in the third type element set are both smaller than the mobility of each gating layer element in the second type element set.

4. The method of manufacturing a phase change memory according to claim 3,

the second sublayer is located between the first sublayer and the third sublayer.

5. The method of manufacturing a phase change memory according to claim 1,

the gating layer elements comprise Ge, Sb, Si, Se, As and Te.

6. A phase change memory, comprising: the phase change memory device comprises a gating layer and a phase change memory layer connected with the gating layer in series;

the gating layer comprises a first sublayer and a second sublayer; the mobility of each element in the first sublayer is less than the mobility of each element in the second sublayer.

7. The phase change memory according to claim 6,

the first sub-layers and the second sub-layers are alternately stacked.

8. The phase change memory according to claim 6,

the gate layer further comprises a third sublayer; the mobility of each element in the third sublayer is less than the mobility of each element in the second sublayer; the second sublayer is located between the first sublayer and the third sublayer.

9. The phase change memory according to claim 8,

the first sub-layer, the second sub-layer and the third sub-layer are alternately stacked.

10. The phase change memory according to claim 6,

the material of the first sub-layer comprises at least one element of Ge, Sb and Si;

the material of the second sub-layer comprises at least one element of selenium Se, arsenic As and tellurium Te.

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