CN114999558B - Method and system for testing memory chip - Google Patents
Method and system for testing memory chip Download PDFInfo
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- CN114999558B CN114999558B CN202210924300.3A CN202210924300A CN114999558B CN 114999558 B CN114999558 B CN 114999558B CN 202210924300 A CN202210924300 A CN 202210924300A CN 114999558 B CN114999558 B CN 114999558B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Abstract
The invention discloses a method and a system for testing a memory chip, wherein the method at least comprises the following steps: providing a chip to be tested, and configuring a test unit in the chip to be tested; performing read-write pretest on the chip to be tested through the test unit to obtain storage information of the chip to be tested after various data are written in, and taking the storage information of the chip to be tested after various data are written in as comparison table information; testing parity check information of the chip to be tested when information is not written and preset information is written; and comparing the parity check information with the comparison table information, and treating the chip to be tested as a waste chip when the parity check information does not conform to the comparison table information. The invention provides a method and a system for testing a memory chip, which can quickly detect a defective chip with low consumption.
Description
Technical Field
The invention belongs to the technical field of storage, and particularly relates to a method and a system for testing a storage chip.
Background
In the manufacturing process of memory chips, defective products may occur due to process limitations. In order to ensure that errors of the chip are within a controllable range during use, the chip needs to be packaged and tested after the chip is packaged, and the manufactured semiconductor element is confirmed for structure and electrical functions so as to ensure that the semiconductor element meets the requirements of customers.
Under the condition of high chip yield requirement, if the quality of a register and a Random Access Memory (RAM) does not meet the standard, random and uncontrollable influence is brought to the device. While package testing for registers and random access memory is cumbersome and resource consuming.
Disclosure of Invention
The invention aims to provide a method and a system for testing a memory chip, which can detect a defective chip quickly and with low consumption.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a method for testing a memory chip, which at least comprises the following steps:
providing a chip to be tested, and configuring a test unit in the chip to be tested;
performing read-write pretest on the chip to be tested through the test unit to obtain storage information of the chip to be tested after various data are written in, and taking the storage information of the chip to be tested after various data are written in as comparison table information;
testing the parity check information of the chip to be tested when information is not written and preset information is written; and
and comparing the parity check information with the comparison table information, and treating the chip to be detected as a waste chip when the parity check information does not accord with the comparison table information.
In an embodiment of the present invention, the step of performing the read-write pretest on the chip to be tested through the test unit includes:
reading the storage information of the chips to be tested when information is not written in and the storage information when the preset information is written in to form pretest data; and
and counting and screening the pretest data to obtain comparison table information.
In an embodiment of the present invention, the step of counting and screening the pretest data includes:
obtaining the number of samples of the chip to be tested for pretesting, and taking half of the number of samples of the chip to be tested as a screening threshold; and
dividing the pretest data into a plurality of comparison information classes according to the content of the pretest data, and acquiring the number of the pretest data of the comparison information classes; and
and when the number of the pretest data exceeds the screening threshold value, recording the comparison information as comparison table information.
In an embodiment of the present invention, the step of testing the parity check information of the chip to be tested when no information is written and when preset information is written includes:
reading default storage information of the chip to be tested, and acquiring odd-even digits of the default storage information;
writing the preset information into the chip to be tested, reading the written storage information of the chip to be tested, and acquiring the parity bit number of the written storage information; and
and recording the parity bit number of the default storage information and the parity bit number of the written storage information as parity check information.
In an embodiment of the present invention, the step of writing the preset information includes:
writing first preset information into the chip to be tested, and acquiring the parity bit number of the first preset information;
and resetting the chip to be tested, writing second preset information into the chip to be tested, and acquiring the odd-even bit number of the second preset information.
In an embodiment of the present invention, the step of writing the first preset information into the chip to be tested includes: and sending a signal for writing the first preset information and a start enabling signal to the chip to be tested.
In an embodiment of the present invention, the step of resetting the chip to be tested includes: and sending a signal for writing the first preset information and a stop enabling signal to the chip to be tested.
In an embodiment of the present invention, the step of configuring the test unit in the chip to be tested includes:
reserving a configuration area on the chip to be tested, and setting a parity check unit and a check register on the configuration area;
electrically connecting the check register to an output end of the parity check unit; and
and establishing a mapping relation between the check register and the chip to be tested.
In an embodiment of the present invention, the step of establishing a mapping relationship between the check register and the chip to be tested includes:
acquiring first physical address information of a register and a memory in the chip to be tested;
acquiring second physical address information of a storage block in the check register; and
and associating the first physical address information and the second physical address information, and forming mapping table information.
The invention provides a test system of a memory chip, which comprises:
the configuration module is used for configuring a test unit in the chip to be tested;
the pretesting module is used for applying the test unit, performing read-write pretest on the chip to be tested, acquiring the storage information of the chip to be tested in various states, and taking the storage information of the chip to be tested in various states as the information of the comparison table;
the read-write testing module is used for testing the parity check information of the chip to be tested in a default state, a state of writing first preset information and a state of writing second preset information; and
and the comparison module is used for comparing the parity check information with the comparison table information and treating the chip to be detected as a waste chip when the parity check information does not accord with the comparison table information.
As described above, the present invention provides a method and a system for testing a memory chip, which can rapidly eliminate unqualified chips caused by physical damage of a register and a memory, thereby improving the yield of the chips. Moreover, according to the test method and the test system provided by the invention, the chips of various types can be tested in the chip sealing test process under the condition of not additionally arranging an external sealing circuit, the consumed circuit resources are less, and the test efficiency is improved. According to the testing method and the testing system provided by the invention, the cost consumption of the chip in the packaging testing stage is reduced, and the testing time can be saved on the premise of ensuring the accuracy. In the process of chip packaging test, the chip can be tested at any time, and the test method has better universality.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a test cell.
FIG. 2 is a flow chart of the testing method of the present invention.
Fig. 3 is a flowchart of step S20.
Fig. 4 is a flowchart of step S24.
Fig. 5 is a flowchart of step S30.
FIG. 6 is a schematic diagram of a test system according to the present invention.
Fig. 7 is a schematic structural diagram of the electronic device according to the present invention.
FIG. 8 is a diagram illustrating a storage structure of computer instructions.
Fig. 9 is a schematic structural diagram of the sealing apparatus.
Description of reference numerals: 1. a chip to be tested; 2. a storage module; 3. a register; 4. a memory; 5. a processor; 6. a memory device; 41. a storage unit; 10. a first test unit; 20. a second test unit; 30. a parity check module; 40. checking a register; 50. a storage block; 100. testing the system; 101. a configuration module; 102. a pre-test module; 103. a read-write test module; 104. a comparison module; 200. sealing and testing equipment; 201. a hardware platform; 2011. a power supply unit; 2012. a communication unit; 2013. a read-write unit; 2014. a control unit; 202. and (3) a software platform.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The memory chip is a specific application of the concept of an embedded system chip in the memory industry. Memory chip products are used in a large number of electronic devices, such as home appliances, mobile phones, smart terminal devices, smart home devices, and various industrial tools. When the chip is applied to the fields of aerospace, vehicle-mounted and military, the requirements for the register and the random access memory are extremely high. In the chip, the registers are small storage areas for storing data, and are used for temporarily storing data participating in operation and operation results. During the operation of the chip, the register directly affects the calling of the function. Random Access Memory (RAM) can directly exchange data with a Central Processing Unit (CPU), and is used to store a large amount of data information. The random access memory affects the accuracy of the chip in storing and exchanging data during operation of the chip. After the chip is packaged, the packaging test method provided by the invention can be used for the functional test of the register and the random access memory in the chip, so that the defective chip is screened out, and the chip can be applied to the fields with high yield requirements such as spaceflight, vehicle-mounted, military and the like.
Referring to fig. 1 and 2, the present invention provides a method for testing a memory chip, where the method for testing a package can test a register and a random access memory in the chip, and includes steps S10 to S50.
S10, providing a chip to be tested, and configuring a test unit in the chip to be tested.
S20, performing read-write pretest on the chip to be tested through the test unit to obtain the storage information of the chip to be tested after various data are written in, and taking the storage information of the chip to be tested after various data are written in as comparison table information.
And S30, testing the parity check information of the chip to be tested when the information is not written and when the preset information is written.
And S40, when the parity check information does not accord with the comparison table information, treating the chip to be detected as a waste chip.
And S50, when the parity check information is consistent with the comparison table information, warehousing and managing the chip to be tested.
Referring to fig. 1 and fig. 2, in an embodiment of the present invention, a chip 1 to be tested includes a memory module 2, and the memory module 2 includes a register 3 and a memory 4. The register 3 may be a basic register or a shift register. The memory 4 is a random access memory. In step S10, a test unit is loaded on the chip 1 to be tested, and the test unit is electrically connected to the memory module 2. The testing units include a plurality of testing units, such as a first testing unit 10 and a second testing unit 20, wherein the first testing unit 10 is electrically connected to the register 3, and the second testing unit 20 is electrically connected to the memory 4. The first test unit 10 and the second test unit 20 have the same structure. The first test unit 10 includes a parity module 30 and a check register 40. The parity module 30 is electrically connected to the register 3, in this embodiment, the parity module 30 is a parity circuit, and the parity module 30 can perform parity check on the read/write result of the register 3. The check register 40 is electrically connected to the parity module 30. Wherein the check register 40 comprises a plurality of memory blocks 50. In the first test unit 10, the number of memory blocks 50 and registers 3 is the same, and the memory blocks 50 and the registers 3 correspond. Specifically, the physical addresses of the register 3 and the memory 4 are taken as first physical address information, the physical address of the memory block 50 is taken as second physical address information, and a mapping table is established between the first physical address information and the second physical address information. Through the mapping table, the parity information obtained by the parity module 30 from the register 3 can be stored in the corresponding storage block 50. The memory 4 includes a plurality of memory cells 41. Similarly, in the second test unit 20, the parity information obtained by the parity module 30 in the storage unit 41 may be stored in the corresponding storage block.
Referring to fig. 1 to 3, in an embodiment of the present invention, the first testing unit 10 performs a pretest on the register 3, and the second testing unit 20 performs a pretest on the memory 4, so as to obtain the storage information of the register 3 and the memory 4 in multiple states, and the storage information obtained by the testing is used as the comparison table information. Wherein the tests of the first test unit 10 and the second test unit 20 can be performed simultaneously. The step S20 specifically includes steps S21 to S24.
S21, reading default storage information of a register and a memory, and obtaining first pretest data.
And S22, writing first preset information into the register and the memory, and obtaining second pretest data.
And S23, writing second preset information into the register and the memory, and obtaining third pretest data.
And S24, formulating first comparison table information, second comparison table information and third comparison table information according to the first pretest data, the second pretest data and the third pretest data.
Referring to fig. 1 to 3, in an embodiment of the invention, in step S21, the default storage information of the register 3 and the memory 4 is read. After the chip 1 to be tested is produced by an upstream manufacturer, the chip 1 to be tested originally stores information which is not written in the testing process, and the stored information is used as default storage information of the chip 1 to be tested. After the configuration of the test units is completed, the chips 1 to be tested in the same batch are subjected to the pretest synchronously. Specifically, in step S21, the enable signal of the parity module 30 is set to 1, the default storage information in the register 3 and the memory 4 is read, and the parity module 30 obtains the parity number during the reading of the default storage information and forms the first pretest data. Therein, the first pretest data is stored in the check register 40, in particular in the memory block 50. The check results of the register 3 and the memory cell 41 are stored in the corresponding memory block 50.
Referring to fig. 1 to 3, in an embodiment of the invention, in step S22, first predetermined information is written into the register 3 and the memory 4, and second pretest data is obtained. The first preset information is information preset by a tester. In this embodiment, the first preset information is data 1. The register 3 and the memory 4 are started, the data 1 is written into the register 3 and the memory 4, and the stored information in the register 3 and the memory 4 is read. The parity module 30 is used to measure the parity bits of the read result and form the second pretest data. In step S23, second preset information is written to the register 3 and the memory 4, and third pretest data is obtained. The second preset information is preset information of a tester. In this embodiment, the second preset information is data 0. The register 3 and the memory 4 are started, the data 0 is written into the register 3 and the memory 4, and the stored information in the register 3 and the memory 4 is read. The parity module 30 is used to test the parity bits of the read result and form the third pretest data.
Referring to fig. 1 to 3, in an embodiment of the present invention, step S21, step S23 and step S23 are performed in sequence, and step S24 may be performed after the first pretest data, the second pretest data and the third pretest data are obtained. The sequential step S24 may also be performed every time parity information is obtained. In the present embodiment, step S24 is performed, for example, after all three parity information are obtained. Step S24 is performed on the first pretest data, the second pretest data, and the third pretest data, respectively, to complete the formulation of the comparison table information. Wherein the step S24 includes steps S241 to S243.
And S241, sequentially acquiring parity check information.
And S242, judging whether the corresponding comparison information class exists in the storage.
S243, newly establishing the parity check information as a comparison information class.
And S244, classifying and storing the parity check information in the corresponding comparison information class.
S245, calculating the total number of the parity check information and the number of the check results in each comparison information class.
S246, obtaining the comparison information class with the most verification results, and taking the corresponding parity check information as comparison table information.
Referring to fig. 1 to 4, in an embodiment of the invention, first pretest data is taken as an example to illustrate how to make the mapping table information. The number of the first pretest data is consistent with the number of the chips 1 to be tested participating in the pretest. In step S241, first pretest data is sequentially acquired from the check register 40. Specifically, the first pretest data is stored in the memory block 50, and the first pretest data may be extracted in the order of the physical addresses of the memory block 50 and stored in the memory bank. In step S242, it is determined whether or not there is a corresponding matching information class in the storage. Specifically, the first pretest data is compared with the comparison information, and if the first pretest data is not consistent with the comparison information, the step S243 is executed. If yes, go to step S244. In step S243, the first pretest data is newly created as a kind of comparison information class. In step S244, the first pretest data classification is stored in the corresponding comparison information class. And executing steps S241-S244 until all the first pretest data are extracted and classified. In step S245, the total number of pieces of the extracted first pretest data and the number of pieces of the first pretest data in each comparison information class are calculated. If the total number of the first pretest data is consistent with the number of the chips 1 to be tested participating in the test, it is determined that the step S24 is executed accurately. On the contrary, if the total number of the first pretest data is not consistent with the number of the chips 1 under test participating in the test, the test process of step S24 may have a miss. And recycling to obtain the first pretest data or performing manual review to ensure the accuracy of the information of the comparison table. The result of the pretest performed on the chips 1 under test of the same batch should be consistent. However, the result of the pretest may be biased due to component errors of the chip 1 to be tested or hardware errors during the testing process. Therefore, in step S246, the comparison table information is prepared with the comparison information class having the largest number of pieces of test data as a standard. Specifically, the first pretest data classified by the corresponding comparison table information is used as the comparison table information. And executing the same operation on the second pretest data and the third pretest data to correspondingly obtain the comparison table information.
Referring to fig. 1 to 4, in one embodiment of the present invention, when the lookup table information is obtained, the number of the check results of the lookup table information is greater than half of the total number. If the number of the generated comparison information classes is too large and the comparison information classes with no result occupying obvious advantages, such as exceeding half of the total number, judging that the problems of hardware type selection and hardware equipment testing possibly occur in the pretest process, and repeating the steps S241-S246. If the same problem still appears, the manual review is carried out. Take the first pretest data as an example. For example, if there are 100 chips 1 to be pre-tested, the obtained first pre-test data is 100 pieces. For example, 95 of the 100 pieces of first pretest data are the same, and the other 5 pieces of first pretest data have different results, the information of the 95 pieces of first pretest data is used as the information of the comparison table, and the test process of the other 5 pieces of first pretest data is manually reviewed. The number of the results of each reference information class in 100 pieces of first pretest data is, for example, 40, for example, 20, for example, 25, and, for example, 15. And if the test result is not accurate, the information of the comparison table is formulated again.
Referring to fig. 1, fig. 2 and fig. 5, in an embodiment of the invention, in step S20, first lookup table information is obtained according to the first pretest data. And obtaining second comparison table information according to the second pretest data. And obtaining third comparison table information according to the third pretest data. The first, second, and third collation table information are stored in the test unit so as to be taken as a reference in step S30. In step S30, the chip 1 to be tested is comprehensively tested, and the test result is compared with the first comparison table information, the second comparison table information, and the third comparison table information, so as to determine whether the chip 1 to be tested is available. Specifically, the step S30 includes steps S31 to S34.
S31, reading the default storage information of the storage module, and acquiring first parity check information.
S32, judging whether the first parity check information is consistent with the first comparison table information.
And S33, writing all 1' S to the storage module, reading the storage information of the storage module, and acquiring second parity check information.
And S34, judging whether the second parity check information is consistent with the second comparison table information.
S35, writing all 0S to the storage module, reading the storage information of the storage module, and acquiring third parity check information.
And S36, judging whether the third parity check information is consistent with the third comparison table information.
Referring to fig. 1, fig. 2 and fig. 5, in an embodiment of the present invention, in step S31, the default storage information in the storage module 2 is read. Specifically, the default storage information of the plurality of registers 3 is read, the enable signal 1 is sent to the parity check module 30, the parity check module 30 starts to operate, the first parity check information of the registers 3 is obtained, and the first parity check information is stored in the check register 40 of the first test unit 10. Likewise, the default storage information of the plurality of memory cells 41 is read, the first parity information is obtained, and the first parity information is stored in the check register 40 of the second test unit 20. In step S32, it is determined whether the first parity information matches the first lookup table information. If the results are not consistent, step S40 is executed, the chip 1 to be tested is treated as a waste chip, and the subsequent steps are not executed. If the result is consistent, step S33 is executed.
Referring to fig. 1, fig. 2 and fig. 5, in an embodiment of the present invention, before step S33 is executed, an enable signal 0 is sent to the parity module 30, so that the parity module 30 stops working. In step S33, a signal for writing the first preset information and a start enable signal are sent to the memory module 2, so that the memory module 2 starts to write the first preset information. The transmission start enable signal is, for example, an enable signal 1, and causes the register 3 and the memory 4 to start operating. The first preset information is data 1, and the storage module 2 is fully written with the data 1. Specifically, data 1 is written into the register 3 and the memory 4, wherein the register 3 is 32 bits, for example, or 8 bits, for example, and then each bit of the register 3 is written with data 1. An enable signal 1 is sent to the parity check module 30 to start the operation of the parity check module 30. The storage information in the storage module 2 is read out, and the parity bits of the read data are tested by the parity module 30 to form second parity information. In step S34, the second parity information and the second comparison table information are compared, and if the second parity information and the second comparison table information are different, step S40 is executed to treat the chip 1 to be tested as a waste chip. If the second parity information and the second lookup table information are identical, step S35 is performed.
Referring to fig. 1, fig. 2 and fig. 5, in an embodiment of the present invention, before the step S35 is executed, an enable signal 0 is sent to the parity module 30, so that the parity module 30 stops operating. And sending a signal for writing the first preset information and a stop enable signal to the storage module 2. Specifically, the disable enable signal is, for example, an enable signal 0. The enable signal of the memory module 2 is set to 0, so that the memory module 2 stops writing the first preset information, for example, stops writing all 1 s, so as to enable the second preset information to be input. In step S35, a signal for writing the second preset information and a start enable signal are transmitted to the memory module 2. Specifically, the enable signals of the register 3 and the memory 4 are set to 1, so that the memory module 2 starts to write the second preset information. The second preset information is, for example, data 0, and the number of bits of the data 0 is consistent with the number of bits of the memory module 2. The data 0 is written into the memory module 2, and the parity module 30 is started again, and the storage information of the memory module 2 is read out. Specifically, the enable signal 1 is sent to the parity check module 30, and the parity check module 30 checks the number of parity bits of the storage information read by the storage module 2 to form third parity check information. And comparing the third parity check information with the third comparison table information, if the third parity check information is inconsistent with the third comparison table information, executing the step S40, and treating the chip 1 to be tested as a waste chip. If the third parity check information is consistent with the third comparison table information, step S50 is executed to put the chip 1 to be tested into storage. Before step S50 is executed, an enable signal 0 is sent to the parity block 30, and the parity block 30 is stopped. And keeping writing the second preset information, and setting the enable signal of the storage module 2 to be 0, so as to stop writing the second preset information, and complete the reset of the chip 1 to be tested, thereby finishing the test of the chip 1 to be tested.
Referring to fig. 1 to 6, the present invention provides a test system 100, wherein the test system 100 includes a configuration module 101, a pre-test module 102, a read-write test module 103, and a comparison module 104. The configuration module 101 is configured to configure a test unit on the chip 1 to be tested. The pretest module 102 is configured to apply the test unit, perform read-write pretest on the chip 1 to be tested, obtain storage information of the chip 1 to be tested in multiple states, and use the storage information of the chip 1 to be tested in multiple states as comparison table information. The read-write test module 103 is configured to test parity check information of the chip 1 under test in a default state, a state of writing the first preset information, and a state of writing the second preset information. The comparison module 104 is configured to compare the parity information with the comparison table information, and when the parity information does not conform to the comparison table information, treat the chip 1 to be tested as a waste chip.
Referring to fig. 7, the present invention further provides an electronic device, where the electronic device includes a processor 5 and a storage device 6, the storage device 6 stores program instructions, and the processor 5 executes the program instructions to implement the above-mentioned method for configuring a data model. The Processor 5 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC) or other programmable logic device, discrete gate or transistor logic device, discrete hardware component; the Memory device 6 may include a Random Access Memory (RAM) and may also include a Non-Volatile Memory (Non-Volatile Memory), such as at least one disk Memory. The Memory device 6 may also be an internal Memory of Random Access Memory (RAM) type, and the processor 5 and the Memory device 6 may be integrated into one or more independent circuits or hardware, such as: application Specific Integrated Circuit (ASIC). It should be noted that the computer program in the storage device 6 can be implemented in the form of software functional units and stored in a computer readable storage medium when the computer program is sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, an electronic device, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention.
Referring to fig. 8, the present invention further provides a computer-readable storage medium 71, where the computer-readable storage medium 71 stores computer instructions 7, and the computer instructions 7 are used for causing the computer to execute the above-mentioned method for configuring a data model. The computer readable storage medium 71 may be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system or propagation medium. The computer-readable storage medium 71 may also include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a Random Access Memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Optical disks may include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-RW), and DVD.
Referring to fig. 1 to 8, a testing system and a testing method provided by the present invention are applied in a packaging and testing apparatus 200. The encapsulation device 200 includes a hardware platform 201 and a software platform 202. The hardware platform 201 includes a power supply unit 2011, a communication unit 2012, a read-write unit 2013, and a control unit 2014. The power supply unit 2011 may provide power to the software platform 202 and the chip 1 to be tested. The communication unit 2012 is electrically connected to the chip 1 to be tested and can send a control signal to the chip 1 to be tested. Specifically, for example, an enable signal 1 or 0 is sent to the register 3, and an enable signal 1 or 0 is sent to the parity check module 30. The read-write unit 2013 supports read-write operation on the chip 1 to be tested. The control unit 2014 is electrically connected to the power supply unit 2011, the communication unit 2012 and the read/write unit 2013, wherein the control unit 2014 may be the processor 5. The communication unit 2012 may be a communication module, a communication Interface, such as a Universal Serial Bus (USB), a Serial Peripheral Interface (SPI), and a communication device such as a repeater or a gateway. The chip 1 to be tested is electrically connected to the hardware platform 201, and the test system 100 is loaded on the software platform 202. Through the establishment of the software platform 202, the test system of the chip 1 to be tested can be operated on the hardware platform 201, the read-write control of the register 3 and the memory 4 is realized, data generated by the read-write of the register 3 and the memory 4 can be stored locally, and the data generated by the read-write can be compared with the information of the comparison table.
Referring to fig. 1 to 8, in an embodiment of the present invention, the lookup table information obtained in step S20 may be stored in the software platform 202, so as to be called to participate in the comparison of the parity information at any time. In the same series of chips 1 to be tested, the same set of look-up table information may be applied. In this embodiment, by testing the default state, the all-1-write state, and the all-0-write state of the chip 1 to be tested, it is possible to directly determine whether the register 3 and the memory 4 have problems by controlling signals of the register 3 and the memory 4. And a mounting space for the test unit can be reserved on the chip 1 to be tested to facilitate the loading of the test unit. The register 3 and the memory 4 can be called for testing at any time, the testing is quick, and the testing time can be saved by 50 times. And the testing apparatus 200 can test a plurality of different types of chips 1 to be tested. The chip 1 to be tested of different models has the same external requirements, and according to the built-in test system and the test method based on the test system provided by the invention, only the universal encapsulation equipment 200 is needed for enabling the software platform 202 to communicate with the chip 1 to be tested. In other embodiments of the present invention, the rewriting register 3 may also be controlled by means of external communication.
Referring to fig. 1 and 2 and fig. 6 and 9, in an embodiment of the present invention, in step S32, step S34 and step S36, if the contents of the parity information and the comparison table information are inconsistent, the storage information and the numerical value of the corresponding register 3 or memory 4 are stored in the check register 40, specifically, in the failure result page of the corresponding storage block 50. The test result may also be synchronously stored in the software platform 202, so as to trace and retrieve the read-write test result. The test unit and the program instruction corresponding to the test method of the present invention may be packaged as a software test package, and the software test package is run by the software platform 202. When the chip 1 to be tested is subjected to packaging test, the test on the register 3 and the memory 4 can be automatically completed. Whether the storage module 2 of the chip 1 to be tested is invalid is confirmed by checking the storage data of the software platform 202, and the corresponding chip 1 to be tested is marked, so that the chip 1 to be tested is distributed and put in storage.
The invention provides a test method and a test system of a memory chip. Based on the test system, the configuration of the test unit can be carried out on the chip to be tested, and the read-write pretest can be carried out on the chip to be tested in various states. The method comprises the steps of obtaining comparison table information of a chip to be tested in various states through read-write pretest of the chip to be tested. And testing the storage information of the chip to be tested in a default state, a state of writing in the first preset information and a state of writing in the second preset information through the read-write testing module, and acquiring the parity check information for reading out the storage information through the parity check module. The parity check information and the comparison table information are compared through the comparison module, so that whether the storage module of the chip to be tested fails or not is judged, and the chip to be tested is conveniently distributed into different storehouses.
In the description of the present specification, reference to the description of the terms "present embodiment," "example," "specific example," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A method for testing a memory chip is characterized by at least comprising the following steps:
providing a chip to be tested, and configuring a test unit in the chip to be tested;
performing read-write pretest on the chip to be tested through the test unit, respectively acquiring the number of parity bits of the stored information of the storage chip when the information is not written and when various preset information is written, and correspondingly setting comparison table information according to the parity bits acquired in different writing states;
testing parity check information of the chip to be tested when information is not written and preset information is written; and
and respectively comparing the parity check information and the corresponding comparison table information when information is not written and when different preset information is written, and treating the chip to be tested as a waste chip when any pair of parity check information and comparison table information in the same writing state are inconsistent.
2. The method according to claim 1, wherein the step of performing read-write pretest on the chip to be tested through the test unit comprises:
reading the storage information of the chips to be tested when information is not written in and the storage information when the preset information is written in to form pretest data; and
and counting and screening the pretest data to obtain comparison table information.
3. The method as claimed in claim 2, wherein the step of counting and screening the pretest data comprises:
obtaining the number of samples of the chip to be tested for pretesting, and taking half of the number of samples of the chip to be tested as a screening threshold; and
dividing the pretest data into a plurality of comparison information classes according to the content of the pretest data, and acquiring the number of the pretest data of the comparison information classes; and
and when the number of the pretest data exceeds the screening threshold value, recording the comparison information as comparison table information.
4. The method for testing the memory chip according to claim 1, wherein the step of testing the parity information of the chip to be tested when no information is written and when preset information is written comprises the steps of:
reading default storage information of the chip to be tested, and acquiring odd-even digits of the default storage information;
writing the preset information into the chip to be tested, reading the written storage information of the chip to be tested, and acquiring the parity bit number of the written storage information; and
and recording the parity bit number of the default storage information and the parity bit number of the written storage information as parity check information.
5. The method as claimed in claim 4, wherein the step of writing the predetermined information comprises:
writing first preset information into the chip to be tested, and acquiring the number of odd-even bits written into the first preset information;
resetting the chip to be tested, writing second preset information into the chip to be tested, and acquiring the odd-even bit number of the second preset information.
6. The method as claimed in claim 5, wherein the step of writing the first predetermined information into the chip to be tested comprises: and sending a signal for writing the first preset information and a start enabling signal to the chip to be tested.
7. The method according to claim 5, wherein the step of resetting the chip under test comprises: and sending a signal for writing the first preset information and a stop enabling signal to the chip to be tested.
8. The method as claimed in claim 1, wherein the step of configuring the test unit in the chip to be tested comprises:
reserving a configuration area on the chip to be tested, and setting a parity check unit and a check register on the configuration area;
electrically connecting the check register to an output end of the parity check unit; and
and establishing a mapping relation between the check register and the chip to be tested.
9. The method according to claim 8, wherein the step of establishing a mapping relationship between the check register and the chip to be tested comprises:
acquiring first physical address information of a register and a memory in the chip to be tested;
acquiring second physical address information of a storage block in the check register; and
and associating the first physical address information and the second physical address information, and forming mapping table information.
10. A system for testing a memory chip, comprising:
the configuration module is used for configuring a test unit in the chip to be tested;
the pre-test module is used for applying the test unit, performing read-write pre-test on the chip to be tested, respectively acquiring the parity bit number of the storage information of the storage chip when the information is not written and when various preset information is written, and correspondingly setting comparison table information according to the parity bit number acquired in different writing states;
the read-write testing module is used for testing the parity check information of the chip to be tested in a default state, a state of writing first preset information and a state of writing second preset information; and
and the comparison module is used for respectively comparing the parity check information and the corresponding comparison table information when information is not written and different preset information is written, and when any pair of parity check information and comparison table information in the same writing state are inconsistent, treating the chip to be detected as a waste chip.
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