CN114639437A - Memory test method, device, equipment and storage medium - Google Patents
Memory test method, device, equipment and storage medium Download PDFInfo
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
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Abstract
The disclosure provides a test method, a test device, test equipment and a storage medium of a memory, and relates to the technical field of semiconductors. The testing method of the memory comprises the following steps: acquiring a first check code of at least one test file; mapping at least one test file into a memory to generate a mapping file; after executing preset test operation to the memory, acquiring a second check code of the mapping file; and determining the state of the memory according to the first check code and the second check code. According to the scheme provided by the embodiment of the disclosure, the application scene of the memory in the use process is simulated by mapping at least one test file into the memory, then the memory is subjected to preset test operation, and whether the memory is abnormal or not is determined by comparing check codes before and after the test operation, so that the test randomness and accuracy are improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method, an apparatus, a device, and a storage medium for testing a memory.
Background
The memory is the most important component of intelligent equipment and computers, and programs in the equipment are operated in the memory. The Memory plays a crucial role in system performance and stability, whether DDR (Double Data Rate SDRAM (Double Data Random Access Memory), LPDDR (Low Power Double Data Rate SDRAM, Low Power Memory technology). Therefore, it is necessary to ensure the reliability of the memories used in these devices, and testing of the memories is necessary.
Currently, many test tools for memories exist in operating systems, but most test tools test a memory by writing predetermined data into the memory, reading the data, and comparing whether the data are consistent. Although these testing tools are highly targeted, they can be started to continuously test selected memory areas in the memory, but they cannot be combined with actual user behavior. For example, mobile devices often enter a standby state, and the like.
Disclosure of Invention
The following is a summary of subject matter that is described in detail in this disclosure. This summary is not intended to limit the scope of the claims.
The disclosure provides a method, an apparatus, a device and a storage medium for testing a memory.
According to a first aspect of the embodiments of the present disclosure, there is provided a method for testing a memory, the method comprising:
acquiring a first check code of at least one test file;
mapping the at least one test file into the memory to generate a mapping file;
after executing a preset test operation to the memory, acquiring a second check code of the mapping file;
and determining the state of the memory according to the first check code and the second check code.
According to some embodiments of the present disclosure, determining the state of the memory from the first parity and the second parity comprises:
and when the second check code is inconsistent with the first check code, determining that the memory is abnormal.
According to some embodiments of the present disclosure, the method of testing a memory further comprises:
when the second check code is inconsistent with the first check code, storing a mapping file corresponding to the second check code inconsistent with the first check code and address information of the memory with abnormity.
According to some embodiments of the present disclosure, the method of testing a memory further comprises:
and comparing the inconsistent data in the test file corresponding to the first check code and the mapping file corresponding to the second check code, and determining the abnormal address information of the memory.
According to some embodiments of the disclosure, the first check code comprises a first hash value and the second check code comprises a second hash value.
According to some embodiments of the disclosure, the preset test operation comprises:
under a preset condition, carrying out a pressure test on the memory for a first preset time;
and awakening the memory after the memory is dormant for a second preset time.
According to some embodiments of the disclosure, the preset condition comprises:
the data quantity transferred to the memory in unit time is larger than or equal to the data quantity allowed to be transferred in unit time of the memory.
According to some embodiments of the present disclosure, the method of testing a memory further comprises:
and when the second check code is inconsistent with the first check code, canceling the corresponding data of the mapping file in the memory.
According to some embodiments of the disclosure, mapping the at least one test file into the memory comprises:
mapping the at least one test file to a storage unit corresponding to at least one memory address to be tested of the storage;
and the size of the storage unit corresponding to the at least one memory address to be tested is the same as that of the at least one test file.
According to some embodiments of the present disclosure, when the at least one test file is plural, sizes of the plural test files are the same or different.
According to some embodiments of the present disclosure, each of the test files corresponds to a first check code.
According to some embodiments of the disclosure, the at least one test file comprises at least one binary file.
According to some embodiments of the disclosure, the memory comprises volatile memory.
According to some embodiments of the disclosure, the at least one test file is stored to a non-volatile memory of a device in which the memory is located.
According to a second aspect of the embodiments of the present disclosure, there is provided a test apparatus of a memory, the test apparatus of the memory including:
the acquisition module is configured to acquire a first check code of the at least one test file;
a mapping module configured to map the at least one test file into the memory, generating a mapped file;
the execution module is configured to acquire a second check code of the mapping file after executing a preset test operation to the memory;
a determination module configured to determine a state of the memory based on the first parity and the second parity.
According to some embodiments of the disclosure, the determining module is configured to, when the second check code is inconsistent with the first check code, save a mapping file corresponding to the second check code inconsistent with the first check code and address information of the memory where the memory is abnormal.
According to a third aspect of embodiments of the present disclosure, there is provided a test apparatus of a memory, the test apparatus of the memory including:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to perform the method of testing a memory according to the first aspect.
According to a fourth aspect of embodiments of the present disclosure, there is provided a non-transitory computer-readable storage medium, wherein instructions, when executed by a processor of a test apparatus of a memory, enable the test apparatus of the memory to perform the method of testing the memory according to the first aspect.
In the method, the device, the equipment and the storage medium for testing the memory provided by the embodiment of the disclosure, the application scene of the memory in the use process is simulated by mapping at least one test file into the memory, then the memory is subjected to preset test operation, and whether the memory is abnormal or not is determined by comparing check codes before and after the test operation, so that the test randomness and the test accuracy are improved.
Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the disclosure. To a person skilled in the art, without inventive effort, other figures can be derived from these figures.
FIG. 1 is a flow chart illustrating a method of testing a memory in accordance with an exemplary embodiment;
FIG. 2 is a flow chart illustrating a method of testing a memory in accordance with an exemplary embodiment;
FIG. 3 is a flow diagram illustrating the execution of a predetermined test operation to a memory in accordance with an exemplary embodiment;
FIG. 4 is a block diagram illustrating a test setup for a memory in accordance with an exemplary embodiment;
FIG. 5 is a block diagram illustrating a test equipment for a memory according to an example embodiment.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the embodiments described are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.
File verification is a verification method commonly used in testing whether an exception occurs in a memory. Common file Check algorithms include parity Check and Cyclic Redundancy Check (CRC), but these two checks do not have the capability of resisting data tampering, and they can Check and correct channel errors in the data transmission process to some extent, but cannot prevent the data from being maliciously damaged.
The invention provides a testing method of a memory, which simulates the similar state of a user in the actual use process of the memory, is used for covering application scenes that a device stores a large number of files into the memory in the use process and a system enters dormancy standby and the like, and judges whether a test file is modified by using a check code, so that whether the memory is abnormal in the application process can be accurately tested, and the randomness and the accuracy of a test result are improved.
Fig. 1 is a flowchart illustrating a testing method of a memory according to an exemplary embodiment of the present disclosure, and referring to fig. 1, the testing method includes the following steps:
step S110, acquiring a first check code of at least one test file;
step S120, mapping at least one test file into a memory to generate a mapping file;
step S130, after executing the preset test operation to the memory, acquiring a second check code of the mapping file;
in step S140, the state of the memory is determined according to the first check code and the second check code.
In step S110, the test files used in the test process are traversed, and the first check code of each test file is calculated and stored. The adopted test files can be one or a plurality of, and the sizes of the plurality of test files can be the same or different.
In step S120, at least one test file is mapped to a memory to be tested, and a mapping file is generated.
The file mapping is a new file data access mechanism provided by an operating system, which can reserve a part of space for a file in a memory space and map the file into the reserved space, once the file is mapped, the operating system manages tasks such as page mapping buffering and caching, and the like, without calling an Application Programming Interface (API) function for allocating and releasing memory blocks and file input/output, and without providing any buffering algorithm by the operating system.
The specific operation mode of the mapping process is as follows: opening a test file, calling mmap (memory mapping) interface, and mapping the test file to the memory to be tested in a read-only mode. After the mapping is completed, other operations, such as a memory copy (memcpy) operation, a read-write operation, and the like, can still be performed on the memory as if the normal memory is accessed.
The embodiment of the disclosure generates the mapping file in the memory to be tested, so as to simulate application scenarios such as the memory being written with the file and entering sleep standby. After the mapping file is generated, a preset test operation is performed on the memory, so that the memory in use or in dormancy can be simulated to be tested.
In step S130, after the preset test operation is performed on the memory for generating the mapping file, the second check code of the mapping file is calculated, and whether the mapping file is rewritten during the execution of the preset test operation can be determined by determining whether the check code changes, that is, whether the first check code and the second check code are the same.
In step S140, it can be determined whether the mapping file is rewritten according to the comparison between the first check code and the second check code, and further it is determined whether the state of the memory is normal or abnormal, if the first check code is the same as the second check code, it indicates that the mapping file is not rewritten, and if the first check code is different from the second check code, it indicates that the mapping file is rewritten.
The method and the device for testing the memory are used for simulating the application scene of the memory in the using process by mapping at least one test file into the memory to be tested, then carrying out preset test operation on the memory, and determining whether the memory is abnormal or not by comparing check codes before and after the preset test operation is carried out.
In some embodiments, the step S140 of determining the state of the memory according to the first check code and the second check code includes:
and when the second check code is inconsistent with the first check code, determining that the memory is abnormal.
According to the characteristic of the hash algorithm, when the second check code is inconsistent with the first check code, the content of the mapping file is inconsistent with the content of the test file, so that the mapping file can be determined to be rewritten in the process of executing the preset test operation on the memory, and the memory is further determined to be abnormal. Of course, it is understood that, besides the hash algorithm, other related algorithms such as an asymmetric encryption algorithm may be used to verify whether the first check code and the second check code are consistent.
Fig. 2 is a flowchart illustrating a method for testing a memory in an exemplary embodiment, and referring to fig. 2, the method for testing a memory in the present embodiment includes the following steps in addition to the steps in the above embodiment:
step S150, when the second check code is inconsistent with the first check code, saving the mapping file corresponding to the second check code inconsistent with the first check code and the address information of the memory with exception.
When the second check code is inconsistent with the first check code, the mapping file corresponding to the inconsistent second check code is rewritten, so that the memory address corresponding to the mapping file can be determined to be abnormal, and the address information corresponding to the rewritten mapping file can be directly stored, namely the address information of the memory with the abnormality. Meanwhile, the mapping file corresponding to the inconsistent second check code is saved, so that the content of the mapping file can be analyzed subsequently, the rewritten content and the address information and the like corresponding to the rewritten content can be found out, and the abnormal position of the memory can be accurately positioned.
It is difficult to determine whether all the contents of the rewritten mapping file are rewritten and the position corresponding to the specific rewritten contents when only part of the contents are rewritten, and the address information corresponding to one mapping file is a piece of address information, not a specific address information, so that it is not possible to directly determine the specific position where the address information of the piece is abnormal based on the address information corresponding to the rewritten mapping file. If the position corresponding to the specific rewritten content in the mapping file is to be determined, the content of the mapping file needs to be acquired, compared with the content of the test file corresponding to the mapping file, and analyzed.
In some embodiments, the testing method further comprises:
and comparing the data in the test file corresponding to the inconsistent first check code and the data in the mapping file corresponding to the second check code, and determining the abnormal address information of the memory.
The data of the test file corresponding to the inconsistent first check code and the data of the mapping file corresponding to the second check code are compared, namely the data in the rewritten mapping file and the data in the test file corresponding to the mapping file are compared, and the position of the rewritten data of the mapping file can be accurately determined according to the position of the inconsistent data, so that the address information corresponding to the rewritten data in the mapping file can be determined, the address information of the specific abnormal position of the memory can be further determined, the accurate positioning of the abnormal position of the memory is realized, and the test accuracy is improved.
In some exemplary embodiments, the first check code includes a first hash value and the second check code includes a second hash value.
Hash algorithms (Hash Algorithm), also known as Hash algorithms, Hash functions, are a method of creating small digital "fingerprints" from any kind of data. The hash algorithm mixes the data again to recreate a hash value.
The Hash algorithm is mainly used for preventing errors in the computer transmission process and guaranteeing the authenticity and integrity of data. The hash algorithm mainly comprises MD4, MD5 and SHA. Wherein, the digital digest of the MD5 Hash file is obtained by calculation of a Hash function. Regardless of the file length, the result of the Hash function calculation is a fixed-length number.
Unlike encryption algorithms, Hash algorithms are irreversible one-way functions. The hash value can be quickly calculated from the raw data of the file, but it is substantially impossible to derive the raw data from the hash value. For example, MD5 and SHA, two different files are almost impossible to obtain the same hash value, and the obtained hash values are very different as long as the original data is slightly changed. Therefore, the file can be accurately detected once modified by using a hash algorithm for testing.
The embodiment of the disclosure adopts a hash algorithm, calculates a first hash value of each test file by traversing each test file, calculates a second hash value of each mapping file after executing a preset test operation, and judges whether the mapping file is consistent with the corresponding test file by using the characteristic of the hash value and whether the second hash value is consistent with the first hash value, thereby determining whether the mapping file is rewritten and determining whether the memory is abnormal, so that data is not required to be directly written into the memory and the test is performed, the test method is closer to the actual application scene of the memory in the use process, and the accuracy of the detection result is improved.
When the second hash value is inconsistent with the corresponding first hash value, the mapping file corresponding to the inconsistent second hash value is saved, the content of the mapping file is compared with the content of the corresponding test file, the address information corresponding to the specific position of the rewritten content of the mapping file can be determined, and the abnormal address information of the memory can be accurately determined.
FIG. 3 is a flow chart illustrating implementation of a predetermined test operation on a memory in an exemplary embodiment, and referring to FIG. 3, in some embodiments, after generating a mapping file, the predetermined test operation performed on the memory includes:
step S131, under a preset condition, performing a pressure test on the memory for a first preset duration;
step S132, the memory is awakened after sleeping for a second preset time.
In step S131, a pressure test is performed on the memory generating the mapping file under a preset condition for a first preset time period to fully test the memory. The first preset time period may be set according to a data amount required for performing the pressure test, or may be set according to a characteristic of the memory to be tested.
Illustratively, the stress test may include pressurizing the memory by increasing the amount of read/write data, or by increasing the load of the system CPU or increasing the computational task of the system CPU, i.e., pressurizing the CPU and thus pressurizing the memory, so that the memory is tested under high load conditions.
In step S132, by hibernating the memory after performing the stress test, a hibernation application scenario of the memory during use can be simulated.
In different test processes for the same memory address or test processes for different memory addresses, the data amount transmitted to the memory in the unit time used for performing the stress test may be the same or different, and the first preset time for performing the stress test may be the same or different.
Suitably, the second preset time duration for the memory to sleep may be the same or different in different test processes for the same memory address or in different test processes for different memory addresses.
In some embodiments, the preset conditions for performing the stress test on the memory include:
the amount of data transferred to the memory per unit time is greater than or equal to the amount of data allowed to be transferred per unit time of the memory.
The embodiment of the disclosure realizes the pressurization test of the overload or full load data transmission of the memory by using the test data volume which is larger than or equal to the data volume allowed to be transmitted in the unit time of the memory to be tested, so as to fully test whether the memory has an abnormal state or not.
In some embodiments, the testing method further comprises:
and when the second check code is inconsistent with the first check code, the corresponding data of the mapping file in the memory is canceled.
In the embodiment of the disclosure, after determining the address information of the memory in the abnormal state according to the inconsistent first check code and the inconsistent second check code and saving the mapping file corresponding to the inconsistent second check code, the corresponding data of the mapping file in the memory can be cancelled, so as to reduce unnecessary occupation of the memory and facilitate accurate execution of a subsequent test process.
In some embodiments, the testing method further comprises: when the second check code is consistent with the first check code, the corresponding data of the mapping file in the memory can be cancelled, so that unnecessary occupation of the memory is reduced, and the accurate execution of the subsequent test process is facilitated.
According to some embodiments of the present disclosure, mapping at least one test file into a memory comprises:
mapping at least one test file to a storage unit corresponding to at least one memory address to be tested of the storage;
the size of the storage unit corresponding to at least one memory address to be tested is the same as the size of at least one test file.
The testing method of the memory provided by the embodiment of the disclosure needs to prepare the testing files in advance, and the number and the size of the testing files can be determined according to the storage space of the memory to be tested. The total size of the prepared test files is matched with the storage space of the memory to be tested, namely the sum of the sizes of the test files is matched with the sum of the storage spaces of the storage units to be tested of the memory to be tested.
When the number of the prepared test files is multiple, all the test files can be mapped into the to-be-tested memory at one time in the test process, and then the test is carried out on all the memory addresses of the memory according to the test requirement, or the test is carried out on part of the to-be-tested memory addresses of the memory; or selecting a part of test files according to the size of the storage unit corresponding to the memory address to be tested, mapping the test files to the storage unit corresponding to the memory address to be tested, and then testing the memory address generating the mapping file.
That is, after all the test files are mapped, the memory addresses of all the mapped files can be tested simultaneously, and the memory addresses of some of the mapped files can also be tested; and mapping part of the test files, and then testing the memory addresses where the mapping files are located.
In some embodiments, when the at least one test file is plural, the sizes of the plural test files are the same or different.
In this embodiment, through a plurality of test files with the same or different sizes, different numbers of test files can be selected for mapping, so as to meet the requirement for testing the storage units corresponding to part of the to-be-tested memory addresses of the memory.
According to some embodiments of the present disclosure, each test file corresponds to one first check code. Correspondingly, each test file corresponds to one mapping file, each mapping file corresponds to one second check code, and therefore, one first check code corresponds to one second check code, and whether the memory address in the memory where the mapping file corresponding to the second check code is located is abnormal or not can be determined by comparing whether the second check code is consistent with the corresponding first check code or not, that is, whether the memory is abnormal or not can be determined.
In some exemplary embodiments, the at least one test file comprises at least one binary file.
In some embodiments, the memory tested by the scheme provided by the present disclosure comprises volatile memory. That is, the mapping location of the test file is in the memory cell corresponding to the to-be-tested memory address of the volatile memory.
Since the test file and its first check code are the basis for determining whether an exception exists in the memory, in some embodiments, at least one test file is stored in a non-volatile memory of the device in which the memory is located. For example, the test file may be stored on a hard disk, a removable hard disk, or a U disk of the device.
According to the embodiment of the disclosure, the test file is stored in the nonvolatile memory, so that the test file and the first check code thereof are prevented from being tampered, and the reliability of the test result is ensured.
According to a second aspect of the embodiments of the present disclosure, a test apparatus of a memory is also provided. FIG. 4 is an exemplary embodiment
Referring to fig. 4, a schematic structural diagram of a testing apparatus 200 for a memory according to an embodiment is shown, in which the testing apparatus 200 includes: an acquisition module 210, a mapping module 220, an execution module 230, and a determination module 240. Wherein, the first and the second end of the pipe are connected with each other,
the obtaining module 210 is configured to obtain a first check code of at least one test file;
the mapping module 220 is configured to map at least one test file into a memory, generating a mapped file;
the execution module 230 is configured to obtain the second check code of the mapping file after the preset test operation is performed on the memory;
the determination module 240 is configured to determine a state of the memory based on the first parity and the second parity.
The method and the device for testing the memory are used for simulating the application scene of the memory in the using process by mapping at least one test file into the memory to be tested, then carrying out preset test operation on the memory, and determining whether the memory is abnormal or not by comparing check codes before and after the preset test operation is carried out.
The testing apparatus 200 for a memory provided by the embodiment of the present disclosure may include any combination of different types of nonvolatile memory devices and/or volatile memory devices. Volatile Memory devices, such as Memory devices, may include, but are not limited to, Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM).
In the memory testing apparatus 200, the obtaining module 210 may be a microcontroller, a special-purpose logic Circuit system, such as a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), or other suitable processor.
The mapping module 220 may be a device including a mmap interface, e.g., a processor including a mmap interface. Illustratively, the mapping module 220 may employ a microprocessor or central processing unit.
The execution module 230 may be one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. Illustratively, the execution module 230 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other Instruction sets, or processors implementing a combination of Instruction sets. The execution module 230 may also be one or more special-purpose Processing devices, such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, and so forth.
The determination module 240 may comprise a processor means of a comparator.
According to some embodiments of the present disclosure, the determining module 240 is further configured to, when the second check code is inconsistent with the first check code, save the mapping file corresponding to the second check code inconsistent with the first check code and the address information of the memory where the exception occurs.
According to the characteristic of the hash algorithm, when the second check code is inconsistent with the first check code, the content of the mapping file is inconsistent with the content of the test file, so that the mapping file can be determined to be rewritten in the process of executing the preset test operation on the memory, and the memory is further determined to be abnormal.
When the second check code is inconsistent with the first check code, the mapping file corresponding to the inconsistent second check code is rewritten, so that the memory address corresponding to the mapping file can be determined to be abnormal, and the address information corresponding to the rewritten mapping file can be directly stored, namely the address information of the memory with the abnormality. Meanwhile, the mapping file corresponding to the inconsistent second check code is saved, so that the content of the mapping file can be analyzed subsequently, the rewritten content and the address information and the like corresponding to the rewritten content can be found out, and the abnormal position of the memory can be accurately positioned.
It is difficult to determine whether all the contents of the rewritten mapping file are rewritten and the position corresponding to the specific rewritten contents when only part of the contents are rewritten, and the address information corresponding to one mapping file is a piece of address information, not a specific address information, so that it is not possible to directly determine the specific position where the address information of the piece is abnormal based on the address information corresponding to the rewritten mapping file. If the position corresponding to the specific rewritten content in the mapping file is to be determined, the content of the mapping file needs to be acquired, compared with the content of the test file corresponding to the mapping file, and analyzed.
With regard to the test apparatus in the above embodiment, the specific manner in which each module performs the operation has been described in detail in the above embodiment related to the test method, and will not be described in detail here.
FIG. 5 is a block diagram illustrating a test apparatus for memory, i.e., a computer apparatus 300, according to an example embodiment. For example, the computer device 300 may be provided as a terminal device. Referring to fig. 5, the computer device 300 includes a processor 310, and the number of the processors may be set to one or more as necessary. Computer device 300 also includes a memory 320 for storing instructions, such as an application program, that are executable by processor 310. The number of the memories can be set to one or more according to needs. Which may store one or more application programs. The processor 310 is configured to execute instructions to perform the above-described method.
As will be appreciated by one skilled in the art, embodiments of the present disclosure may be provided as a method, apparatus (device), or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied in the media. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, including, but not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer, and the like. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
In an exemplary embodiment, a non-transitory computer-readable storage medium comprising instructions, such as memory 320 comprising instructions, executable by processor 310 of device 300 to perform the above-described method is provided. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
A non-transitory computer readable storage medium having instructions therein which, when executed by a processor of a memory testing device, enable the memory testing device to perform a method of testing a memory as described above.
The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of additional like elements in the article or device comprising the element.
While preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various changes and modifications may be made to the disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.
Claims (18)
1. A method for testing a memory, the method comprising:
acquiring a first check code of at least one test file;
mapping the at least one test file into the memory to generate a mapping file;
after executing a preset test operation to the memory, acquiring a second check code of the mapping file;
and determining the state of the memory according to the first check code and the second check code.
2. The method for testing the memory according to claim 1, wherein determining the state of the memory according to the first check code and the second check code comprises:
and when the second check code is inconsistent with the first check code, determining that the memory is abnormal.
3. The method for testing a memory according to claim 1, further comprising:
when the second check code is inconsistent with the first check code, storing a mapping file corresponding to the second check code inconsistent with the first check code and address information of the memory with abnormity.
4. The method for testing a memory according to claim 2, further comprising:
and comparing the inconsistent data in the test file corresponding to the first check code and the mapping file corresponding to the second check code, and determining the abnormal address information of the memory.
5. The method for testing a memory according to claim 1, wherein the first check code includes a first hash value, and the second check code includes a second hash value.
6. The method for testing a memory according to claim 1, wherein the predetermined test operation comprises:
under a preset condition, carrying out a pressure test on the memory for a first preset time;
and awakening the memory after the memory is dormant for a second preset time.
7. The method for testing a memory according to claim 6, wherein the preset condition comprises:
the data quantity transferred to the memory in unit time is larger than or equal to the data quantity allowed to be transferred in unit time of the memory.
8. The method for testing a memory according to claim 1, further comprising:
and when the second check code is inconsistent with the first check code, canceling the corresponding data of the mapping file in the memory.
9. The method of testing a memory of claim 1, wherein mapping the at least one test file into the memory comprises:
mapping the at least one test file to a storage unit corresponding to at least one memory address to be tested of the storage;
and the size of the storage unit corresponding to the at least one memory address to be tested is the same as that of the at least one test file.
10. The method for testing a memory according to claim 1, wherein when the at least one test file is plural, sizes of the plural test files are the same or different.
11. The method for testing a memory according to claim 10, wherein each of the test files corresponds to a first check code.
12. The method of claim 1, wherein the at least one test file comprises at least one binary file.
13. The method of testing a memory of claim 1, wherein the memory comprises a volatile memory.
14. The method for testing a memory according to claim 1, wherein the at least one test file is stored in a non-volatile memory of a device in which the memory is located.
15. A test apparatus for a memory, the test apparatus comprising:
the acquisition module is configured to acquire a first check code of at least one test file;
a mapping module configured to map the at least one test file into the memory, generating a mapped file;
the execution module is configured to acquire a second check code of the mapping file after executing a preset test operation to the memory;
a determination module configured to determine a state of the memory based on the first parity and the second parity.
16. The apparatus for testing a memory according to claim 15, wherein the determining module is configured to save a mapping file corresponding to the second check code that is inconsistent with the first check code and address information of the memory where the memory is abnormal, when the second check code is inconsistent with the first check code.
17. A test apparatus for a memory, the test apparatus comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to perform a method of testing a memory according to any one of claims 1 to 14.
18. A non-transitory computer readable storage medium, wherein instructions in the non-transitory computer readable storage medium, when executed by a processor of a test device of a memory, enable the test device of the memory to perform the test method of the memory according to any one of claims 1 to 14.
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