CN114995093B - Time-to-digital converter, method for processing periodic signal and signal processing system - Google Patents

Abstract

According to a time-to-digital converter, a method of processing a periodic signal, and a signal processing system of the present disclosure, a time-to-digital converter (TDC) identifies whether jitter is present in any one of two periodic signals received as inputs. In one embodiment, jitter is detected by examining first and second count sequences, respectively, of first and second periodic signals received as input signals, wherein the first count sequence represents respective times at which a first sequence of edges having a first direction of the first periodic signal occurs on a time scale, and the second count sequence represents respective times at which a second sequence of edges having the first direction of the second periodic signal occurs on the time scale. Accurate detection of signal jitter can be achieved.

Description

Time-to-digital converter, method for processing periodic signal and signal processing system

Require priority

This patent application relates to an indian provisional patent application entitled "Time-to-Digital Converter (TDC) Architecture for Measuring Phase Differences between Multiple Clocks" filed on 30.9.2021, application No.: IN 202141044473, and claiming priority from this provisional patent application, is incorporated herein IN its entirety to the extent consistent with the description herein.

This patent application also relates TO U.S. patent application entitled "TIME-TO-DIGITAL CONVERTER (TCD) TO OPERATE WITH INPUT CLOCK signal WITH jitter" ("TIME-TO-DIGITAL CONVERTER (TDC) operating WITH jittered INPUT CLOCK signal"), filed on 10/5/2022, application number: US 17/662669, and claiming priority of that US patent application, is incorporated herein in its entirety to the extent consistent with the description herein.

RELATED APPLICATIONS

This application is related To co-pending U.S. patent application entitled "Counter Design for a Time-To-Digital Converter (TDC)" ("Counter Design for Time-To-Digital Converter (TDC)"), filed on even date with US 17/662669, inventor Debasish beehera (debarsh-brahara) et al, the entire contents of which are incorporated herein.

This application relates to co-pending U.S. patent application entitled "Time-to-digital Converter (TDC) Measuring Phase Difference Between Periodic Inputs", filed on the same day as US 17/662669, inventor Debasish Behera (debarsh brahara), et al, the entire contents of which are incorporated herein.

Technical Field

Embodiments of the present disclosure relate generally to time-to-digital converters (TDCs) and, more particularly, to TDCs that operate with an input clock signal having jitter.

Background

TDC is typically used to measure the time interval between a pair of events. The measured values are typically quantized to corresponding digital values. These events are typically voltage or logic level changes of the corresponding signal pairs. TDCs are used in electronic devices such as Phase Locked Loops (PLLs), timing cards, toF (time of flight) measurement devices, such as radiation detectors, diagnostic devices, and the like.

A TDC typically receives a periodic input signal and generates successive digital values representing the phase difference at the corresponding time. Each digital value represents the time difference between corresponding edges (of the same direction) of two periodic inputs. Examples of the periodic signal include a clock signal and the like.

Jitter typically occurs with a clock signal provided as an input to the TDC. Jitter refers to an additional noise component introduced to the clock signal, appearing as a deviation from the desired/nominal period. As is well known in the related art, jitter is introduced due to switching noise, crosstalk, thermal noise, and the like.

Aspects of the present disclosure relate to a TDC adapted to operate with a clock signal having jitter.

Disclosure of Invention

In view of the above, the present application provides a time-to-digital converter, a method of processing a periodic signal, and a signal processing system.

The application discloses a time-to-digital converter, the time-to-digital converter includes: counting logic to generate a first and a second count sequence for a first and a second periodic signal, respectively, received as input signals, the first count sequence representing respective times at which a first sequence of edges having a first direction of the first periodic signal occurs on a time scale, the second count sequence representing respective times at which a second sequence of edges having the first direction of the second periodic signal occurs on the time scale; and core logic to identify whether jitter is present in any of the first and second periodic signals by processing the first and second count sequences.

Optionally, the core logic operates to generate a sequence of phase differences between the first and second periodic signals according to a first method in the absence of jitter and according to a second method in the presence of jitter.

Optionally, wherein the second periodic signal has a frequency that is an integer multiple of a frequency of the first periodic signal, wherein the core logic is further operative to: generating a sequence of window boundaries identifying respective instants at which an edge of the first direction has occurred in both the first and second periodic signals, wherein a duration between two consecutive boundaries constitutes a corresponding window of the sequence of windows; subtracting the respective first counts of the first sequence of counts from the respective subsequences of counts of the second sequence of counts in each window to generate a sequence of time differences in each window, wherein each time difference has a corresponding sign and magnitude, wherein the first method comprises calculating each phase difference in the sequence of phase differences by summing a positive time difference and a negative time difference in separate accumulators, wherein the second method comprises calculating each phase difference in the sequence of phase differences by summing both the positive time difference and the negative time difference into a single accumulator.

Optionally, wherein the time-to-digital converter is operable when the integer multiple is one and when the integer multiple is greater than 1.

Optionally, wherein the core logic includes: an input analyzer module to generate the window boundary sequence from the first count sequence and the second count sequence; and an output generator module to generate one value of a sequence of values in each window of the sequence of windows, wherein the value is indicative of a corresponding phase difference of the window.

Optionally, wherein the output generator module comprises: a subtraction unit for generating the sequence of time differences for each window; a positive minimum generator for selecting a positive minimum representing a minimum of positive values contained in the sequence of time differences; a negative maximum generator for selecting a negative maximum representing a maximum of negative values contained in the time difference sequence; a first accumulator to receive the sequence of positive minima covering a corresponding window and to add values in the sequence of positive minima to generate a first accumulated value; a second accumulator to receive a sequence of the negative maximums covering the corresponding window and to add values in the sequence of the negative maximums to generate a second accumulated value; and a jitter detector module to receive the first and second accumulated values and to generate a jitter present signal indicating whether the jitter is present, wherein the jitter detector module determines that the jitter is present if the accumulated values of both the first and second accumulators have exceeded respective thresholds.

Optionally, wherein the output generator module comprises: a first accumulator output module to receive the first and second accumulation values and to generate a minimum magnitude of the first and second accumulation values as an accumulated phase difference for the corresponding window when it is determined that jitter is not present.

Optionally, wherein one of the first accumulator and the second accumulator is reset to a boundary value when the jitter is determined to be present, wherein the reset accumulator thereafter accumulates one of the positive minimum value and the negative maximum value having a lower magnitude in each window, wherein the first accumulator output module forwards an accumulation value in the reset accumulator to the accumulated phase difference.

Optionally, the output generator module further comprises: a window counter for counting up to a predetermined number of said windows, wherein said first accumulator and said second accumulator are reset when said window counter counts up to said predetermined number of said windows and when said jitter detector module detects the presence of jitter, said reset accumulator for performing an accumulation operation on said predetermined number of said windows before checking again for jitter for a subsequent time difference when it is determined that jitter is present.

Optionally, a second accumulator output module is included for determining a lower magnitude of the first and second accumulated values received at the end of the predetermined number of windows and providing the lower magnitude as an accumulated phase difference when jitter is not present, the second accumulator output module for forwarding the output of the reset accumulator across the predetermined number of windows as the accumulated phase difference when jitter is present.

The present application also discloses a method of processing a periodic signal in a time-to-digital converter, the method comprising: receiving a first and a second count sequence of a first and a second periodic signal, respectively, the first count sequence representing respective times at which a first sequence of edges having a first direction of the first periodic signal occurs on a time scale, the second count sequence representing respective times at which a second sequence of edges having the first direction of the second periodic signal occurs on the time scale; and examining the first and second count sequences to identify whether jitter is present in any of the first and second periodic signals.

Optionally, when the first periodic signal has the same frequency as the second periodic signal, the checking includes: subtracting each count in the first count sequence from the corresponding count in the second count sequence to form a difference sequence; and checking whether there are a sufficient number of positive and negative values in the sequence of difference values to indicate whether jitter is present in one of the two periodic signals.

Optionally, when the second periodic signal has a frequency that is an integer multiple of a frequency of the first periodic signal, the checking includes: generating a sequence of window boundaries identifying respective instants at which an edge of the first direction has occurred in both the first and second periodic signals, wherein a duration between two consecutive boundaries constitutes a corresponding window of the sequence of windows; subtracting the respective first count of the first count sequence from the respective count subsequence of the second count sequence in each window to generate a sequence of difference values in each window; identifying a positive minimum and a negative maximum in the sequence of difference values; accumulating the positive minimum values of a sequence of windows as a first accumulated value and the negative maximum values of the sequence of windows as a second accumulated value, when there is no jitter, selecting a smaller magnitude of the first and second accumulated values as the accumulated phase difference for the corresponding window.

Optionally, wherein the checking checks whether both the first and second accumulated values have exceeded respective thresholds to infer whether jitter is present.

Optionally, when there is jitter, further comprising: resetting one of the first and second accumulators to a boundary value, thereafter continuing the reset accumulator to accumulate one of the positive and negative minimums having a lower magnitude in each window, wherein the reset accumulator forwards the accumulation value as the accumulated phase difference.

The present application also discloses a signal processing system, the signal processing system includes: a TDC for generating an output sequence representing phase differences between respective times of receipt of a first periodic signal and a second periodic signal as input signals, wherein the TDC is operable to identify whether jitter is present in either of the first periodic signal and the second periodic signal and to perform a corrective action to mitigate the effect of jitter in the measurement of the phase differences; and a processing module for processing the output sequence.

Optionally, a phase locked loop comprising the TDC is further included and the processing module operates to minimise any phase difference between the first and second periodic signals represented by the output sequence.

Optionally, wherein the TDC comprises: counting logic to generate a first and a second count sequence for the first and the second periodic signal, respectively, the first count sequence representing respective times at which a first edge sequence having a first direction of the first periodic signal occurs on a time scale, the second count sequence representing respective times at which a second edge sequence having the first direction of the second periodic signal occurs on the time scale; and core logic to identify whether jitter is present in any of the first and second periodic signals by processing the first and second count sequences; wherein the core logic operates to generate the output sequence between the first and second periodic signals according to a first method in the absence of jitter and according to a second method in the presence of jitter.

Optionally, wherein the second periodic signal has a frequency that is an integer multiple of a frequency of the first periodic signal, wherein the core logic is further operative to: generating a sequence of window boundaries identifying respective instants at which an edge of the first direction has occurred in both the first and second periodic signals, wherein a duration between two consecutive boundaries constitutes a corresponding window of the sequence of windows; subtracting the respective first counts of the first sequence of counts from the respective subsequences of counts of the second sequence of counts in each window to generate a sequence of time differences in each window, wherein each time difference has a corresponding sign and magnitude, wherein the first method comprises calculating each output in the sequence of outputs by summing a positive time difference and a negative time difference in separate accumulators, wherein the second method comprises calculating each output in the sequence of outputs by summing both the positive time difference and the negative time difference into a single accumulator.

Optionally, wherein the TDC is operable when the integer multiple is one and when the integer multiple is greater than 1.

The time-to-digital converter disclosed herein can minimize the effect of jitter on the phase difference measurement when jitter is detected, providing a reasonably accurate phase difference.

Drawings

Exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings, which are briefly described below.

FIG. 1 is a block diagram of an exemplary device in which aspects of the present disclosure may be implemented.

Fig. 2 is a timing diagram illustrating jitter in a pair of input clocks in one embodiment.

Fig. 3A is a flow diagram illustrating a manner in which a time-to-digital converter (TDC) operates with an input clock signal having jitter according to an aspect of the present disclosure.

Fig. 3B is a block diagram of core logic implemented in one embodiment of the present disclosure.

Fig. 4A is a block diagram of an input analyzer module implemented in one embodiment of the present disclosure.

Fig. 4B is a block diagram of an output generator module implemented in one embodiment of the present disclosure.

Fig. 5 is a block diagram showing specific implementation details of a unique count generator and a window identification module for generating each phase difference value in one embodiment of the present disclosure.

Fig. 6 is a timing diagram illustrating the manner in which the signal unique-count and the signal window-identifier are generated for a pair of input clocks having the same frequency in one embodiment of the present disclosure.

Fig. 7 is a timing diagram illustrating the manner in which signals unique-count and signal window-identifier are generated for a pair of input clocks having integer relative multiples greater than one in one embodiment of the present disclosure.

Fig. 8A is a timing diagram illustrating the operation of a TDC for a pair of input clocks having the same frequency in one embodiment of the present disclosure.

Figure 8B is a timing diagram illustrating the operation of a TDC with respect to a pair of input clocks having integer-related frequencies in one embodiment of the present disclosure.

Fig. 9A is a timing diagram illustrating an operation of a TDC for detecting jitter when jitter is present in any one of input clocks in one embodiment of the present disclosure.

Figure 9B is a timing diagram illustrating the operation of a TDC in the presence of jitter in any of the input clocks in one embodiment of the present disclosure.

Fig. 10 is a timing diagram illustrating the manner in which phase difference samples are accumulated in one embodiment of the present disclosure.

Fig. 11 is a block diagram of a signal processing system in one embodiment of the present disclosure in which an apparatus implemented according to aspects of the present disclosure may be incorporated.

In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

Detailed Description

1. Overview

A time-to-digital converter (TDC) provided according to one aspect of the present disclosure identifies whether jitter is present in either of two periodic signals received as inputs. In one embodiment, jitter is detected by examining first and second count sequences, respectively, of first and second periodic signals received as input signals, wherein the first count sequence represents respective times at which a first sequence of edges having a first direction of the first periodic signal occurs on a time scale, and the second count sequence represents respective times at which a second sequence of edges having the first direction of the second periodic signal occurs on the time scale.

According to another aspect of the present disclosure, the TDC generates the phase difference according to a first method in the absence of jitter and according to a second method in the presence of jitter. In one embodiment, the first method entails calculating the phase difference by summing the positive and negative time differences in separate accumulators, while the second method calculates the phase difference by summing both the positive and negative time differences into a single accumulator. Thus, when the presence of jitter is identified, the TDC advantageously generates a phase difference without taking into account at least some of the noise introduced by the jitter.

According to another aspect of the present disclosure, the TDC can also operate when two periodic signals have the same frequency or when one of the two periodic signals has a frequency that is an integer multiple of the frequency of the other periodic signal.

In one embodiment, the core logic that processes the TDC of the first and second count sequences may include an input analyzer and an output generator. The input analyzer module generates a window boundary sequence from the first count sequence. The output generator generates a value indicative of a corresponding phase difference per clock cycle of a slower of the two periodic signals.

In one embodiment, the output generator includes: a subtraction unit for generating a time difference sequence; a positive minimum generator for selecting a positive minimum representing a minimum of the positive values contained in the time difference series; a negative maximum value generator for selecting a negative maximum value representing a maximum value among negative values included in the time difference sequence; a first accumulator for receiving a sequence of positive minima covering a corresponding window and adding values in the sequence of positive minima to generate a first accumulated value; a second accumulator for receiving a sequence of negative minimums covering a corresponding window and summing values in the sequence of negative minimums to generate a second accumulation value, and a jitter detector module for receiving the first and second accumulation values and generating a jitter present signal indicating whether jitter is present, wherein the jitter detector module determines that jitter is present if both the first and second accumulators have exceeded respective threshold values.

The TDC may further include an accumulator output module for receiving the first and second accumulated values and generating a minimum magnitude of the first and second accumulated values as an accumulated phase difference up to a corresponding window when it is determined that jitter is not present.

When jitter is determined to be present, one of the two accumulators is reset to a boundary value (e.g., 0), and thereafter, the reset accumulator accumulates one of the positive minimum value and the negative maximum value having a lower magnitude in each window, wherein the accumulator output module forwards the accumulated value in the reset accumulator to the accumulated phase difference.

Several aspects of the disclosure are described below with reference to examples for illustration. One skilled in the relevant art will recognize, however, that the disclosure may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown in detail to avoid obscuring aspects of the disclosure. Furthermore, the described features/aspects may be practiced in various combinations, but only some of which are described herein for the sake of brevity.

2. Exemplary device

Fig. 1 is a block diagram of a time-to-digital converter (TDC) implemented in accordance with aspects of the present disclosure in one embodiment. The TDC 100 is shown as including count logic 105 and core logic 110. The TDC 100 is shown as being connected to receive an input clock clk-in-1 (101-1) and input clock clk-in-2 (101-2) and a measurement clock clk-meas (103). The input clock clk-in-1 (101-1) and the input clock clk-in-2 (101-2) represent periodic inputs for which the phase difference is to be measured (determined) using the TDC 100. "phase difference" refers to the difference in phase angle between two periodic signals. The parenthesized reference signs after the signal name reference signs represent the corresponding path numbers in the figure, and the following description is also performed according to the rule.

The path 115 provided according to an aspect of the present disclosure provides a value representing the (accumulated) phase difference at the corresponding time instant.

The counting logic 105 internally includes a counter for each of the input clocks clk-in-1 (101-1) and clk-in-2 (101-2). The counting logic 105 is connected to receive the input clock clk-in-1 (101-1) and the input clock clk-in-2 (101-2). The measurement clock clk-meas (103) represents the measurement clock applied to the counter in the counting logic 105. In one embodiment, each of these counters is designed to increment by one count per cycle (e.g. at each rising edge) of the measurement clock clk-meas (103). However, in alternative embodiments, other counting conventions may be employed, such as decrementing the counter by 1 or some other fixed value for each clock cycle of the measurement clock clk-meas (103), as will be apparent to those skilled in the art. The frequency of the measurement clock clk meas (103) determines, at least partially or substantially, the resolution with which the time difference between two events, such as the rising edge of the input clock, can be generated.

The counting logic 105 is shown as generating signals count-1 (104-1) and count-2 (104-2) for input clocks clk-in-1 (101-1) and clk-in-2 (101-2), respectively. Each count sequence in signals count-1 (104-1) and count-2 (104-2) represents a respective instant at which a pre-specified direction (rising or falling) edge of the corresponding input clock occurs on the same time scale. The term "same time scale" means that each count represents a respective relative duration from a common start time. For example, the counter for each input clock starts counting (e.g., from zero) at the same time (e.g., after reset) and at the same frequency. The counting logic 105 can be implemented in a known manner. In one embodiment of the present disclosure, the counts generated by the counters in the count logic 105 are 36 bits wide and the time resolution of these counters is 62.5 picoseconds (ps).

In one embodiment, the counting logic 105 is implemented as described in U.S. application entitled "Counter Design for a Time-To-Digital Converter (TDC)" ("Counter Design for Time-To-Digital Converter (TDC)") filed on month 5 and day 10, 2022, and assigned To the assignee of the present application, the contents of which are incorporated herein by reference in their entirety.

Core logic 110 is connected to receive signal count-1 (104-1) and signal count-2 (104-2) and generate an output digital value on path 115, as briefly described above.

Several features of the present disclosure may be better understood when one understands the manner in which periodic inputs may exhibit jitter. The way in which the input clock appears jittery will therefore be briefly described next with reference to fig. 2.

3. Periodic input with dithering

FIG. 2 is a timing diagram illustrating the manner in which one of a pair of periodic inputs having the same frequency and the same phase in steady state has jitter in one embodiment. In fig. 2, the waveform of the jitter is not drawn to scale and is provided only to illustrate the jitter. In FIG. 2, the two waveforms on path 101-1 and path 102-1 represent the waveforms of input clock clk-in-1 (101-1) and input clock clk-in-2 (101-2), respectively, for which the phase difference is to be measured.

Rising edges of the input clock clk-in-1 (101-1) are shown to occur at times t11, t12, t14, and t18, while rising edges of the input clock clk-in-2 (101-2) are shown to occur at times t10, t13, t15, and t16. In steady state, in the absence of jitter in the input clock, each rising edge of the input clock clk-in-2 (101-2) will coincide with a corresponding rising edge of the input clock clk-in-1 (101-1), i.e., rising edges of the input clock clk-in-2 (101-2) will also occur at times t11, t12, t14, and t18.

However, as shown in FIG. 2, the rising edge of the input clock clk-in-2 (101-2) is shown to occur either slightly earlier than the corresponding rising edge of the input clock clk-in-1 (101-1), such as at times t10 and t16 within some cycles, or slightly later than the corresponding rising edge of the input clock clk-in-1 (101-2), such as at times t13 and t15 within some cycles.

Thus, the input clock clk-in-2 (101-2) is said to have "jitter". In general, jitter exhibits a random characteristic, and thus exhibits a negative time difference and a positive time difference when superimposed on an otherwise ideal clock signal. Aspects of the present disclosure utilize this observation to identify jitter.

Further aspects of the present disclosure seek to reduce the undesirable effects on the measured phase difference by ignoring time differences of positive or negative sign in the calculation of the phase difference when the presence of jitter is identified.

For ease of understanding, the timing diagram of FIG. 2 depicts a simplified illustration of dithering. In practice, however, the jitter will be more random and there may be several cycles with jitter within the input clock. Further, as will be apparent to those skilled in the art, the jitter may be of several types, such as random jitter, deterministic jitter, and the like. Aspects of the present disclosure are also applicable to this type of dithering.

Although the timing diagram of fig. 2 shows jitter in a pair of periodic inputs (input clocks) having the same frequency, aspects of the present disclosure are also applicable to a pair of input clocks having frequencies that are integer multiples of greater than 1.

A TDC 100 implemented according to aspects of the present disclosure, in addition to providing a phase difference in the presence and absence of jitter, also detects the presence of jitter in one of these input clocks, as described in the examples below.

4. Flow chart

Fig. 3A is a flow chart illustrating a manner in which a TDC according to an aspect of the present disclosure operates with an input clock signal having jitter. The flow diagram is described with respect to core logic 110 of fig. 1 for illustration only. However, many of the features can be implemented in other systems and/or other environments without departing from the scope and spirit of several aspects of the present disclosure, as will be apparent to those skilled in the relevant arts by reading the disclosure provided herein.

Additionally, some steps may be performed in a different order than depicted below to suit a particular environment, as will be apparent to one of ordinary skill in the relevant art. Many such implementations are contemplated as being covered by several aspects of the present disclosure. The flowchart begins in step 301, where control immediately passes to step 303.

In step 303, core logic 110 receives first and second count sequences of first and second periodic signals, respectively. In step 304, core logic 110 generates a time difference between edges (of the same direction) of the two periodic signals, where each time difference is represented by a sign and a magnitude.

In step 306, the core logic 110 checks whether there is jitter in one of these two periodic signals. If there is no jitter, control passes to step 307, and if there is jitter, control passes to step 311. Step 307 and step 311 calculate the phase difference according to different methods, in particular to counteract the effect of jitter on the accurate phase difference measurement.

Any suitable method may be selected to minimize the effect of jitter on the phase difference measurement when jitter is detected. In the embodiments described below, the first method entails calculating the phase difference by summing the positive and negative time differences in separate accumulators, while the second method calculates the phase difference by summing both the positive and negative time differences into a single accumulator.

Control then passes to step 315 where the calculated phase difference is provided to any external component that needs such information. The flowchart ends at step 320.

Thus, the TDC of the present disclosure provides a fairly accurate phase difference even when there is jitter in one of these clock signals. The details of the specific implementation of the core logic contained in such a TDC in one embodiment of the present disclosure are briefly provided below.

5. Core logic

Fig. 3B is a block diagram illustrating details of a specific implementation of core logic 110 in one embodiment of the present disclosure. The core logic 110 is shown as including an input analyzer module 350 and an output generator module 390.

The input analyzer module 350 is shown receiving the input signal count-1 on path 104-1, the signal count-2 on path 104-2, the signal clk-dig-tdc on path 307, and the signal jitter-indicator on path 395. The input analyzer module 350 generates a signal window-identifier on path 332, a signal count1-sub on path 342-1, and a signal count2-sub on path 342-2. The input analyzer module 350 receives the signal count-1 (104-1) and the signal count-2 (104-2) at each rising edge of the corresponding input clock clk-in-1 (101-1) and input clock clk-in-2 (101-2). Input analyzer module 350 may store signal count-1 (104-1) and signal count-2 (104-2) values and, in addition, perform operations such as processing the inverse of the counters that generated signal count-1 (104-1) and signal count-2 (104-2). In the absence of such additional operations, signals count1-sub (342-1) and count2-sub (342-2) are functionally equivalent to signals count-1 (104-1) and count-2 (104-2), respectively.

The input analyzer module 350, among other operations, operates to determine boundaries (respective times) of the window, which correspond to (or are defined by) a pair of consecutive edges of either of the two input clocks clk-in-1 (101-1) and clk-in-2 (101-2) when the two clocks have the same frequency, and which correspond to a pair of consecutive edges of the slower clock when the clocks have an integer multiple frequency greater than 1. As will be described in detail below, the input analyzer 350 uses a signal window-identifier (332) to indicate the boundaries (left and right edges) of the window.

Although the description continues with respect to the rising edge of the input clock, aspects of the present disclosure are equally applicable to the falling edge of the input clock, as will be apparent to those skilled in the art upon reading the disclosure herein.

Output generator module 390 is shown receiving signal window-identifier on path 332, signal count1-sub on path 342-1, signal count2-sub on path 342-2, signal clk-dig-tdc on path 307, and signal jitter-indicator on path 395. In one embodiment, output generator module 390 generates one value in a sequence of values in each window in a sequence of windows on path 115, where the value indicates the corresponding calculated phase difference for that window. Additional outputs may be provided on the corresponding paths based on the operating mode of the TDC 100 as will be described in detail below.

Although the TDC 100 described above is shown as operating on only one pair of periodic inputs, the TDC 100 may be implemented to operate on more than one pair of periodic inputs simultaneously with appropriate modifications to the TDC 100. Operation with more than one pair of periodically inputted TDCs is described in detail in U.S. application entitled "Time-to-digital Converter (TDC) Measuring Phase Difference Between multiple clocks" filed on 10/5/2022 and assigned to the assignee of the present application, the contents of which are incorporated herein by reference in their entirety.

Details of the operations performed by the input analyzer module 350 and the output generator module 390 of the core logic 110 in determining a phase difference between a pair of input clocks are described in detail next.

6. Input analyzer module

Fig. 4A is a block diagram illustrating specific implementation details of an input analyzer module in one embodiment of the disclosure. The input analyzer module 350 is shown as including a first count (count 1-q) generator 405-1, a second count (count 2-q) generator 405-2, a first unique generator 410-1, a second unique generator 410-2, a first toggle generator 415-1, a second toggle generator 415-2, a window identification module 420, and a toggle module 425. The specific modules and interconnections of fig. 4A are shown as examples only. More or fewer modules may be used in other embodiments of the disclosure. In an embodiment of the present disclosure, the modules 405-1, 405-2, 410-1, 410-2, 415-1, and 415-2 are implemented using sequential logic, while the window identification module 420 and the flip module 425 are implemented using combinational logic. However, these modules may be implemented in different ways, as will be apparent to those skilled in the art upon reading the disclosure herein. The sequential modules of the input analyzer module 350 are clocked by the signal clk-dig-tdc (307).

As described above, the frequency of the signal clk-dig-tdc (307) is greater than the frequency of the input clocks clk-in-1 (101-1) and clk-in-2 (101-2), and the values of the signals count-1 (104-1) and count-2 (104-2) are received at each rising edge of the respective clocks. Thus, the values of the signals count-1 (104-1) and count-2 (104-2) may remain unchanged for two or more cycles of the signal clk-dig-tdc (307). Accordingly, changes in the respective values of the signals count-1 (104-1) and count-2 (104-2) may be examined to determine the phase difference between the input clocks clk-in-1 (101-1) and clk-in-2 (101-2). The first count generator 405-1, the second count generator 405-2, the first unique generator 410-1, the second unique generator 410-2, and the window identification module 420 operate to provide this functionality.

The first count generator 405-1 receives the signal count-1 on path 104-1 and generates the signal count1-q on path 406-1. In one embodiment, the first count generator 405-1 is implemented as a positive edge triggered flip-flop. The first count generator 405-1 is clocked by the signal clk-dig-tdc (307). Signal count1-q (406-1) represents a time-delayed version of signal count-1 (104-1). Thus, signal count-1 (104-1) is delayed by one clock cycle of signal clk-dig-tdc (307) before being output onto path 406-1.

Second count generator 405-2 receives signal count-2 on path 104-2 and generates signal count2-q on path 406-2. In one embodiment, the second count generator 405-2 is implemented as a positive edge triggered flip-flop. The second count generator 405-2 is clocked by the signal clk-dig-tdc (307). Signal count2-q (406-2) represents a time-delayed version of signal count-2 (104-2). Thus, signal count-2 (104-2) is delayed by one clock cycle of signal clk-dig-tdc (307) before being output onto path 406-2.

First unique generator 410-1 receives signal count-1 (104-1), signal count1-q (406-1), and signal window-identifier (332), and generates signal unique-count1-q on path 411-1. As can be observed from FIG. 4A, the operation of the first unique generator 410-1 and the window identification module 420 (described below) depend on the output of each other. Typically, the output of the first unique generator 410-1 is a binary signal that indicates whether a new count is available at the boundary of the window identified by the window identification module 420. In one embodiment of the present disclosure, the first unique generator 410-1 is implemented as a sequential module, clocked by the signal clk-dig-tdc (307), and implements the following logic:

first unique generator 410-1 generates a logic low level on path 411-1 when signal count-1 (104-1) equals signal count1-q (406-1) and signal window-identifier (332) is a logic high level, and generates a logic high level when signal count-1 (104-1) does not equal signal count1-q (406-1). In other words, the first unique generator 410-1 operates to determine that the count value of the signal count-1 (104-1) has undergone a change from its value in the previous clock cycle of the signal clk-dig-tdc (307) (indicating the occurrence of the rising edge of the input clock clk-in-1 (101-1)), and additionally takes into account the value of the signal window-identifier (332).

Second unique generator 410-2 receives signal count-2 (104-2), signal count2-q (406-2), and signal window-identifier (332), and generates signal unique-count2-q on path 411-2. As can be observed from FIG. 4A, the operation of the second unique generator 410-2 and the window identification module 420 (described below) are dependent on the output of each other. Generally, output by the second unique generator 410-2 is a binary signal that indicates whether a new count is available at the boundary of the window identified by the window identification module 420. In one embodiment of the present disclosure, the second unique generator 410-2 is implemented as a sequential module, clocked by the signal clk-dig-tdc (307), and implements the following logic:

second unique generator 410-2 generates a logic low level on path 411-2 when signal count-2 (104-2) equals signal count2-q (406-2) and signal window-identifier (332) is a logic high level, and generates a logic high level when signal count-2 (104-2) does not equal signal count2-q (406-2). In other words, the second unique generator 410-2 operates to determine that the count value of the signal count-2 (104-2) has undergone a change from its value in the previous clock cycle of the signal clk-dig-tdc (307) (indicating the occurrence of the rising edge of the input clock clk-in-2 (101-2)), and additionally takes into account the value of the signal window-identifier (332).

The core logic 110 receives a continuous stream of counts representing corresponding edges of the input clocks clk-in-1 (101-1) and clk-in-2 (101-2). The core logic 110 generates each output in the output sequence (as described above) from a (same direction, rising/falling) pair of consecutive edges of one input clock (e.g., input clock clk-in-1 (101-1)) and a single edge of the other input clock (e.g., input clock clk-in-2 (101-2)). Thus, core logic 110 needs to identify a corresponding pair of consecutive edges for generating each output. The window identification module 420 implemented in the input analyzer module 350 performs such operations.

The window identification module 420 operates to identify the window boundaries described above. That is, the window identification module 420 operates to identify the occurrence of a pair of consecutive edges in the same direction (rising or falling) of the slower input clock when the frequencies of the two input clocks are integer multiples of greater than 1, or in the same direction (rising or falling) of either of the two input clocks when the frequencies of the two input clocks are equal. The duration between these moments is referred to herein as a window. Each window may have a respective stream of differences that need to be examined in order to generate an output (representing the phase difference between the input clocks clk-in-1 (101-1) and clk-in-2 (101-2)) after the end of each window.

Window identification module 420 receives signal unique-count1-q (411-1) and signal unique-count2-q (411-2) and generates a signal window-identifier on path 332. Window identification module 420 generates a logic high level on path 332 when both signal unique-count1-q (411-1) and signal unique-count2-q (411-2) are logic high, otherwise generates a logic low level. As will be apparent from the description below, a pair of consecutive logic high levels represents a window boundary as described above.

First rollover generator 415-1 receives signal count-1 (104-1), signal count1-q (406-1), signal window-identifier (332), and generates signal rolover-1 on path 416-1. In an embodiment of the present disclosure, the first toggle generator 415-1 is implemented as a sequential module, clocked by the signal clk-dig-tdc (307). When the count value of signal count-1 (104-1) has exceeded the full scale value (toggle) of the counter, first toggle generator 415-1 generates a logic high level on path 416-1. As is well known in the relevant art, when the value of the counter reaches its full scale value, it is said that a roll-over has occurred and the counter starts counting from zero. For example, for a 10-bit counter, when the value of the count reaches 1024, it is said that a roll-over occurs.

Second toggle generator 415-2 receives signal count-2 (104-2), signal count2-q (406-2), signal window-identifier (332), and generates signal rolover-2 on path 416-2. In an embodiment of the present disclosure, the second toggle generator 415-2 is implemented as a sequential module, clocked by the signal clk-dig-tdc (307). When the count value of signal count-2 (104-2) has exceeded the full scale value (rollover) of the counter, second rollover generator 415-2 generates a logic high level on path 416-2.

The flipping module 425 receives the signal count-1 (104-1), the signal count-2 (104-2), the signal rolover-1 (416-1), and the signal rolover-2 (416-2), and generates the signal count1-sub (342-1) and the signal count2-sub (342-2). In an embodiment of the present disclosure, the flipping module 425 is implemented as a combination module. The toggle module 425 operates to ensure that in the event that any input count toggles, the corresponding correct value of the input count is forwarded to the output generator module 390.

In one embodiment, the flipping process is implemented as described in detail in U.S. application entitled "Time-to-digital Converter (TDC) Measuring Phase Difference Between Periodic Inputs" ("Time-to-digital Converter (TDC)" for Measuring Phase Difference Between Periodic Inputs ") filed on 10/5/2022, and assigned to the assignee of the present application, the contents of which are incorporated herein by reference in their entirety.

Specific implementation details of the output generator module 390 in one embodiment of the present disclosure are provided next.

7. Output generator module

Fig. 4B is a block diagram illustrating specific implementation details of an output generator module in one embodiment of the present disclosure. The output generator module 390 is shown to include a subtraction unit 430, a positive minimum generator 435, a negative maximum generator 445, a window counter 444, a positive Accumulator 440, a negative Accumulator 450, a jitter detector 460, a Running-Accumulator-data generator 465, and an Accumulator-valid-data generator 475.

The specific modules and interconnections of fig. 4B are shown as examples only. More or fewer modules may be used in other embodiments of the disclosure. In one embodiment of the disclosure, modules 435, 445, 444, 440, 450, and 475 are shown as sequential, while modules 430 and 465 are shown as combined. The other output signals, namely, the signal running-acc-data (491), the signal running-simple (492), and the signal data-valid (493), are generated by a running-accumulator-data generator (465) and an accumulator-valid-data generator (475), which are additionally implemented in core logic 110 to enable operation in modes (1) and (2), as described below.

In one embodiment, the TDC 100 is designed to operate in the following modes:

mode (1): accumulator mode, where the input clock clk-in-1 (101-1) and the input clock clk-in-2 (101-2) have the same frequency.

Mode (2): accumulator mode, in which the frequencies of the input clock clk-in-1 (101-1) and the input clock clk-in-2 (101-2) are integer related.

Mode (3): continuous single shot mode.

Mode (4): disposable single shot mode.

In modes (1) and (2), the TDC 100 receives a predetermined value (from a user via corresponding means not shown) indicating the number of phase difference samples to be accumulated. In both modes, the TDC 100 generates outputs on path 115 (signal output), path 493 (signal data-value), path 491 (signal running-acc-data), and path 492 (signal running-nsample). At the end of sampling each predetermined number of samples (hereinafter referred to as an accumulation period), the TDC 100 asserts the signal data-valid (493) and provides an accumulated phase difference value on path 115 (signal output). At the end of accumulating each phase difference sample, the TDC 100 provides the phase difference value accumulated thus far on path 491 (signal running-acc-data). The signal running-nsample (492) indicates the number of samples accumulated in the signal running-acc-data (491). The average of the accumulated values (total accumulated value divided by the number of accumulated samples) may be determined by components external to the TDC 100.

In mode (3), the TDC 100 generates a phase difference between the pair of periodic inputs (as in mode (1) and mode (2) without accumulation of phase difference samples), and provides a sequence of phase differences on an additional path (not shown).

In mode (4), the TDC 100 operates on a pulsed input, generates a one-time phase difference between pulses, and provides a phase difference on an additional path (not shown).

Output generator module 390 receives signal window-identifier (332), signal count1-sub (342-1), and signal count2-sub (342-2). In one embodiment, signal window-identifier (332), signal count1-sub (342-1), and signal count2-sub (342-2) are buffered in pipeline stages (not shown) at one sample depth to enable core logic 110 to meet circuit timing requirements. In one embodiment, the pipeline delay stage is implemented using registers, and the signal is delayed/buffered by one clock cycle of signal clk-dig-tdc (307).

The output generator module 390 generates a signal jitter-indicator on path 395. The signal jitter-indicator (395) is used to indicate jitter in any of the input clocks, as will be described in detail below. Although path 395 is shown as a single path, signal jitter-present (392) and signal use jitter-propach (393) are provided on path 395.

The subtraction unit 430 receives the signal count1-sub on path 342-1 and the signal count2-sub on path 342-2. Subtracting unit 430 generates a signal running-count-diff on path 433. In an embodiment of the present disclosure, subtraction unit 430 is implemented as a signed subtraction module. Thus, the subtraction unit 430 generates a signed difference between the signal count1-sub (342-1) and the signal count2-sub (342-2). The signal running-count-diff (433) represents the stream of time differences between edges or edge pairs of the input clock clk-in-1 (101-1) and the input clock clk-in-2 (101-2) within the window.

Positive minimum generator 435 operates to determine a positive minimum among/between a set of difference values (signal running-count-diff (433)) generated by subtraction unit 430 in each window identified by window identification module 420 (i.e., between a pair of consecutive positive (rising) edges of the slower of the two input clocks). The positive minimum generator 435 receives the signal running-count-diff on path 433, the signal window-identifier on path 332, and generates the signal pos-min on path 436. In one embodiment of the present disclosure, positive minimum generator 435 is implemented as a sequential module, clocked by signal clk-dig-tdc (307), and operates according to the following logic:

if the signal window-identifier (332) is a logic high level and the signal running-count-diff (433) is zero or positive, then the signal pos-min (436) is recorded as the signal running-count-diff (433). Otherwise, if the signal window-identifier (332) is a logic high level and the signal running-count-diff (433) is non-zero and negative, then the signal pos-min (436) is recorded as a full scale positive value. In other words, if signal count-1 (104-1) and signal count-2 (104-2) each consist of P bits, then the full scale positive value is + (2P-1), hereinafter referred to as "max1". Otherwise, if the signal running-count-diff (433) is a positive value and less than the signal pos-min (436), the signal pos-min (436) is updated to the signal running-count-diff (433). Thus, the positive minimum generator 435 operates to determine a positive minimum of the running-count-diff signal (433) between two consecutive pulses of the window-identifier (332).

The negative maximum generator 445 operates to determine the largest negative value among/between a set of differences (signal running-count-diff (433)) generated by the subtraction unit 430 in each window identified by the window identification module 420 (i.e., between a pair of consecutive positive (rising) edges of the slower of the two input clocks). The negative maximum generator 445 receives the signal running-count-diff on path 433, the signal window-identifier on path 332, and the signal neg-max on path 446. In one embodiment of the present disclosure, the negative maximum generator 445 is implemented as a sequential module, clocked by the signal clk-dig-tdc (307), and operates according to the following logic:

if the signal window-identifier (332) is a logic high level and the signal running-count-diff (433) is zero or negative, then the signal neg-max (446) is recorded as the signal running-count-diff (433). Otherwise, if the signal window-identifier (332) is a logic high level and the signal running-count-diff (433) is non-zero and positive, then the signal neg-max (446) is recorded as a full scale negative value. In other words, if signal count-1 (104-1) and signal count-2 (104-2) each consist of P bits, the full scale negative value is- (2P-1), hereinafter referred to as "max2". Otherwise, if the signal running-count-diff (433) is negative and greater than the signal neg-max (446), the signal neg-max (446) is updated to the signal running-count-diff (433). Thus, the negative maximum generator 445 operates to determine the maximum negative value of the running-count-diff signal (433) between two pulses of the window-identifier (332).

Window counter 444 receives signal pos-min (436), signal neg-max (446), and signal jitter-indicator (395), and generates signal sample-done on path 447. In one embodiment, window counter 444 increments the value of the counter at the end of each window and asserts signal nsample-done (447) when the counter value equals a predetermined number of phase difference samples provided as user input. When the received value of signal jitter-present (392) is a logic high level, window counter 444 asserts signal nsample-done on path 447 (ending the current accumulation period) and resets the counter's value to zero (indicating the start of a new accumulation period).

Positive accumulator 440 receives signal pos-min on path 436, signal neg-max on path 446, signal window-identifier on path 332, signal nsample-done on path 447, signal jitter-indicator on path 395, and signal acc-pos-q on path 442. In one embodiment, as will be described in detail below, the value of "max1" above is the threshold of positive accumulator 440, which forms the basis for indicating the presence of jitter.

In one implementation, when the value received on path 392 (signal jitter-present) is a logic high level (indicating that there is jitter in any of the input clocks), positive accumulator 440 resets the accumulated value, i.e., signal acc-pos-q (442), to a boundary value (e.g., zero).

In one embodiment, positive accumulator 440 accumulates (adds) the received signal pos-min (436) when the value received on path 393 (signal use-jitter-proproach) is a logic low level (indicating that there is no jitter in the input clock). In other words, positive accumulator 440 ignores received signal neg-max (446) when signal use-jitter-proproach (393) is a logic low level.

When the value received on path 393 (the signal use-jitter-proproach) is a logic high level (indicating that there is jitter in the input clock), positive accumulator 440 operates using the following method:

positive accumulator 440 calculates the lower magnitudes (absolute minimum) of signal pos-min (436) and signal neg-max (446) received in each window and accumulates (adds) the calculated values (with corresponding signs) to the current value of positive accumulator 440. For example, in the window, if the value of signal pos-min (436) is received as "+1" and the value of signal neg-max (446) is received as "-2", positive accumulator 440 adds "+1" to the current value in positive accumulator 440. As another example, in the window, if the value of signal pos-min (436) is received as "+3" and the value of signal neg-max (446) is received as "-2", then positive accumulator 440 calculates the lower magnitude as "-2" and adds "-2" (with a sign) to the current value in positive accumulator 440.

Negative accumulator 450 receives signal neg-max on path 446, window-identifier on path 332, signal ample-done on path 447, signal jitter-indicator on path 395, and signal acc-neg-q on path 452. In one embodiment, as will be described in detail below, the value of "max2" above is the threshold of the negative accumulator 450, which forms the basis for indicating the presence of jitter.

In one implementation, the positive accumulator 440 resets the accumulation value signal acc-pos-q (442) to a boundary value (e.g., zero) when the value received on path 392 (signal jitter-present) is a logic high level (indicating jitter is present in any of the input clocks).

In one embodiment, negative accumulator 450 accumulates (adds) received signal neg-max (446) when the value received on path 393 (signal use-jitter-propach) is a logic low level (indicating that there is no jitter in the input clock). When the value received on path 393 (the signal use-jitter-approach) is a logic high level (indicating that there is jitter in any of the input clocks), negative accumulator 450 does not accumulate any values.

The running accumulator data generator 465 and accumulator valid data generator 475 examine the signal acc-pos-q (442) and the signal acc-neg-q (452) to determine the outputs (signal running-acc-data (491) and signal output (115)) in patterns (1) and (2) above. Together, the modules 440, 450, 465, and 475 include accumulation logic operable to generate corresponding outputs in an accumulation mode of operation of the TDC 100.

Run accumulator data generator 465 receives signal acc-pos-q (442), signal acc-neg-q (452), signal jitter-indicator (395) and generates signal running-acc-data on path 491 and signal running-nsample on path 492.

In one embodiment, when the value received on path 393 (signal use-jitter-proproach) is a logic low level (indicating no jitter is present in the input clock), accumulator data generator 465 is run to determine the lower magnitude (absolute minimum) of signal acc-pos-q (442) and signal acc-neg-q (452) and provide the lower magnitude on path 491. When the value received on path 393 (signal use-jitter-proproach) is a logic high level (indicating that there is jitter in the input clock), accumulator data generator 465 is run to forward the value received on path 442 (signal acc-pos-q) and ignore signal acc-neg-q (452). The signal running-nsample (492) indicates the number of samples accumulated in the signal running-acc-data (491).

Accumulator valid data generator 475 receives signals acc-pos-q (442), acc-neg-q (452), signal nsample-done (447), and signal jitter-indicator (395) and generates signal data-valid on path 493 and signal output on path 115. At the end of accumulating every predetermined number of samples (indicated by signal nsample-done (447)), accumulator valid data generator 475 asserts signal data-valid (493) and provides an accumulated phase difference on path 115.

In one embodiment, the accumulator valid data generator 475 resets the current accumulated value to a boundary value (e.g., zero) when the value received on path 392 (signal jitter-present) is a logic high level. When the value received on path 393 (signal use-jitter-proproach) is a logic low level (indicating no jitter in the input clock), the accumulator valid data generator 475 determines the lower magnitude (absolute minimum) of the signal acc-pos-q (442) and signal acc-neg-q (452) received at the end of the accumulation period and provides the same value on path 115 until the end of the next accumulation period. When the value received on path 393 (signal use-jitter-proproach) is a logic high level (indicating that there is jitter in the input clock), accumulator valid data generator 475 forwards the value received on path 442 (signal acc-pos-q) at the end of the accumulation period and provides that value as the accumulated phase difference on path 115 until the end of the next accumulation period. In other words, when the value received on path 393 (signal use-jitter-approach) is a logic high level (indicating the presence of jitter in the input clock), accumulator valid data generator 475 ignores signal acc-neg-q (452).

Jitter detector 460 receives signal acc-pos-q (442) and signal acc-neg-q (452) and generates a signal jitter-indicator on path 395. As described above, the signal jitter-indicator (395) is used to indicate that there is jitter in any of the input clocks.

As described above, jitter detector 460 generates signal jitter-present (392) and signal use jitter-approach (393) on path 395. In one implementation, a logic low level on path 392 (signal jitter-present) indicates that there is no jitter in the input clocks, while a logic high level on path 392 (signal jitter-present) indicates that there is jitter in any of the input clocks. The signal jitter-present (392) is set to a logic low level by default. The jitter detector 460 checks whether the values of both the signal acc-pos-q (442) and the signal acc-neg-q (452) have exceeded the respective threshold values ("max 1" and "max2", respectively). If so, the jitter detector 460 generates a logic high level on path 392 indicating that there is jitter in either of the input clocks clk-in-1 (101-1) and clk-in-2 (101-2). In an exemplary embodiment, the jitter-present (392) signal is deasserted after one clock cycle of the signal clk-dig-tdc (307). Thus, the pulse width of the signal jitter-present (392) is equal to one clock cycle of the signal clk-dig-tdc (307).

In one embodiment, the signal use-jitter-approach (393) defaults to a logic low level. When it is determined that jitter is present, jitter detector 460 generates a logic high level on path 393. The jitter detector 460 maintains the signal use-jitter-approach (393) in an asserted state (logic high) for a duration equal to a predetermined number of windows provided by the user for accumulation of phase difference samples. Jitter detector 460 determines the end of a predetermined number of windows based on signal nsample-done received on path 447 (not shown).

While in the illustrative embodiment, detection of jitter is shown as being performed by jitter detector 460 implemented external to module running accumulator data generator 465 and accumulator valid data generator 475, in alternative embodiments, jitter detector 460 may be implemented as part of either module running accumulator data generator 465 or accumulator valid data generator 475.

Specific implementation details of the first unique generator and the second unique generator in one embodiment of the present disclosure are provided next.

8. Unique count generator

FIG. 5 is a block diagram showing specific implementation details of a unique count generator in one embodiment of the present disclosure. FIG. 5 is shown to contain a flip-flop 502-1, a first count generator 405-1, a first unique generator 410-1, a flip-flop 502-2, a second count generator 405-2, a second unique generator 410-2, and a window identification module 420. The first unique generator 410-1 is again shown to contain a logic block 505-1, multiplexers (MUXs) 507-1, 509-1, 511-1, 513-1, flip-flops 515-1, inverters 520-1, and AND gates 518-1. The second unique generator 410-2 is again shown to contain a logic block 505-2, multiplexers 507-2, 509-2, 511-2, 513-2, flip-flop 515-2, inverter 520-2, and AND gate 518-2. The specific modules and interconnections in fig. 5 are shown as examples only. More or fewer modules may be used in other embodiments of the disclosure.

Logic module 505-1 receives signal count-1 (104-1) and signal count1-q (406-1), and generates signal unique-count1 (501-1). In one embodiment, logic block 505-1 generates a logic high level on path 501-1 if signal count-1 (104-1) and signal count1-q (406-1) are not equal, and generates a logic low level otherwise. Thus, logic module 505-1 implements the logic: unique-count1= (count-1 | = count 1-q).

MUX 507-1 receives a logic high level and signal unique-count1-q (411-1) on path 503-1 and forwards one of the logic high level and signal unique-count1-q (411-1) as an output (MUX select output) on path 508-1 based on the logic value of the select signal (signal unique-count1 (501-1)). Thus, when signal unique-count1 (501-1) is logic high, MUX 507-1 forwards the logic high (503-1) on path 508-1. When signal unique-count1 (501-1) is logic low, MUX 507-1 forwards signal unique-count1-q on path 508-1 (411-1).

MUX 509-1 receives a logic low level on path 504-1, an output of MUX 507-1 on path 508-1, and one of the logic low level (signal on signal 504-1) and the MUX output (signal on path 508-1) is forwarded as an output (MUX select output) on path 510-1 based on the logic value of the select signal (signal on path 519-1). Thus, when the value on path 519-1 is a logic high, MUX 509-1 forwards a logic low (signal on path 504-1) on path 510-1. When the value on path 519-1 is a logic low, MUX 509-1 forwards the value on path 508-1 on path 510-1.

MUX 511-1 receives a logic low level on path 506-1, receives the output of MUX 509-1 on path 510-1, and forwards one of the logic low level and the signal on path 510-1 of the MUX output on path 512-1 as an output (the MUX select output) based on the logic value of the select signal (i.e., signal jitter-present (392)).

The signal jitter-present (392) is received from the output generator module 390 (as described above with respect to FIG. 4B) and indicates whether jitter is present in any of the input clocks (clk-in-1 (101-1) and clk-in-2 (101-2)). Thus, when the signal jitter-present (392) is a logic high level (indicating that jitter is present), MUX 511-1 forwards the logic low level on path 512-1 (signal on path 506-1). When signal jitter-present (392) is a logic low, MUX 511-1 forwards the value on path 510-1 on path 512-1. Therefore, when the signal jitter-present (392) is at a logic high level, the signal unique-count-1-q (411-1) is set to a logic low level (reset).

MUX 513-1 receives a logic low level on path 516-1, receives the output of MUX 511-1 on path 512-1, and forwards one of the logic low level and the MUX output (the signal on path 512-1) as an output (the MUX select output) on path 514-1 based on the logic value of select signal rstn-i (519). The signal rstn-i (519) represents a chip reset or power-on reset. Thus, when signal rstn-i (519) is a logic high, MUX 513-1 forwards a logic low (516-1) on path 514-1. When signal rstn-i (519) is a logic low, MUX 513-1 forwards the value on path 512-1 on path 514-1.

The flip-flop 515-1 is clocked by the signal clk-dig-tdc (307). Flip-flop 515-1 receives the input signal on path 514-1 at its D input and generates an output (Q), signal unique-count1-Q on path 411-1. In one embodiment, flip-flop 515-1 is implemented as a positive edge triggered flip-flop.

And gate 518-1 receives the output of inverter 520-1 on path 521-1, the signal window-identifier on path 332, and the result of the and operation on path 519-1.

Window identification module 420 receives signal unique-count1-q (411-1) and signal unique-count2-q (411-2) and generates a signal window-identifier on path 332. In one embodiment of the present disclosure, the window identification module 420 is implemented as an and gate. Thus, window identification module 420 implements the logic to: window-identifier = (unique-count 1-q & & unique-count 2-q). In the exemplary implementation, the signal window-identifier (332) is deasserted after one clock cycle of the signal clk-dig-tdc (307). Thus, the pulse width of the signal window-identifier (332) is equal to one clock cycle of the signal clk-dig-tdc (307), and the frequency of the signal window-identifier (332) is equal to the slower of the two selected input clock frequencies (clk-in-1 (101-1) and clk-in-2 (101-2)), where the frequencies of the two clocks are integer related.

The components 505-1, 507-1, 509-1, 511-1, and 513-1 together implement the following logic:

if (window-identifier && !unique-count1)

unique-count1-q = 0

else if (unique-count1)

unique-count1-q = 1

the above expression (window-identifier & & | _ unique-count 1) contains the operators & & and |, which respectively represent the and not operators. Therefore, when the value of the signal window-identifier is logic high and the value of the signal unique-count1 is logic low, the expression (window-identifier & &! unique-count 1) will be evaluated as 1, and otherwise as 0.

The components 505-2, 520-2, 518-2, 507-2, 509-2, 511-2, 513-2, and 515-2 operate in a similar manner to the components 505-1, 520-1, 518-1, 507-1, 509-1, 511-1, 513-1, and 515-1, respectively, and the description is not repeated here for the sake of brevity.

The manner in which the unique count generator and window identification module operate to determine the window is next illustrated with exemplary waveforms.

9. Generating a signal unique-count and a signal window-identifier for a pair of input clocks having the same frequency

Fig. 6 is a timing diagram (not drawn to scale) illustrating the manner in which the signal unique-count (501, 411) and the signal window-identifier (332) are generated for a pair of input clocks having the same frequency (and phase difference) in one embodiment of the present disclosure. FIG. 6 shows exemplary waveforms of the signal clk-dig-tdc (307), the input clock clk-in-1 (101-1), the signal count-1 (104-1), the signal count1-q (406-1), the signal unique-count1 (501-1), the signal unique-count1-q (411-1), the input clock clk-in-2 (101-2), the signal count-2 (104-2), the signal count2-q (406-2), the signal unique-count2 (501-2), the signal unique-count2-q (411-2), and the signal window-identifier (332). In this exemplary implementation, the counts corresponding to the input clocks (clk-in-1 (101-1) and clk-in-2 (101-2)) are assumed to be 36 bits wide. The particular count values and phase differences between the input clocks clk-in-1 and clk-in-2 shown in FIG. 6 are not drawn to scale, but are merely used to illustrate the manner in which the unique count values and signals window-identifier are generated. For purposes of this specification, the "X" value in the data waveform (signal count-1 (104-1), signal count1-q (406-1), signal count-2 (104-2), count2-q (406-2), signal running-count-diff (433), signal pos-min (436), signal neg-max (446), signal acc-pos-q (442), signal acc-neg-q (452)) indicates an "don't care" value.

The value "289" (signal count-1 (104-1)) received at t610 corresponds to a digital representation of the occurrence time of the rising edge (RE 11) of the input clock clk-in-1 (101-1), and the value "310" (signal count-2 (104-2)) received at t612 corresponds to a digital representation of the occurrence time of the rising edge (RE 21) of the input clock clk-in-2 (101-2). Counters (in counting logic 105, not shown) sampled by respective input clocks clk-in-1 and clk-in-2 provide respective count value signals count-1 (104-1) and count-2 (104-2) on respective rising edges of input clocks clk-in-1 and clk-in-2. As described above, the counters corresponding to each pair of input clocks are synchronized, i.e., count from the same initial value (e.g., zero) and increment at the same rate. Thus, the counters represent time instants on the same time scale.

The counts corresponding to the rising edges of the input clock clk-in-1 (101-1) are shown as being received at times t610, t618, and t 626. Thus, signal count-1 (104-1) is shown as having a value 289 between t610-t618, a value 373 between t618-t626, and a value 457 between t626-t 632. Signal count1-q (406-1) is the value of signal count-1 (104-1), but is delayed by one clock cycle of signal clk-dig-tdc (307) by a flip-flop, first count generator 405-1. Thus, when signal count-1 (104-1) has a value 289 beginning at t610, signal count1-q (406-1) is shown to have a value 289 beginning at t612 (after one cycle of signal clk-dig-tdc (307)). Thus, the signals count1-q (406-1) are shown to have values 289 between t612-t620, 373 between t620-t628, and 457 between t628-t 632.

When the value of signal count-1 (104-1) is not equal to the value of signal count1-q (406-1), signal unique-count1 (501-1) is asserted. In other words, the signal unique-count1 (501-1) is set to a logic high level when the count of the input clock clk-in-1 (101-1) has undergone a change from its value in the previous clock cycle of the signal clk-dig-tdc (307). Thus, when the value of signal count-1 (104-1) is not equal to the value of signal count1-q (406-1), signal unique-count1 (501-1) is shown to be asserted only during time intervals t610-t612, t618-t620, and t626-t 628.

As described above, the signal unique-count1-q (411-1) is determined based on the following logic:

if (window-identifier && !unique-count1)

unique-count1-q = 0

else if (unique-count1)

unique-count1-q = 1 (logic 1.1)

The logic is evaluated based on the values of the signal window-identifier (332) and the signal unique-count1 (501-1) one clock cycle before the current time. Therefore, at t612, the value of the signal window-identifier (332) under evaluation is considered to be a logic low level (a value in the time interval t610-t 612), and the value of the signal unique-count1 (501-1) under evaluation is considered to be a logic high level. Thus, the first unique generator 410-1 evaluates logic 1.1 and begins setting the signal unique-count1-q (411-1) to a logic high level at t 612.

The counts corresponding to the rising edges of the input clock clk-in-2 (101-2) are shown as being received at times t612, t620, and t 628. Thus, signal count-2 (104-2) is shown as having values 310 between t612-t620, 394 between t620-t628, and 478 between t628-t 632. The signal count2-q (406-2) is the value of the signal count-2 (104-2), but is delayed by one clock cycle of the signal clk-dig-tdc (307) by a flip-flop, i.e. a second count generator 405-2. Thus, when signal count-2 (104-2) has a value 310 beginning at t612, signal count2-q (406-2) is shown to have a value 310 beginning at t614 (after one cycle of signal clk-dig-tdc (307)). Thus, the signal count2-q (406-2) is shown as having a value 310 between t614-t622, a value 394 between t622-t630, and a value 478 between t630-t 632.

When the value of signal count-2 (104-2) is not equal to the value of signal count2-q (406-2), signal unique-count2 is asserted (501-2). In other words, the signal unique-count2 (501-2) is set to a logic high level when the count of the input clock clk-in-2 (101-2) has undergone a change from its value in the previous clock cycle of the signal clk-dig-tdc (307). Thus, when the value of signal count-2 (104-2) is not equal to the value of signal count2-q (406-2), signal unique-count2 (501-2) is shown to be asserted only during time intervals t612-t614, t620-t622, and t628-t 630.

As described above with respect to FIG. 5, the signal unique-count2-q (411-2) is determined based on the following logic:

if (window-identifier && !unique-count2)

unique-count2-q = 0

else if (unique-count2)

unique-count2-q = 1 \ 8230; \8230; \ 8230; (logic 1.2)

The above logic is evaluated based on the values of signal window-identifier (332) and signal unique-count2 (501-2) one clock cycle before the current time as described above with respect to signal unique-count1-q (411-1). Therefore, at t612, the value of the signal window-identifier (332) under evaluation is considered to be a logic low level (a value in the time interval t610-t 612), and the value of the signal unique-count2 (501-2) under evaluation is considered to be a logic high level. Thus, the second unique generator 410-2 evaluates logic 1.2 and begins at t612 with the signal unique-count2-q (411-2) remaining at a logic low level.

Similarly, at t614, for an evaluation of logic 1.2, the value of the signal window-identifier (332) is logic low, and the value of the signal unique-count2 (501-2) is logic high. Thus, the second unique generator 410-2 evaluates the logic 1.2 above and begins setting the signal unique-count2-q (411-2) to a logic high level at t 614.

When the signal unique-count2-q (411-2) is set to a logic high level at t614, the signal window-identifier (332) also becomes a logic high level because both the signal unique-count1-q (411-1) and the signal unique-count2-q (411-2) are logic high levels. As described above, at t616, i.e., after one clock cycle of the signal clk-dig-tdc (307), the signal window-identifier (332) is deasserted.

At t616, to determine the signal unique-count1-q (411-1), the value of the signal window-identifier (332) is logic high, and the value of the signal unique-count1 (501-1) is logic low. Thus, signal unique-count1-q (411-1) is set to a logic low level beginning at t 616.

At t616, to determine the signal unique-count2-q (411-2), the value of the signal window-identifier (332) is logic high, and the value of the signal unique-count2 (501-2) is logic low. Thus, signal unique-count2-q (411-2) is set to a logic low level beginning at t 616.

The values of signal unique-count1-q (411-1), signal unique-count2-q (411-2), and signal window-identifier (332) are generated in a similar manner at the respective times up to t632, as shown in fig. 6.

Thus, the signal window-identifier (332) is shown as identifying the boundaries of windows, where each window corresponds to a pair of consecutive edges of the input clock (in this illustration, input clock clk-in-1 (101-1)).

The manner in which the signal unique-count (501, 411) and the signal window-identifier (332) are generated for a pair of input clocks having integer-related multiples is described next.

10. Generating a signal unique-count and a signal window-identifier for a pair of input clocks having integer-related frequencies

Fig. 7 is a timing diagram (not drawn to scale) illustrating the manner in which signals unique-count (501, 411) and signal window-identifier (332) are generated for a pair of input clocks having integer-related multiples in one embodiment of the present disclosure. In other words, the frequency of one input clock, such as input clock clk-in-1 (101-1), is M times the frequency of another input clock, such as input clock clk-in-2 (101-2), where M is an integer greater than or equal to 2.

In fig. 7, M is shown as 8. Thus, the frequency of the input clock clk-in-1 (101-1) is 8 times the frequency of the input clock clk-in-2 (101-2). Thus, 8 rising edges (E11-E18) of the input clock clk-in-1 (101-1) are shown to exist between 2 consecutive rising edges (E21, E22) of the input clock clk-in-2 (101-2).

FIG. 7 shows exemplary waveforms of the signal clk-dig-tdc (307), the input clock clk-in-1 (101-1), the signal count-1 (104-1), the signal count1-q (406-1), the signal unique-count1 (501-1), the signal unique-count1-q (411-1), the input clock clk-in-2 (101-2), the signal count-2 (104-2), the signal count2-q (406-2), the signal unique-count2 (501-2), the signal unique-count2-q (411-2), and the signal window-identifier (332). In this exemplary implementation, the counts corresponding to the input clocks clk-in-1 (101-1) and clk-in-2 (101-2)) are assumed to be 36 bits.

It is noted here that the rising edges of the input clock are not synchronized with respect to the measurement clock clk-meas (103) or are used in the counting logic 105 or the signal clk-dig-tdc (307). Thus, there may be an uncertainty of at most 3 cycles of the signal clk-dig-tdc (307) between the occurrence of a rising edge and the arrival of the corresponding count. For example, the signal count-1 (104-1) corresponding to the rising edge E11 of the input clock clk-in-1 (101-2) is shown as being received at t710, slightly later than the actual occurrence of the rising edge.

The count corresponding to the rising edge of the input clock clk-in-1 (101-1) is shown as being received at times t710, t716, t718, t720, t722, t724, t726, t728, and t 730. Thus, signal count-1 (104-1) is shown as having a value 297 between t710-t716, a value 381 between t716-t618, a value 465 between t718-t720, a value 549 between t720-t722, a value 633 between t722-t724, a value 717 between t724-t726, a value 801 between t726-t728, a value 885 between t728-t730, and a value 969 between t730-t 736. count1-q (406-1) is the value of signal count-1 (104-1), but is delayed by one clock cycle of signal clk-dig-tdc (307) by a flip-flop, first count generator 405-1. Thus, when signal count-1 (104-1) has a value 297 that begins at t710, signal count1-q (406-1) is shown as having a value 297 that begins at t712 (after one cycle of signal clk-dig-tdc (307)). Thus, each value of signal count1-q (406-1) is shown as being delayed by one period of signal clk-dig-tdc (307) relative to the corresponding value of signal count-1 (104-1) in FIG. 7.

When the value of signal count-1 (104-1) is not equal to the value of signal count1-q (406-1), signal unique-count1 (501-1) is asserted. During time interval t710-t712, signal count-1 (104-1) has value 297 and signal count1-q (406-1) has value 214, so signal unique-count1 (501-1) is shown as being asserted during time interval t710-t 712. Each respective value of signal unique-count1 (501-1) is set to a logic high level during a time interval when the corresponding value of signal count-1 (104-1) does not equal the value of signal count1-q (406-1) during the time interval.

Prior to t710, the signal unique-count1-q (411-1) is shown to have a logic high value. The signal unique-count1-q (411-1) is determined according to the above logic 1.1. Logic 1.1 is evaluated based on the values of signal window-identifier (332) and signal unique-count1 (501-1) one clock cycle before the current time. Therefore, at t712, the value of the signal window-identifier (332) to be evaluated is considered to be a logic low level (value in the interval t710-t 712), and the value of the signal unique-count1 (501-1) to be evaluated is considered to be a logic high level. Thus, the first unique generator 410-1 evaluates the logic described above and continues to hold the signal unique-count1-q (411-1) at a logic high level at t 712.

At t714, to determine the signal unique-count1-q (411-1), the value of the signal window-identifier (332) is logic high, and the value of the signal unique-count1 (501-1) is logic low. Thus, the first unique generator 410-1 evaluates the logic described above and begins to deassert the signal unique-count1-q at t714 (411-1).

When the value of signal count-2 (104-2) is not equal to the value of signal count2-q (406-2), signal unique-count2 is asserted (501-2). Thus, the signal unique-count2 (501-2) is shown to be asserted only during time intervals t710-t712 and t730-t 732.

The signal unique-count2-q (411-2) is determined in a manner similar to the signal unique-count1-q (411-1). Thus, signal unique-count2-q (411-2) is shown asserted during time interval t712-t714 (because the value of signal window-identifier (332) under evaluation is considered to be a logic low level and the value of signal unique-count2 (501-2) under evaluation is considered to be a logic high level). Similarly, signal unique-count2-q (411-2) is also asserted during time interval t732-t 734.

At 612, when the signal unique-count2-q (411-2) is set to a logic high level, the signal window-identifier (332) also becomes a logic high level because both the signal unique-count1-q (411-1) and the signal unique-count2-q (411-2) are logic high. As described above, at t714, i.e., after one clock cycle of the signal clk-dig-tdc (307), the signal window-identifier (332) is deasserted. Similarly, the signal window-identifier is again asserted (332) during time interval t732-t 734.

The phase difference of a pair of input clocks at an integer correlation multiple of frequency is the time between the occurrence of the edge of the slower clock and the occurrence of the nearest edge of the faster clock. Thus, in FIG. 7, the signal window-identifier (332) pulse is shown as being generated upon the occurrence of the rising edge of the input clock clk-in-2 (101-2) (the slower clock), thereby identifying the boundaries of the windows used to generate the respective outputs at the end of each window.

The various modules of core logic as described in detail above enable the TDC 100 to generate a digital value representing a phase difference between a pair of periodic inputs whose frequencies are related to each other by an integer value, i.e., whose frequencies are the same or an integer multiple of the correlation (e.g., 2 times, 3 times, etc.). The manner in which the TDC 100 determines the phase difference for each of the above scenarios is shown below with respect to an exemplary figure.

11. Determining phase difference between a pair of input clocks having the same frequency

Figure 8A is an exemplary timing diagram (not to scale) illustrating the manner in which the TDC 100 determines the phase difference between a pair of clocks having the same frequency. FIG. 8A shows exemplary waveforms of signal clk-dig-tdc (307), input clock clk-in-1 (101-1), signal count-1 (104-1), signal count1-q (406-1), signal unique-count1 (501-1), signal unique-count1-q (411-1), input clock clk-in-2 (101-2), signal count-2 (104-2), signal count2-q (406-2), signal unique-count2 (501-2), signal unique-count2-q (411-2), and signal window-identifier (332). Waveforms of the signal clk-dig-tdc (307), the input clock clk-in-1 (101-1), the signal count-1 (104-1), the signal count1-q (406-1), the signal unique-count1 (501-1), the signal unique-count1-q (411-1), the input clock clk-in-2 (101-2), the signal count-2 (104-2), the signal count2-q (406-2), the signal unique-count2 (501-2), the signal unique-count2-q (411-2), and the signal window-identifier (332) correspond to those shown in fig. 7, and a description thereof will not be repeated here for brevity.

In addition, FIG. 8A shows exemplary waveforms of the signal running-count-diff (433), the signal pos-min (436), the signal neg-max (446), the signal acc-pos-q (442), and the signal acc-neg-q (452). For purposes of this description, the "X" value in the data waveform (signal count-1 (104-1), signal count1-q (406-1), signal count-2 (104-2), signal count2-q (406-2), signal running-count-diff (433), signal pos-min (436), signal neg-max (446), signal acc-pos-q (442), signal acc-neg-q (452)) indicates an "don't care" value. The value "max1" in the data waveform signal pos-min (436) represents the maximum positive threshold value, i.e., (2) in this case ³⁶ -1)。

The rising edges R11-R13 of the input clock clk-in-1 (101-1) are shown as occurring at respective times t810, t818, and t826. Thus, the digital core 110 receives values 289, 373, and 457 of the signal count-1 (104-1), corresponding to each rising edge of the input clock clk-in-1 (101-1), respectively.

Similarly, the rising edges R21-R23 of the input clock clk-in-2 (101-2) are shown as occurring at respective times t812, t820, and t828. Thus, the digital core 110 receives the values 310, 394, and 478 of the signal count-2 (104-2), corresponding to each rising edge of the input clock clk-in-2 (101-2), respectively. Thus, in the illustrative embodiment, the input clock clk-in-2 (101-2) is shown lagging in phase (approximately 90 degrees) with respect to the input clock clk-in-1 (101-1).

Although the counts corresponding to the rising edges of the input clocks (clk-in-1 (101-1) and clk-in-2 (101-2)) (signal count-1 (104-1) and signal count-2 (104-2)) are shown as being received in synchronization with the respective rising edges, in practice, the counts may be received slightly later than the occurrence of the corresponding rising edges of the input clocks clk-in-1 (101-1) and clk-in-2 (102-2).

In response to signal count-2 (104-2) changing its value at t812 (to 310), signal window-identifier is asserted at t814 (332) for one clock cycle of signal clk-dig-tdc (307). Thus, starting at t816, the phase difference between the input clock clk-in-1 (101-1) and the input clock clk-in-2 (101-2) is measured.

Based on the values in the durations (signal count1-q (406-1) minus signal count2-q (406-2)) (based on the pipeline delays described above), signal running-count-diff (433) is shown to have the following values in the corresponding time interval:

t816-t818：running-count-diff (433) = 289 - 310 = -21

t818-t820：running-count-diff (433) = 289 - 310 = -21

t820-t822：running-count-diff (433) = 289 - 310 = -21

t822-t824：running-count-diff (433) = 373 - 310 = 63

the phase difference in the duration t816-t822 represents the phase difference between the rising edge R21 of the input clock clk-in-2 (101-2) and the rising edge R11 of the input clock clk-in-1 (101-1), and the phase difference in the duration t822-t824 represents the phase difference between the rising edge R22 of the input clock clk-in-2 (101-2) and the rising edge R12 of the input clock clk-in-1 (101-1).

At t818, positive minimum generator 435 receives a logic high (signal window-identifier) on path 332 and a value of "-21" (signal running-count-diff) on path 433. Thus, the positive minimum generator 435 sets the value of the signal pos-min (436) to max1 at t 818.

At t820, positive minimum generator 435 receives a logic low level (signal window-identifier) on path 332 and a value of "-21" (signal running-count-diff) on path 433. Thus, the positive minimum generator holds the current value of the signal pos-min (436), i.e., max1, at t 820. In this manner, the value of signal pos-min (436) is shown to be updated based on the values of signal window-identifier (332), signal running-count-diff (433), and the current value of signal pos-min (436).

At t818, negative maximum generator 445 receives a logic high (signal window-identifier) on path 332 and a value of "-21" (signal running-count-diff) on path 433. Therefore, the negative maximum generator 445 sets the value of the signal neg-max (446) to the value of the signal running-count-diff (433), i.e., -21".

At t820, negative maximum generator 445 receives a logic low (signal window-identifier) on path 332 and a value of "-21" (signal running-count-diff) on path 433. Therefore, negative maximum generator 445 holds the current value of signal neg-max (446), i.e., -21 "at t 820. In this manner, the value of signal neg-max (446) is shown to be updated/maintained based on the values of signal window-identifier (332), signal running-count-diff (433), and the current value of signal neg-max (446).

Using similar operations as described above, the TDC 100 determines the phase difference between periodic clock inputs having equal frequencies for other values of the phase difference (leading or lagging).

The manner in which the TDC 100 determines the phase difference between a pair of input clocks having frequencies that are integer multiples of correlation (2 or more) is shown next by way of example.

12. Determining a phase difference between a pair of input clocks having integer-related multiples of a frequency

Figure 8B is a timing diagram (not to scale) illustrating the manner in which the TDC 100 measures the phase difference between a pair of clocks having integer-related multiples of frequency. FIG. 8B shows exemplary waveforms of signal clk-dig-tdc (307), input clock clk-in-1 (101-1), signal count-1 (104-1), signal count1-q (406-1), signal unique-count1 (501-1), signal unique-count1-q (411-1), input clock clk-in-2 (101-2), signal count-2 (104-2), signal count2-q (406-2), signal unique-count2 (501-2), signal unique-count2-q (411-2), signal window-identifier (332), signal running-count-diff (433), signal pos-min (436), signal neg-max (446), signal acc-pos-q (442), and signal acc-neg-q (452). These waveforms correspond to those shown in fig. 8A, and for the sake of brevity, the description thereof is not repeated here. In this exemplary implementation, the counts corresponding to the input clocks clk-in-1 (101-1) and clk-in-2 (101-2)) are assumed to be 36 bits.

As described above with respect to FIG. 7, the frequency of the input clock clk-in-1 (101-1) is shown to be 8 times the frequency of the input clock clk-in-2 (101-2). Thus, the 8 rising edges (D11-D18) of the input clock clk-in-1 (101-1) are shown to exist between 2 consecutive rising edges (D21, D22) of the input clock clk-in-2 (101-2).

Further, as described above with respect to FIG. 7, the signal count-1 (104-1) and the signal count-2 (104-2) are received slightly later than the occurrence of the corresponding rising edges of the input clock clk-in-1 (101-1) and the input clock clk-in-2 (102-2), respectively. Thus, signal count-1 (104-1) received at t854 corresponds to the rising edge D11 of input clock clk-in-1 (101-1) shown to occur at t852, and signal count-2 (104-2) received at t854 corresponds to the rising edge D21 of input clock clk-in-2 (101-2) shown to occur at t 851.

In response to signal count-2 (104-2) changing its value at t854 (to 281), within one clock cycle of signal clk-dig-tdc (307), signal window-identifier is asserted at t855 (332). Thus, starting at t856 (one clock cycle after the window-identifier (332) is asserted), the phase difference between the rising edge D21 of the slower clock clk-in-2 (101-2) and each rising edge (D11-D18) of the faster clock clk-in-1 (101-1) that exists between two consecutive edges D21 and D22 of the slower clock clk-in-2 (101-2) is measured.

Based on the values in the durations (signal count1-q (406-1) minus signal count2-q (406-2)) (based on the pipeline delays described above), signal running-count-diff (433) is shown to have the following values in the corresponding time interval:

t856-t859：running-count-diff (433) = 297 - 281 = 16

t859-t861：running-count-diff (433) = 381 - 281 = 100

t861-t863：running-count-diff (433) = 465 - 281 = 184

t863-t865：running-count-diff (433) = 549 - 281 = 268

t865-t867：running-count-diff (433) = 633 - 281 = 452

t867-t869：running-count-diff (433) = 717 - 281 = 436

t869-t874：running-count-diff (433) = 801 - 281 = 520

t874-t877：running-count-diff (433) = 885 - 281 = 604

thus, the signal running-count-diff (433) is shown as having 8 different values, where each value represents a phase difference between the rising edge D21 of the input clock clk-in-2 (101-2) and a corresponding one of the rising edges D11-D18 (of the clock clk-in-1 (101-1)).

Prior to t857, the signal pos-min (436) is shown to have a value of 17 as a result of a previous (not shown) minimum phase difference between two consecutive rising edges of the input clock clk-in-2 (101-2). At t857, positive minimum generator 435 receives a signal running-count-diff (433) having a value of 16 and receives a logic high (signal window-identifier) on path 332, and thus, positive minimum generator 435 updates signal pos-min (436) to the value of the signal running-count-diff (433), i.e., 16, at t 857. Between t857 and t876, the positive minimum generator 435 maintains the value of the signal pos-min (436) at its current value, i.e., 16, since neither of the signal running-count-diff (433) values exceeds the current value of 16.

Prior to t857, signal neg-max (446) is shown as having a large negative value (-2) ^36-1 ). Beginning at t857, negative maximum generator 445 maintains signal neg-max (446) at a large negative value since all phase difference values are positive.

At t875, the signal window-identifier (332) signal is again asserted, indicating the occurrence of the next rising edge (D22) of the input clock clk-in-2 (101-2). It can be observed that the value 16 is the minimum phase difference of all 8 differences measured between the two signal window-identifier (332) pulses. Thus, at t875, the phase difference between the input clock clk-in-1 (101-2) and the input clock clk-in-2 (101-2) is determined to be 16. As described above, the phase difference of a pair of input clocks at an integer correlation multiple of frequency is the time between the occurrence of an edge of the slower clock and the occurrence of the nearest edge of the faster clock.

According to another aspect of the disclosure, the TDC 100 operates to generate a phase difference when there is jitter in any of the input clocks. The manner in which the TDC operates in the presence of jitter is described next by way of example.

13. Operation of a TDC in the presence of jitter in an input clock signal

Figures 9A and 9B together illustrate the operation of a TDC with an input clock signal having jitter in one embodiment of the present invention. In particular, FIG. 9A is a timing diagram (not to scale) illustrating the manner in which the TDC 100 identifies the presence of jitter in the input clock signal. FIG. 9A shows exemplary waveforms of signal clk-dig-tdc (307), input clock clk-in-1 (101-1), signal count-1 (104-1), signal count1-q (406-1), signal unique-count1 (501-1), signal unique-count1-q (411-1), input clock clk-in-2 (101-2), signal count-2 (104-2), signal count2-q (406-2), signal unique-count2 (501-2), signal unique-count2-q (411-2), signal window-identifier (332), signal running-count-diff (433), signal pos-min (436), neg-max (446), signal acc-pos-q (442), and signal acc-neg-q (452). These waveforms correspond to those shown in fig. 8A, and for the sake of brevity, the description thereof is not repeated here. In addition, FIG. 9A shows exemplary waveforms of signal jitter-present (392) and signal use jitter-approach (393). In this exemplary implementation, the counts corresponding to the input clocks clk-in-1 (101-1) and clk-in-2 (101-2)) are assumed to be 36 bits.

In an exemplary embodiment, the input clock clk-in-1 (101-1) and the input clock clk-in-2 (101-2) represent a pair of clocks having the same frequency with jitter being accompanied in the input clock clk-in-2 (101-2). Rising edges R31-R34 of the input clock clk-in-1 (101-1) are shown as occurring at respective times t910, t915, t919, and t928. Thus, the core logic 110 receives the values 289, 373, 457, and 541 of the signal count-1 (104-1), corresponding to each rising edge of the input clock clk-in-1 (101-1), respectively.

In FIG. 9A, the input clock clk-in-2 (101-2) is shown with jitter. Thus, some rising edges of input clock clk-in-2 (101-2), such as edges R42 and R44, are shown to occur slightly before corresponding rising edges of input clock clk-in-1 (101-1), i.e., R32 and R34, respectively, such as at times t914 and t926 in some cycles, while some rising edges of input clock clk-in-2 (101-2), such as edges R41 and R43, are shown to occur slightly after corresponding rising edges of input clock clk-in-1 (101-2), i.e., R31 and R33, respectively, such as at times t912 and t920 in some cycles.

Based on the values in the durations (signal count1-q (406-1) minus signal count2-q (406-2)) (based on the pipeline delays described above), signal running-count-diff (433) is shown to have the following values in the respective time intervals:

t913-t916：running-count-diff (433) = 289 - 290 = -1

t916-t917：running-count-diff (433) = 289 - 372 = -83

t917-t921：running-count-diff (433) = 373 - 372 = 1

t921-t923：running-count-diff (433) = 457 - 372 = 85

thus, jitter in the input clock clk-in-2 (101-2) is shown to cause a positive phase difference and a negative phase difference. It may be observed that in certain types of jitter (such as random jitter), the probability of jitter causing a positive phase error and a negative phase error may be substantially equal.

The positive minimum generator 435 and the negative maximum generator 445 operate according to the logic described above, and thus generate the signal pos-min (436) and the signal neg-max (446) as shown in FIG. 9A. At t916, the signal window-identifier (332) is asserted, and thus at t918, the signal pos-min (436) is added to the current accumulation value in positive accumulator 440. Thus, beginning at t918, the signal acc-pos-q (442) is shown as having a value of "max1".

At t916, signal window-identifier (332) is asserted, and thus at t918, signal neg-max (446) is added to the current accumulation value in negative accumulator 450. Thus, the signal acc-neg-q (452) is shown to have a value "-1" during the time interval t918-t 924. At t924, the value "max2" is added to the signal acc-neg-q (452), thereby generating the value "max2-1" in the accumulator 450.

It can be observed that both positive accumulator 440 and negative accumulator 450 accumulate large values, exceeding the respective thresholds (i.e., "max1" for positive accumulator 440, and "max2" for negative accumulator 450). This occurs when there are a sufficient number of positive and negative values in the running-count-diff (433). In the absence of jitter, only one accumulator (positive accumulator 440 or negative accumulator 450, but not both) accumulates the threshold. For example, in the illustration of FIG. 8A (input clock clk-in-2 (101-2) lags input clock clk-in-1 (101-1) in phase), only positive accumulator 440 accumulates the threshold. In the diagram of FIG. 8B (input clock clk-in-2 (101-2) precedes input clock clk-in-1 (101-1) in phase), only the accumulator 450 accumulates the threshold.

When both positive accumulator 440 and negative accumulator 450 accumulate large values, it is indicative of jitter in any of the input clock signals, which would otherwise have a zero phase difference.

In time intervals t918-t924, the jitter detector 460 checks whether the values of both signal acc-pos-q (442) and signal acc-neg-q (452) have exceeded the respective threshold values. The signal acc-pos-q (442) exceeds the corresponding threshold, while the signal acc-neg-q (452) does not. Thus, the jitter detector 460 does not generate a logic high level (signal jitter-present) on path 392.

At t924, the jitter detector 460 checks whether the values of both the signal acc-pos-q (442) and the signal acc-neg-q (452) have exceeded respective threshold values. Jitter detector 460 determines that both accumulators have exceeded the respective thresholds. Thus, the jitter detector 460 generates a logic high (signal jitter-present) on path 392. As described above, the jitter detector 460 deasserts the signal jitter-present after one clock cycle of the signal clk-dig-tdc (307) (392). In addition, at t924, jitter detector 460 generates a logic high level (signal use-jitter-propoach) on path 393. Jitter detector 460 remains asserted (logic high) until the end of the accumulation of the predetermined number of phase difference samples (indicated by assertion of signal nsample-done on path 447), after which jitter detector 460 de-asserts signal use-jitter-propach (393).

At t926, as a result of receiving a logic high level (signal jitter-present) on path 392, positive accumulator 440 and negative accumulator 450 clear (set to boundary values, e.g., zero) the respective accumulation values (signal acc-pos-q (442) and acc-neg-q (452)). Thus, starting at t926, the signal acc-pos-q (442) and the signal acc-neg-q (452) are shown as having zero values. Similarly, beginning at t926, the positive minimum generator 435 and the negative maximum generator 445, upon receiving a logic high level (signal jitter-present) on path 392, also clear (set to a boundary value, e.g., zero) the respective values and are therefore shown as having a zero value. Further, at t926, the window counter 444 resets the sample counter to zero, ending the current accumulation period and beginning a new accumulation period (of a predetermined number of windows).

In one embodiment, only positive accumulator 440 is restarted, and negative accumulator 450 is not used in the presence of jitter. Figure 9B is a timing diagram (not to scale) illustrating the manner in which the TDC 100 operates to provide phase difference in the presence of jitter in one embodiment of the present disclosure. The timing diagram of fig. 9B illustrates the operation of the TDC after time t930 of fig. 9A.

Accordingly, the exemplary waveforms of FIG. 9B, i.e., signal clk-dig-tdc (307), input clock clk-in-1 (101-1), signal count-1 (104-1), signal count1-q (406-1), signal unique-count1 (501-1), signal unique-count1-q (411-1), input clock clk-in-2 (101-2), signal count-2 (104-2), second count2-q (406-2), signal unique-count2 (501-2), signal unique-count2-q (411-2), signal window-identifier (332), signal running-count-diff (433), signal pos-min (436), signal neg-max (446), signal acc-pos-q (442), and signal acc-neg-q (452), will not be repeated herein for brevity and for brevity for those shown in FIG. 9A.

As described above with respect to fig. 9A, prior to t940, the presence of jitter has been identified and positive accumulator 440 and negative accumulator 450 have been reset to boundary values (e.g., zeros in the illustrative embodiment).

Beginning at t940, positive accumulator 440 accumulates phase difference values as described below, while negative accumulator 450 does not accumulate any values. The input clock clk-in-2 (101-2) is shown as having continuous jitter. Since signal use-jitter-adapt (393) (not shown) is a logic high level (starting at t924 in fig. 9A), positive accumulator 440 calculates the lower magnitude (absolute minimum) of signals pos-min (436) and neg-max (446) received in each window and accumulates (adds) the calculated values with the corresponding sign to the current value of positive accumulator 440.

Thus, at t948, positive accumulator 440 calculates the lower minimum of values "max1" and "-1" and adds "-1" to signal acc-pos-q (442) (which is zero in this case). Similarly, at t954, positive accumulator 440 calculates the lower minimum of "1" and "max2" and adds "+1" to signal acc-pos-q (442) (in this case "-1"), generating a "0". Using similar operation, the signal acc-pos-q (442) is shown to have a value "-1" during time intervals t948-t954, a value "0" during time intervals t954-t960, and a value "-1" during time intervals t 960-966.

Thus, the accumulated phase difference is substantially equal to zero or a very small value. The accumulated value divided by the number of accumulated samples (equal to the number of windows, e.g. 1024) is provided as the phase difference between the input clocks.

It will be appreciated that for a given jitter value (signal jitter-input), the greater the number of samples accumulated (i.e., the longer the averaging time), the greater the accuracy of the estimated phase difference. After averaging, the jitter in the input clock may be reduced by the signal jitter-input/sqrt (nsample).

Although the exemplary implementations depicted in fig. 9A and 9B are described with respect to input clocks having the same frequency, aspects of the present invention are applicable to input clocks having integer related multiples of greater than one.

Further, while positive accumulator 440, running accumulator data generator 465 and accumulator valid data generator 475 are shown to operate using alternative logic in the presence of jitter, in alternative embodiments such logic may be implemented in separate modules with appropriate changes to the signal paths. Further, in an alternative embodiment, when jitter is present, the output of positive accumulator 440 may be provided as an accumulated phase difference on a separate path.

According to another aspect of the disclosure, the TDC 100 accumulates a predetermined number (provided by the user) of phase differences between the input clocks (clk-in-1 (101-1) and clk-in-2 (101-2)) and averages the accumulated values (i.e., the accumulated value divided by the number of phase difference samples) to potentially increase the resolution with which the phase differences may be determined. The manner in which this accumulation is achieved is described by way of example next.

14. Accumulation of phase difference samples

Fig. 10 is a timing diagram (not drawn to scale) showing the accumulation of phase difference samples in one embodiment of the disclosure. Specifically, the diagram is shown as a waveform containing a signal running-acc-data (491), a signal nsample-done (447), a signal running-nsample (492), a signal output (115), and a signal data-valid (493). The waveforms on paths 115, 493, 491 and 493 are available in modes (1) and (2) of TDC 100 (as described above).

As previously described with respect to FIG. 4B, the run accumulator data generator 465 generates the running-acc-data (491) and running-nsample (492) signals. The signal running-acc-data (491) represents the accumulated phase difference value at the end of each window.

In the case where the input clocks (clk-in-1 (101-1) and clk-in-2 (101-2) have a small frequency, such as about 1 Hz, and the user has programmed a relatively high number, say 1024, of samples of the predetermined number of phase difference samples to be accumulated, it may be desirable for the signal running-acc-data (491) to persist so each accumulation period will last 1024 seconds.

Referring to FIG. 10, two accumulation periods are shown, one between time intervals t1010-t1025, and the next between t1025-t 1035. Accordingly, signal nsample-done is asserted at times t1020 and t1032 (447).

At time t1025 (at the end of the first accumulation period within duration t1010-t 1025), the accumulated data on path 115 is available and held at that value (accumulator valid data 1) until the next accumulation period completes (in this case, until t 1035). At t1025, signal data-valid (493) is also asserted to indicate that the data available on path 115 is valid. If the user reads the output on path 115 during time interval t1025-t1035, the user is provided with an updated value (accumulator valid data 1) at t 1025.

In mode (1), referring to FIG. 8A, when the accumulation period ends at t830 (based on the predetermined number of phase difference samples provided as user input), the accumulator valid data generator 475 determines the absolute minimum of the signal acc-pos-q (442) and the signal acc-neg-q (452) and provides the value (signal output) on path 115. Thus, starting at t830 until the end of the next accumulation period, the value "21" is provided as signal output (115).

In mode (2), referring to FIG. 8B, prior to t857, the signal acc-pos-q (442) is shown as having a value 655 as a result of a previous accumulation (not shown). At t855, the signal window-identifier (332) is asserted, and thus at t857, the signal pos-min (436) is added to the current accumulated value. Thus, beginning at t857, the signal acc-pos-q (442) is shown as having a value of (655 + 17), 672. At t878, after asserting the window-identifier (332) at t875, the pos-min signal (436) is added to the current accumulation value. Thus, beginning at t878, the signal acc-pos-q (442) is shown as having a value of (672 + 16), 688.

With continued reference to FIG. 8B, prior to t857, the signal acc-neg-q (452) is shown as having a large negative value (-2) as a result of a previous accumulation (not shown) ^36-1 ). At t855, the signal window-identifier (332) is asserted, and thus at t857 the signal neg-max (446) is added to the current accumulation value. Thus, starting at t857, the signal acc-neg-q (452) is shown to have a value of-68, 719,476,734.

Thus, when the accumulation period ends at t875 (based on the predetermined number of phase difference samples provided as user input), accumulator valid data generator 475 determines the absolute minimum of signal acc-pos-q (442) and signal acc-neg-q (452), and provides the value (signal output) on path 115. Thus, starting at t878 until the end of the next accumulation period, the value 672 is provided as signal output (115).

The value of the signal running-nsample (492) is incremented each time the window-identifier (332) is asserted (not shown). Each value of the data signal running-acc-data (491) is also updated each time the window-identifier (332) is asserted (after each window is over). Thus, if the user wishes to check the accumulation value between the beginning and end of the accumulation period, the user can read the signal running-acc-data on path 491. The running-nsample data available on path 492 indicates the number of accumulated samples available on path 491.

For example, referring now to FIG. 10, if the user reads the signal running-acc-data (491) at time t1015, the signal running-nsample (492) indicates that 2 samples have been accumulated, and the absolute minimum of the signal acc-pos-q (442) and the signal acc-neg-q (452) is available on path 491 (signal running-acc-data).

In mode (1), referring to FIG. 8A, positive accumulator 440 and negative accumulator 450 accumulate signal pos-min (436) and signal neg-max (446), respectively, as shown in FIG. 8A. For the running accumulator data provided as output on path 491, the absolute minimum of instantaneous values of signal acc-pos-q (442) and signal acc-neg-q (452) will be determined. Thus, the signal running-acc-data (491) provides a value of "21" for a duration of t818-t826, and a value of "42" for a duration of t826-t 832. In pattern (2), referring to FIG. 8B, the signal running-acc-data (491) provides a value 655 for a duration t857-t878, and a value 672 beginning at t 878. Thus, the TDC 100 provides accumulated data in accumulator modes (1) and (2).

In this manner, aspects of the present invention enable a TDC to operate with a periodic input having jitter. The TDC 100 implemented as described above may be incorporated into a larger device or system as briefly described below.

15. System for controlling a power supply

Fig. 11 is a block diagram of an exemplary signal processing system incorporating a phase locked loop implemented according to various aspects of the present disclosure as described in detail above. System 1100 is shown to contain synchronous ethernet (SyncE) timing card-1 1110 and synchronous ethernet timing card-2 1120, as well as line cards 1 through N, of which only two line cards 1130 and 1150 are shown for simplicity. Line card 1130 is shown to contain a Jitter Attenuator phase-locked loop (Jitter Attenuator PLL) 1140 and a synchronous Ethernet PHY transmitter 1145. Line card 1150 is shown to contain a jitter attenuator phase lock loop 1160 and a synchronous ethernet PHY transmitter 1165. The components of fig. 11 may operate in accordance with the synchronous ethernet (SyncE) networking standard. As is well known in the related art, synchronous ethernet is a physical layer (PHY) -based technology for implementing synchronization in packet-based ethernet. The synchronous ethernet clock signal sent over the physical layer should be traceable to an external master clock (e.g., from a timing card such as synchronous ethernet timing card 1110 or 1120). Thus, the ethernet packet is retimed with respect to the master clock and then transmitted in the physical layer. Thus, data packets (e.g., on path 1131 and path 1151) are retimed and transmitted without any timestamp information being recorded in the data packets. These packets may be generated by a corresponding application such as IPTV (internet protocol television), voIP (voice over internet protocol), etc.

Thus, line card 1130 receives a packet on path 1131 and forwards the packet on output 1146 after the packet has been retimed (synchronized) to the master clock. Similarly, line card 1150 receives the packet on path 1151 and forwards the packet on output 1166 after it has been retimed (synchronized) to the master clock.

The master clock (1111/clock-1) is generated by synchronous ethernet timing card-1 1110. Synchronous ethernet timing card-2 1120 generates a redundant clock (1121/clock-2) that will be used by line cards 1130 and 1150 in the event of a failure of the primary clock 1111. A master clock 1111 and a redundant clock 1121 are provided to each of the line cards 1130 and 1150 via a backplane (represented by numeral 1170).

In the line card 1130, the jitter attenuator phase locked loop 1140 may contain a TDC 100 for detecting the phase difference between its input clocks as described in detail above, and receive a master clock 1111 and a redundant clock 1121. The jitter attenuator phase lock loop 1140 generates an output clock 1141 that is used to synchronize (retime) packets received on path 1131 and forwarded on path 1146 to the retimed packets.

Similarly, in linecard 1150, the jitter attenuator phase locked loop 1160 may also contain a TDC 100 for detecting the phase difference between its input clocks as described in detail above, and receiving a master clock 1111 and a redundant clock 1121. The jitter attenuator phase-locked loop 1160 generates an output clock 1161 that is used to synchronize (retime) packets received on path 1151 and to transition out to retimed packets on path 1166. Upon loss of phase, the jitter attenuator phase lock loop 1160 is designed to provide phase lock in the manner described in detail above.

16. Conclusion

Reference throughout this specification to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

It should be understood that the particular structure or configuration of the various modules/components described above is by way of example only. However, alternative embodiments using different configurations will be apparent to those skilled in the relevant art from reading the disclosure provided herein.

While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present disclosure should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents. All the equivalent structures or equivalent processes performed by using the contents of the specification and the drawings of the present application, such as the combination of technical features between the embodiments, or the direct or indirect application to other related technical fields, are all included in the scope of the present application.

Claims (14)

1. A time-to-digital converter, the time-to-digital converter comprising:

counting logic to generate a first and a second count sequence for a first and a second periodic signal, respectively, received as input signals, the first count sequence representing respective times at which a first sequence of edges having a first direction of the first periodic signal occurs on a time scale, the second count sequence representing respective times at which a second sequence of edges having the first direction of the second periodic signal occurs on the time scale; and

core logic to identify whether jitter is present in any of the first periodic signal and the second periodic signal by processing the first count sequence and the second count sequence;

wherein the core logic operates to generate a sequence of phase differences between the first and second periodic signals according to a first method in the absence of jitter and according to a second method in the presence of jitter; wherein the second periodic signal has a frequency that is an integer multiple of a frequency of the first periodic signal;

the core logic is further operative to generate a sequence of window boundaries identifying respective times at which edges of the first direction have occurred in both the first and second periodic signals, wherein a duration between two consecutive boundaries constitutes a corresponding window of the sequence of windows; subtracting the respective first counts of the first sequence of counts from the respective subsequences of counts of the second sequence of counts in each window to generate a sequence of time differences in each window, wherein each time difference has a corresponding sign and magnitude, wherein the first method comprises calculating each phase difference in the sequence of phase differences by summing a positive time difference and a negative time difference in separate accumulators, wherein the second method comprises calculating each phase difference in the sequence of phase differences by summing both the positive time difference and the negative time difference into a single accumulator.

2. The time-to-digital converter of claim 1, wherein the time-to-digital converter is operable when the integer multiple is one and when the integer multiple is greater than 1.

3. The time-to-digital converter of claim 2, wherein the core logic comprises:

an input analyzer module to generate the window boundary sequence from the first count sequence and the second count sequence; and the number of the first and second groups,

an output generator module to generate one value of a sequence of values in each window of the sequence of windows, wherein the value indicates a corresponding phase difference for the window.

4. The time-to-digital converter of claim 3, wherein the output generator module comprises:

a subtraction unit for generating the sequence of time differences for each window;

a positive minimum generator for selecting a positive minimum representing a minimum among positive values contained in the sequence of time differences;

a negative maximum generator for selecting a negative maximum representing a maximum of negative values contained in the time difference sequence;

a first accumulator to receive the sequence of positive minima covering a corresponding window and to add values in the sequence of positive minima to generate a first accumulated value;

a second accumulator to receive a sequence of the negative maximums covering the corresponding window and to add values in the sequence of the negative maximums to generate a second accumulated value; and the number of the first and second groups,

a jitter detector module to receive the first and second accumulated values and to generate a jitter present signal indicating whether the jitter is present,

wherein the jitter detector module determines that the jitter is present if the accumulated values of both the first accumulator and the second accumulator have exceeded respective threshold values.

5. The time-to-digital converter of claim 4, wherein the output generator module comprises:

a first accumulator output module to receive the first and second accumulation values and to generate a minimum magnitude of the first and second accumulation values as an accumulated phase difference for the corresponding window when it is determined that jitter is not present.

6. The time-to-digital converter of claim 5, wherein when it is determined that the jitter is present,

one of the first accumulator and the second accumulator is reset to a boundary value, wherein the reset accumulator thereafter accumulates one of the positive minimum value and the negative maximum value having a lower magnitude in each window,

wherein the first accumulator output module forwards an accumulated value in the reset accumulator to the accumulated phase difference.

7. The time-to-digital converter of claim 6, wherein the output generator module further comprises:

a window counter for counting up to a predetermined number of the windows,

wherein the first accumulator and the second accumulator are reset when the window counter counts up to the predetermined number of the windows and when the jitter detector module detects the presence of jitter,

when jitter is determined to be present, the reset accumulator is used to accumulate the predetermined number of the windows before checking again for jitter in subsequent time differences.

8. The time-to-digital converter of claim 7, further comprising a second accumulator output module to determine a lower magnitude of the first and second accumulation values received at the end of the predetermined number of windows and to provide the lower magnitude as an accumulated phase difference when jitter is not present,

the second accumulator output module is to forward an output of the reset accumulator spanning the predetermined number of window numbers to the accumulated phase difference when jitter is present.

9. A method of processing a periodic signal in a time-to-digital converter, the method comprising:

receiving a first and a second count sequence of a first and a second periodic signal, respectively, the first count sequence representing respective times at which a first sequence of edges having a first direction of the first periodic signal occurs on a time scale, the second count sequence representing respective times at which a second sequence of edges having the first direction of the second periodic signal occurs on the time scale; and

checking the first and second count sequences to identify whether jitter is present in any of the first and second periodic signals;

when the first periodic signal has the same frequency as the second periodic signal, the checking includes: subtracting each count in the first count sequence from the corresponding count in the second count sequence to form a difference sequence; and checking whether there are a sufficient number of positive and negative values in the sequence of difference values to indicate whether there is jitter in one of the two periodic signals;

when the second periodic signal has a frequency that is an integer multiple of a frequency of the first periodic signal, the checking comprises: generating a sequence of window boundaries identifying respective instants at which an edge of the first direction has occurred in both the first and second periodic signals, wherein a duration between two consecutive boundaries constitutes a corresponding window of the sequence of windows; subtracting the respective first count of the first count sequence from the respective count subsequence of the second count sequence in each window to generate a sequence of difference values in each window; identifying a positive minimum and a negative maximum in the sequence of difference values; accumulating the positive minimum values of a sequence of windows as a first accumulated value and the negative maximum values of the sequence of windows as a second accumulated value, when there is no jitter, selecting a smaller magnitude of the first and second accumulated values as the accumulated phase difference for the corresponding window.

10. The method of claim 9, wherein the checking checks whether both the first accumulation value and the second accumulation value have exceeded respective thresholds to infer whether jitter is present.

11. The method of claim 10, when jitter is present, further comprising:

resetting one of the first and second accumulation values to a boundary value,

thereafter continuing to accumulate one of the positive minimum and negative maximum values having lower magnitudes in each window,

wherein an accumulated value that continues to accumulate after a reset is forwarded as the accumulated phase difference.

12. A signal processing system, characterized in that the signal processing system comprises:

a TDC for generating an output sequence representing phase differences between respective instants of time between a first periodic signal and a second periodic signal received as input signals, wherein the TDC is operable to identify whether jitter is present in any of the first and second periodic signals and to perform a corrective action to mitigate the effect of jitter in the measurement of the phase differences; and a processing module for processing the output sequence;

wherein the TDC comprises:

counting logic to generate a first and a second count sequence for the first and the second periodic signal, respectively, the first count sequence representing respective times at which a first edge sequence having a first direction of the first periodic signal occurs on a time scale, the second count sequence representing respective times at which a second edge sequence having the first direction of the second periodic signal occurs on the time scale; and

core logic to identify whether jitter is present in any of the first and second periodic signals by processing the first and second count sequences; wherein the core logic is operative to generate the output sequence between the first and second periodic signals according to a first method in the absence of jitter and according to a second method in the presence of jitter;

wherein the second periodic signal has a frequency that is an integer multiple of a frequency of the first periodic signal, the core logic further operative to: generating a sequence of window boundaries identifying respective instants at which an edge of the first direction has occurred in both the first and second periodic signals, wherein a duration between two consecutive boundaries constitutes a corresponding window of the sequence of windows; subtracting the respective first counts of the first sequence of counts from the respective subsequences of counts of the second sequence of counts in each window to generate a sequence of time differences in each window, wherein each time difference has a corresponding sign and magnitude, the first method includes calculating each output in the sequence of outputs by summing a positive time difference and a negative time difference in separate accumulators, the second method includes calculating each output in the sequence of outputs by summing both the positive time difference and the negative time difference in a single accumulator.

13. The signal processing system of claim 12, further comprising a phase-locked loop including the TDC, and the processing module operates to minimize any phase difference between the first and second periodic signals represented by the output sequence.

14. The signal processing system of claim 13, wherein the TDC is operable when the integer multiple is one and when the integer multiple is greater than 1.

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