CN114979522A - Adaptive pixel level high dynamic CMOS image sensor and implementation method thereof - Google Patents

Abstract

The invention discloses a self-adaptive pixel-level high-dynamic CMOS image sensor and a realization method thereof.A pixel array outputs photoelectric signals which are respectively input to a column-level ADC reading circuit and a pixel-level ADC circuit; a comparator in the column ADC readout circuit receives the photoelectric signal and the ramp signal respectively, and the comparison result is transmitted to a data synthesizer through a counter; the comparison unit in the pixel ADC circuit receives the photoelectric signal and the reference signal respectively, the comparison result is processed by the register unit and then is transmitted to the control unit and the data synthesizer respectively, the control unit generates control duration data and feeds the control duration data back to the pixel array, and the final result is generated in the data synthesizer and is output. The high real-time characteristic of the pixel level ADC circuit and the high-precision characteristic of the column level ADC reading circuit are organically combined, the final result is output by the data synthesizer, and the high dynamic imaging requirement is met when the light ray changes rapidly.

Description

Adaptive pixel level high dynamic CMOS image sensor and implementation method thereof

Technical Field

The invention belongs to the technical field of image sensors, and relates to a self-adaptive pixel-level high-dynamic CMOS image sensor and an implementation method thereof.

Background

The CMOS image sensor is widely applied to space detection, earth observation, industrial monitoring and consumer electronics, and meets the application requirements of target acquisition, detection perception, imaging shooting and the like through collection of various types of complex light. The dynamic range of the CMOS image sensor is a range capable of monitoring the intensity of light, and due to the fact that the trap capacity of the device is limited, when incident light is too strong, pixels are rapidly saturated, and strong light information is lost. The dynamic range of the natural world from direct sunlight to dark night reaches 180dB, and a sensor with a wide dynamic range can detect a wide scene illumination range, so that images with more details can be generated. The dynamic range of the device is improved, so that the device is favorable for good scientific detection, industrial application and imaging quality, and has important value for improving technological strength and national life.

Currently employed high dynamic range implementations include: potential well capacity regulation technology, multiple sampling technology and logarithmic response technology. The potential well capacity regulating technology is to increase the capacity of the potential well by one or several times during exposure by adding the transverse overflow gate, so that the transmission curve of the charge of the CMOS image sensor changing along with the light intensity is compressed. The multiple sampling technology is used for sampling the same scene for multiple times under different exposure times and combining the output of the multiple sampling into an image with a large dynamic range. The logarithmic response technology utilizes the characteristic that an MOS transistor connected with a diode works in a sub-threshold region to obtain a logarithmic response transmission curve of the photodiode.

In the prior art, a high dynamic implementation method mainly adopts a planar 2D structure and adopts a single pixel level ADC or a single column level ADC. Referring to fig. 8, in the overall structure diagram of the high dynamic image sensor in the prior art, the pixel array and the column ADC readout circuit are located on the same plane, and respectively complete photoelectric conversion and analog-to-digital conversion, and a high dynamic configuration signal is input through an external SPI interface to achieve dynamic range improvement through light determination. Referring to fig. 9, the pixel array includes a global exposure control tube, a transmission tube, a high dynamic reset tube, a source following tube and a readout control tube, the column ADC readout circuit includes a comparator and a counter, the voltage and the control time of the high dynamic tube are adjusted by external configuration, a high dynamic target is achieved, but a high dynamic mode is determined by shooting a scene, the feedback period is long, the shooting scene of light and shade high speed conversion cannot be adapted, the imaging requirement of high dynamic cannot be met, the longitudinal space is not fully utilized, and the space utilization rate is yet to be improved.

Disclosure of Invention

The invention aims to solve the problems that only a single ADC is used in the prior art, the high dynamic calibration instantaneity is poor, and the high dynamic imaging requirement cannot be met under the condition of rapid light ray conversion, and provides a self-adaptive pixel-level high dynamic CMOS image sensor and an implementation method thereof.

In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:

a self-adaptive pixel-level high-dynamic CMOS image sensor comprises a pixel array, a column-level ADC reading circuit and a pixel-level ADC circuit;

the pixel array and the column-level ADC reading circuit are arranged on an upper chip, the pixel-level ADC circuit is arranged on a lower chip, and a 3D stacking structure is arranged between the upper chip and the lower chip;

the pixel array outputs photoelectric signals, and the photoelectric signals are respectively input to the column-level ADC reading circuit and the pixel-level ADC circuit;

the column-level ADC readout circuit comprises a comparator, a counter and a data synthesizer, wherein the negative end of the comparator receives an optical electric signal, the positive end of the comparator inputs a ramp signal, and a comparison result is transmitted to the data synthesizer through the counter;

the pixel level ADC circuit comprises a comparison unit, a control unit and a register unit, wherein the positive end of the comparison unit receives a photoelectric signal, the negative end of the comparison unit receives a reference signal, a comparison result is processed by the register unit and then is respectively transmitted to the control unit and a data synthesizer, the control unit generates control duration data and feeds the control duration data back to the pixel array, and a final result is generated in the data synthesizer and is output.

The invention is further improved in that:

the pixel array comprises a global exposure control tube, a transmission tube, a high dynamic reset tube, a source following tube, a reading control tube, a diode and a capacitor, wherein drain electrodes of the global exposure control tube, the high dynamic reset tube and the source following tube are all connected with VDD, a source electrode of the global exposure control tube is grounded through the diode after being connected with a source electrode of the transmission tube, the drain electrode of the transmission tube and the source electrode of the high dynamic reset tube are connected to an FD point, the FD point is connected with a grid electrode of the source following tube and is grounded through the capacitor, the source electrode of the source following tube is connected with the drain electrode of the reading control tube, and the source electrode of the reading control tube outputs an optical electrical signal.

The comparison unit comprises a first comparator, a second comparator and a third comparator, positive input ends of the first comparator, the second comparator and the third comparator are photoelectric signals, and negative input ends of the first comparator, the second comparator and the third comparator are respectively a reference level high VREFH, a reference level VREF and a reference level low VREFL.

The reference level high VREFH, the reference level VREF, and the reference level low VREFL are specifically expressed as:

where V0 is the output voltage value under the pixel reset condition, and V _ full scale is the difference between the voltage value output when the pixel is saturated and the voltage value output when the pixel is reset.

The register unit is a truth table register, and the output result of the comparison unit is compared with the numerical value in the truth table register to judge the light intensity.

And a copper-copper interconnection structure is adopted between the upper chip and the lower chip.

A realization method of a self-adaptive pixel-level high-dynamic CMOS image sensor comprises the following steps:

the pixel array outputs photoelectric signals, the comparison units of the pixel-level ADC circuit receive the photoelectric signals for comparison, the photoelectric signals are respectively input to positive input ends of a first comparator, a second comparator and a third comparator, negative input ends of the first comparator, the second comparator and the third comparator are respectively a reference level high VREFH, a reference level VREF and a reference level low VREFL, and digital signals are output after comparison is completed;

comparing the digital signals in a truth table register according to the digital signals, judging the light intensity, outputting a corresponding high-bit digital signal to a data synthesizer by the truth table register, determining the corresponding control duration data output by a time controller, feeding the control duration data back to a pixel array by the time controller, and adjusting a high dynamic reset tube in real time;

the photoelectric signal is input to the negative input end of the comparator and compared with the ramp signal, when the photoelectric signal is greater than the ramp signal, the comparator is turned over, the counter counts for the first time, and the counting result is transmitted to the data synthesizer;

and the data synthesizer synthesizes the received data and outputs a final result.

When the photoelectric signal is smaller than VREFL, the comparison unit outputs 000; when the photoelectric signal is smaller than VREF, the comparison unit outputs 001; when the photoelectric signal is smaller than VREFH, the comparison unit outputs 011; when the photo signal is greater than VREFH, the comparing unit outputs 111.

Compared with the prior art, the invention has the following beneficial effects:

the photoelectric signal output by the pixel array is utilized to realize real-time detection and processing of light in the pixel level ADC circuit and the comparison calculation of control time, so that the target of high dynamic control is achieved, the high real-time characteristic of the pixel level ADC circuit and the high-precision characteristic of the column level ADC reading circuit are organically combined, the final result is output by the data synthesizer, the high dynamic imaging requirement is realized when the light changes rapidly, and the longitudinal space is fully utilized by adopting a 3D stacking framework.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

FIG. 1 is a diagram of the overall structure of an adaptive pixel-level high dynamic CMOS image sensor according to the present invention;

FIG. 2 is a detailed structure diagram of an adaptive pixel level high dynamic CMOS image sensor according to the present invention;

FIG. 3 is a timing diagram of a sensor pre-exposure of the present invention;

FIG. 4 is a timing diagram of the high dynamic state of the sensor of the present invention;

FIG. 5 is a graph of high dynamic reset tube voltage;

FIG. 6 is a graph of the high dynamic voltage of the sensor of the present invention;

FIG. 7 is a flow chart of the sensor operation of the present invention;

fig. 8 is an overall structure diagram of a high dynamic image sensor in the prior art;

fig. 9 is a detailed structural diagram of a high dynamic image sensor in the prior art.

Wherein: 101-pixel array, 102-column level ADC reading circuit, 103-pixel level ADC circuit and 10-global exposure control tube; 11-a transfer pipe; 12-high dynamic reset tube; 13-source follower tube; 14-readout control tube; 15-a first comparator; 16-a second comparator; 17-a third comparator; 18-a time controller; 19-truth table register; 20-a comparator; 21-a counter; 22-data synthesizer.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures.

In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which is usually arranged when the product of the present invention is used, the description is merely for convenience and simplicity, and the indication or suggestion that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, cannot be understood as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.

Furthermore, the term "horizontal", if present, does not mean that the component is required to be absolutely horizontal, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.

In the description of the embodiments of the present invention, it should be further noted that unless otherwise explicitly stated or limited, the terms "disposed," "mounted," "connected," and "connected" should be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

The invention is described in further detail below with reference to the accompanying drawings:

referring to fig. 1, the overall structure diagram of the adaptive pixel-level high dynamic CMOS image sensor of the present invention includes a pixel array 101, a column-level ADC reading circuit 102, and a pixel-level ADC circuit, where the pixel array 101 and the column-level ADC circuit 102 are disposed on an upper chip, the pixel-level ADC circuit 103 is disposed on a lower chip, and nodes of the upper chip and the lower chip are connected through metal connection columns.

Referring to fig. 2, a specific structure diagram of the adaptive pixel level high dynamic CMOS image sensor of the present invention includes a global exposure control transistor 10, a pass transistor 11, a high dynamic reset transistor 12, a source follower transistor 13, a readout control transistor 14, a diode and a capacitor in a pixel array 101, a comparator 20, a counter 21 and a data synthesizer 22 in a column ADC readout circuit 102, a first comparator 15, a second comparator 16, a third comparator 17, a time controller 18 and a truth table register 19 in a pixel level ADC circuit 103, drains of the global exposure control transistor 10, the high dynamic reset transistor 12 and the source follower transistor 13 are all connected to VDD, a source of the global exposure control transistor 10 is connected to a source of the pass transistor 11 and then grounded through the diode, a drain of the pass transistor 11 and a source of the high dynamic reset transistor 12 are connected to an FD point, the FD point is connected to a gate of the source follower transistor 13 and grounded through the capacitor, the source electrode of the source follower tube 13 is connected with the drain electrode of the readout control tube 14, and the source electrode of the readout control tube 14 outputs an optical electro-signal; the negative end of the comparator 20 receives the photoelectric signal, the positive end inputs the ramp signal, and the comparison result is transmitted to the data synthesizer 22 through the counter 21; the comparison unit comprises a first comparator 15, a second comparator 16 and a third comparator 17, positive input ends of the first comparator 15, the second comparator 16 and the third comparator 17 are all photoelectric signals, negative input ends of the first comparator 15, the second comparator 16 and the third comparator 17 are respectively a reference level high VREFH, a reference level VREF and a reference level low VREFL, the photoelectric signals and the reference signals are compared to output thermometer codes, comparison is carried out in a truth table register 19, the strength of light is judged, the truth table register 19 outputs corresponding high-bit digital signals to a data synthesizer 22, it is determined that a time controller 18 outputs corresponding control duration data, the time controller 18 feeds the control duration data back to the pixel array 101, and real-time adjustment is carried out on the high dynamic reset tube 12; the photoelectric signal is input to the negative input end of the comparator 20 and compared with the ramp signal, when the photoelectric signal is greater than the ramp signal, the comparator 20 is turned over, the counter 21 counts for one time, and the counting result is transmitted to the data synthesizer 22; the data synthesizer 22 synthesizes the received data and outputs the final result.

Referring to fig. 3, which is a timing diagram of the sensor pre-exposure of the present invention, the global exposure control tube 10 is used as a global reset control switch, and is turned on once at the beginning of each frame to reset the photodiodes of the entire pixel array; before transferring the image signal of the whole pixel array from the PD to the FD, the high dynamic reset tube 12 is opened to reset the FD; after resetting of the FD point is completed, the transmission pipes 11 of the whole pixel array are simultaneously opened, image signals are transferred to the FD point from the PD, all pixels are executed in parallel due to the adoption of a pixel-level ADC structure, the row selection switch source is opened along with the pipe 13, light intensity electric signals are read out, and the light intensity electric signals enter the column-level ADC reading circuit 102. The photo signal is compared with a reference level high VREFH, a reference level VREF and a reference level low VREFL by comparators 15-17. The voltage value output when the pixel is saturated is Vf, the output voltage value under the pixel reset condition is V0, the difference between the Vf and the output voltage value is the pixel output swing V _ full scale, wherein the voltage values of VREFL, VREF, and VREFH are respectively:

as shown in Table 1, the comparator outputs thermometer codes, and the values of t 1-t 3 are determined by comparing the truth table. A, B, C are respectively the outputs of comparators 15-17, because the stronger the light intensity, the lower the PIXEL output voltage value, when the light intensity is strong, the output voltage of PIXEL _ OUT is less than VREFL, ABC outputs 000; when the light intensity is strong, the output voltage of PIXEL _ OUT is less than VREF, and ABC outputs 001; when the light intensity is weaker, the output voltage of the PIXEL _ OUT is smaller than VREFH, and ABC outputs 011; when the light intensity is weak, the output voltage of the PIXEL _ OUT is greater than VREFH and ABC outputs 111. The corresponding t 1-t 3 settings are shown in table 1 to meet different high dynamic requirements, as shown in fig. 4, the total duration of t 1-t 3 is the exposure duration t, and is configured by the user according to the device use requirements, and the real-time value is the proportion relation between t 1-t 3. If the light intensity is weak light, t 1-t 3 are all 0, and the high dynamic reset tube 12 is connected with the power voltage in t during exposure.

TABLE 1 truth table corresponding to high dynamic time sequence

PIXEL-OUT	A	B	C	t1	t2	t3	Light intensity	MSB<0>	MSB<1>
										≤VREFL	0	0	0	2	4	6	High strength	0	0
≤VREF	0	0	1	4	4	4	Is stronger	0	1
										≤VREFH	0	1	1	6	4	2	Is weaker	1	0
≥VREFH	1	1	1	0	0	0	Weak (weak)	1	1

In the pixel reset phase, as shown in fig. 5, the voltage on the high dynamic reset tube 12 is 3.3V, and at this time, the potential barrier of the tube is low, and the photocurrent discharges through the tube; then, the high dynamic reset tube 12 is lowered from 3.3V to a voltage value of V1 for a time duration of t1, V1 defaults to 1.4V, the voltage of the high dynamic reset tube 12 is lowered, so the potential barrier of the tube is raised, at this time, since the voltage Vpd > V1-Vth across the photodiode at this time, the photocurrent integration and Vpd are lowered, when Vpd < V1-Vth, the high dynamic reset tube 12 is turned on, the photocurrent integration is stopped, the charge accumulated by PD at this time is qh (t), qh (t) reflects the maximum charge amount that can be accumulated by the photodiode when the gate voltage of the high dynamic reset tube 12 is lowered, and when the accumulated charge amount is greater than qh (t), the redundant charge forces the high dynamic reset tube 12 to be turned on, and discharges through a loop formed by VDD, the high dynamic reset tube 12, the transmission tube 11, the photodiode 10 and GND; then the gate voltage of the high dynamic reset tube 12 is reduced to a voltage value of V2 again and lasts for a time period of t2, V2 is defaulted to 1.2V, and with the reduction of the gate voltage of the high dynamic reset tube 12 again, Vpd > V2-Vth, so that the M2 tube is cut off again, and the photocurrent continues to be integrated until Vpd < V2-Vth; then the voltage is reduced to a voltage value of V3 and lasts for a time period of t3, the default of V3 is 1.0V, and the process is continuously repeated; finally, the voltage is reduced to the voltage value of V4 and kept at the voltage level until the exposure is finished, and the voltage of V4 is 0.8V by default, and the voltage is low, so that the condition that the photodiode is in an overexposure state can be avoided.

Fig. 6 shows the result of piecewise linear response of the sensor pixel caused by the change of the gate voltage of the high dynamic reset tube 12. As can be seen from the figure, when the luminance is high, the output slope becomes gentle, and the dynamic range extension is realized.

Fig. 7 shows an overall execution process, which compares the photoelectric signal with a reference through pre-integration and outputting the photoelectric signal, determines the intensity of light by using a 3D stacked chip ADC, and controls the length of the segmented integration time according to the intensity light result. And then, low-order conversion and high-order and low-order ADC data synthesis are carried out through the column-level ADC, so that the self-adaptive high-dynamic image sensor is realized.

An embodiment of the present invention provides a method for implementing an adaptive pixel-level high dynamic CMOS image sensor, including the following steps:

the pixel array 101 outputs an optoelectronic signal, and the optoelectronic signal is compared with a reference signal in a comparison unit of the pixel-level ADC circuit 103 to output a digital signal;

comparing the digital signals in a truth table register 19 according to the digital signals, judging the light intensity, outputting a corresponding high-bit digital signal to a data synthesizer 22 by the truth table register 19, determining that a corresponding control duration data is output by a time controller 18, feeding the control duration data back to a pixel array 101 by the time controller 18, and adjusting the high-dynamic reset tube 12 in real time;

the photoelectric signal is input to the negative input end of the comparator 20 to be compared with the ramp signal, when the photoelectric signal is greater than the ramp signal, the comparator 20 is turned over, the counter 21 counts for one time, and the counting result is transmitted to the data synthesizer 22;

the data synthesizer 22 synthesizes the received data and outputs the final result.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. An adaptive pixel-level high dynamic CMOS image sensor is characterized by comprising a pixel array (101), a column-level ADC readout circuit (102) and a pixel-level ADC circuit (103);

the pixel array (101) and the column-level ADC reading circuit (102) are arranged on an upper chip, the pixel-level ADC circuit (103) is arranged on a lower chip, and a 3D stacking structure is arranged between the upper chip and the lower chip;

the pixel array (101) outputs photoelectric signals, and the photoelectric signals are respectively input to a column-level ADC reading circuit (102) and a pixel-level ADC circuit (103);

the column-level ADC readout circuit (102) comprises a comparator (20), a counter (21) and a data synthesizer (22), wherein the negative end of the comparator (20) receives an optical electric signal, the positive end inputs a ramp signal, and the comparison result is transmitted to the data synthesizer (22) through the counter (21);

the pixel level ADC circuit (103) comprises a comparison unit, a control unit and a register unit, wherein the positive end of the comparison unit receives a photoelectric signal, the negative end of the comparison unit receives a reference signal, the comparison result is processed by the register unit and then is respectively transmitted to the control unit and the data synthesizer (22), the control unit generates control duration data and feeds the control duration data back to the pixel array (101), and the final result is generated in the data synthesizer (22) and is output.

2. An adaptive pixel level high dynamic CMOS image sensor as in claim 1, the pixel array (101) is characterized by comprising a global exposure control tube (10), a transmission tube (11), a high-dynamic reset tube (12), a source following tube (13), a readout control tube (14), a diode and a capacitor, wherein the drains of the global exposure control tube (10), the high-dynamic reset tube (12) and the source following tube (13) are all connected with VDD, the source of the global exposure control tube (10) is connected with the source of the transmission tube (11) and then grounded through the diode, the drain of the transmission tube (11) and the source of the high-dynamic reset tube (12) are connected to an FD point, the FD point is connected with the gate of the source following tube (13) and grounded through the capacitor, the source of the source following tube (13) is connected with the drain of the readout control tube (14), and the source of the readout control tube (14) outputs an electrical light signal.

3. An adaptive pixel level high dynamic CMOS image sensor according to claim 1, wherein the comparing unit comprises a first comparator (15), a second comparator (16) and a third comparator (17), positive input terminals of the first comparator (15), the second comparator (16) and the third comparator (17) are all photoelectric signals, and negative input terminals are respectively a reference level high VREFH, a reference level VREF and a reference level low VREFL.

4. An adaptive pixel level high dynamic CMOS image sensor according to claim 3, wherein the reference level high VREFH, the reference level VREF and the reference level low VREFL are specified as:

where V0 is the output voltage value under the pixel reset condition, and V _ full scale is the difference between the voltage value output when the pixel is saturated and the voltage value output when the pixel is reset.

5. An adaptive pixel level high dynamic CMOS image sensor as claimed in claim 1, wherein the register unit is a truth table register (19), and the light intensity is determined by comparing the output result of the comparing unit with the value in the truth table register (19).

6. The adaptive pixel level high dynamic CMOS image sensor of claim 1, wherein a copper-copper interconnect structure is used between the upper chip and the lower chip.

7. A realization method of an adaptive pixel level high dynamic CMOS image sensor is characterized by comprising the following steps:

the pixel array (101) outputs photoelectric signals, the comparison units of the pixel ADC circuit (103) receive the photoelectric signals for comparison, the photoelectric signals are respectively input to positive input ends of a first comparator (15), a second comparator (16) and a third comparator (17), negative input ends of the first comparator, the second comparator and the third comparator are respectively a reference level high VREFH, a reference level VREF and a reference level low VREFL, and digital signals are output after comparison is completed;

comparing the digital signals in a truth table register (19) according to the digital signals, judging the light intensity, outputting a corresponding high-bit digital signal to a data synthesizer (22) by the truth table register (19), determining the corresponding control duration data output by a time controller (18), feeding the control duration data back to a pixel array (101) by the time controller (18), and adjusting a high-dynamic reset tube (12) in real time;

the photoelectric signal is input to the negative input end of the comparator (20) and compared with the ramp signal, when the photoelectric signal is greater than the ramp signal, the comparator (20) is turned over, the counter (21) counts for one time, and the counting result is transmitted to the data synthesizer (22);

a data synthesizer (22) synthesizes the received data and outputs the final result.

8. The method of claim 7, wherein when the photo signal is less than VREFL, the comparing unit outputs 000; when the photoelectric signal is smaller than VREF, the comparison unit outputs 001; when the photoelectric signal is smaller than VREFH, the comparison unit outputs 011; when the photo signal is greater than VREFH, the comparing unit outputs 111.

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