CN114978238A - Echo cancellation system and echo cancellation method - Google Patents
Echo cancellation system and echo cancellation method Download PDFInfo
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Abstract
An echo cancellation system includes a data transmission circuit and an echo cancellation circuit. The data transmission circuit is used for receiving a transmission signal. The echo cancellation circuit includes a first filter. The first filter is used for generating a first filtering signal according to the transmission signal and a filter coefficient. The filter coefficients are updated according to a high frequency leakage process. The echo cancellation circuit is further configured to generate an echo cancellation signal according to the first filtered signal. The data transmission circuit is further used for generating an output signal according to a receiving signal and the echo cancellation signal.
Description
Technical Field
The embodiments described in the present application relate to an echo cancellation technology, and in particular, to an echo cancellation system and an echo cancellation method.
Background
As communication technologies have evolved, various communication systems have been developed and used in many different applications. In a communication system using Full-Duplex (Full-Duplex) technology, a pair of transmission lines will have a transmission signal and a reception signal. When the impedances of the two transmission lines are not matched or the hybrid architecture of the receiving device is not matched, the transmission signal may be introduced into the receiving signal. This can cause Echo (Echo) and can affect the signal-to-noise ratio (SNR) of the communication system.
Disclosure of Invention
Some embodiments of the present application relate to an echo cancellation system. The echo cancellation system comprises a data transmission circuit and an echo cancellation circuit. The data transmission circuit is used for receiving a transmission signal. The echo cancellation circuit includes a first filter. The first filter is used for generating a first filtering signal according to the transmission signal and a filter coefficient. The filter coefficients are updated according to a high frequency leakage process. The echo cancellation circuit is further configured to generate an echo cancellation signal according to the first filtered signal. The data transmission circuit is further used for generating an output signal according to a receiving signal and the echo cancellation signal.
Some embodiments of the present application relate to an echo cancellation method. The echo cancellation method comprises the following steps: receiving a transmission signal through a data transmission circuit; generating a first filtering signal according to the transmission signal and a filter coefficient by a first filter in an echo cancellation circuit, wherein the filter coefficient is updated according to a high-frequency leakage program; generating an echo cancellation signal according to the first filtering signal through an echo cancellation circuit; and generating an output signal according to a receiving signal and the echo cancellation signal through the data transmission circuit.
In summary, in the present application, the filter coefficients of the filter circuit in the echo cancellation circuit can be updated according to the high frequency leakage procedure. Therefore, the high frequency component can be suppressed to avoid signal drift, so that the echo cancellation system can operate normally.
Drawings
The foregoing and other objects, features, advantages and embodiments of the present application will be more readily understood from the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic diagram of an echo cancellation system according to some embodiments of the present application;
FIG. 2 is a schematic diagram of an echo cancellation system according to some embodiments of the present application;
FIG. 3 is a graph of the operation times versus the SNR of the system signals; and
fig. 4 is a flowchart of an echo cancellation method according to some embodiments of the present application.
Detailed Description
The term "coupled," as used herein, may also refer to "electrically coupled," and the term "connected" may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.
Refer to fig. 1. Fig. 1 is a schematic diagram of an echo cancellation system S1 according to some embodiments of the present application. In some embodiments, the echo cancellation system S1 is used in an Ethernet (Ethernet) system.
In some embodiments, the echo cancellation system S1 employs Full Duplex (Full-Duplex) technology. That is, the system has a pair of transmission lines, and the transmission lines have transmission signals and reception signals, respectively. For the example of fig. 1, the transmission signal of the echo cancellation system S1 is the transmission signal TX1, and the reception signal of the echo cancellation system S1 is the reception signal RXC. In some embodiments, the transmission signal TX1 may be generated by encoding a signal from a medium access control layer (MAC layer), but the application is not limited thereto.
Taking the example of fig. 1 as an example, the echo cancellation system S1 includes a data transmission circuit 100, an echo cancellation circuit 200, and an echo cancellation circuit 300. In some embodiments, the echo cancellation circuit 200 is used to generate an echo cancellation signal EC1 to cancel most of the echo in the analog end cancellation system. The echo cancellation circuit 300 is used to generate an echo cancellation signal EC2 to cancel the remaining echo at the digital end.
In particular, the data transmission circuit 100 may receive a transmission signal TX1, where the transmission signal TX1 has a first sampling frequency (e.g., 400 megahertz (MHz)). The echo cancellation circuit 200 also receives the transmission signal TX1 and performs an oversampling procedure on the transmission signal TX1 to generate the transmission signal TX2, wherein the transmission signal TX2 has a second sampling frequency (e.g., 800 mhz) greater than the first sampling frequency. The echo cancellation circuit 200 generates an echo cancellation signal EC1 according to the transmission signal TX 2. Then, the data transmission circuit 100 generates the output signal DO according to the analog signal TXC, the receiving signal RXC, the echo cancellation signal EC1 and the echo cancellation signal EC 2. By the echo cancellation signal EC1 and the echo cancellation signal EC2, the influence of the echo on the signal can be cancelled, and the signal-to-noise ratio (SNR) of the echo cancellation system S1 is further improved.
In some embodiments, the data transmission circuit 100 includes a memory 102, an over-sampling circuit 104, an shaping circuit 106, a digital-to-analog converter 108, an analog front-end processing circuit 110, an analog-to-digital conversion circuit 112, a parallel-to-serial conversion circuit 114, an adder AD1, a serial-to-parallel conversion circuit 116, a filter circuit 118, and an adder AD 2. The analog-digital conversion circuit 112 includes an analog-digital converter 1121 and an analog-digital converter 1122. The filter circuit 118 includes a filter 1181 and a filter 1182.
In some embodiments, the echo cancellation circuit 200 includes an oversampling circuit 202, a filter circuit 204, an adder AD3, a random number generation circuit 206, a filter circuit 208, an oversampling circuit 210, an shaping circuit 212, an adder AD4, and a digital-to-analog converter 214.
In operation, a transmit signal TX1 is received by memory 102. In some embodiments, the memory 102 is implemented as a register capable of executing a first-in-first-out (FIFO) process, but the application is not limited thereto. The memory 102 then transmits the transmission signal TX1 to the over-sampling circuit 104 and the over-sampling circuit 202.
The oversampling circuit 104 performs an oversampling procedure on the transmission signal TX1 to generate the transmission signal TX3, wherein the transmission signal TX3 has a third sampling frequency (e.g., 1.6 gigahertz) greater than the second sampling frequency. Then, the shaping circuit 106 generates a shaping signal SD1 according to the transmission signal TX 3. The digital-to-analog converter 108 converts the digital version of the shaped signal SD1 into an analog version of the analog signal TXC. The analog signal TXC can be processed by a transformer and then output to a network cable or other electronic components.
On the other hand, the oversampling circuit 202 performs an oversampling procedure on the transmission signal TX1 to generate a transmission signal TX 2. As previously mentioned, the transmission signal TX2 has the second sampling frequency. Then, the filter circuit 204 may perform a filtering process on the TX2 with a filtered least mean square (FxLMS) mechanism to generate the filtered signal AEC _ O. In addition, the random number generation circuit 206 may generate a random number PN. In some embodiments, the random number PN is a pseudo-noise sequence (pseudo-noise sequence), but the present application is not limited thereto. The adder AD3 combines the filtered signal AEC _ O and the random number PN to generate the operation signal CD 1. The over-sampling circuit 210 performs an over-sampling procedure on the operation signal CD1 to generate the transmission signal TX 4. The transmission signal TX4 also has a third sampling frequency. That is, the sampling frequency of the transmission signal TX4 is set to be equal to the sampling frequency of the transmission signal TX 3. The shaping circuit 212 generates a shaping signal SD2 according to the transmission signal TX 4. The adder AD4 combines the shaping signal SD2 and the shaping signal SD1 to generate the operation signal CD 2. The digital-to-analog converter 214 converts the digital operation signal CD2 into an analog echo cancellation signal EC 1.
In some embodiments, echo may be caused if the analog signal TXC is introduced into the transmission line carrying the received signal. That is, the analog front-end processing circuit 110 receives the incoming analog signal TXC. The analog front end processing circuit 110 generates a processing signal AFE _ O according to the analog signal TXC, the echo cancellation signal EC1 from the echo cancellation circuit 200, and the received signal RXC. The processing signal AFE _ O also has a third sampling frequency. The analog-to-digital conversion circuit 112 generates the digital signal D _ ODD and the digital signal D _ EVEN according to the processing signal AFE _ O. In some embodiments, the digital signal D _ ODD is generated by the adc 1121 operating according to a first sampling frequency and sampling the processing signal AFE _ O with a first phase (e.g., ODD phase), and the digital signal D _ EVEN is generated by the adc 1122 operating according to the first sampling frequency and sampling the processing signal AFE _ O with a second phase (e.g., EVEN phase). Then, the parallel-to-serial conversion circuit 114 converts the digital signal D _ ODD and the digital signal D _ EVEN in parallel into the serial signal SRD in serial.
In addition, the random number PN is subjected to an inversion procedure to generate an inverted random number-PN. The filter circuit 208 generates a filter signal FO according to the inverted random number-PN. The adder AD1 combines the filtered signal FO and the serial signal SRD in serial form to generate the operation signal CD3 in serial form. The serial-parallel conversion circuit 116 converts the operation signal CD3 in serial form into a parallel signal PD in parallel form. The filter 1181 operates according to a first sampling frequency and samples the parallel signal PD with a first phase (e.g., an odd phase) to generate the filtered signal DLF 1. The filter 1182 operates according to the first sampling frequency and samples the parallel signal PD with the second phase (e.g., even phase) to generate the filtered signal DLF 2. In some embodiments, the filters 1181 and 1182 are implemented as low-pass filters, but the application is not limited thereto. The summer AD2 combines the filtered signal DLF1, the filtered signal DLF2, and the echo cancellation signal EC2 from the echo cancellation circuit 300 to generate the output signal DO.
In some related art techniques, an echo cancellation circuit generates an echo cancellation signal based on a signal having a lower sampling frequency. In these related arts, the echo cancellation signal cannot effectively cancel the echo, and thus the signal-to-noise ratio of the communication system cannot be effectively improved.
In the present application, the echo cancellation circuit 200 generates the echo cancellation signal EC1 according to the transmission signal TX2 with a higher sampling frequency (a second sampling frequency, e.g., 800 mhz). Thus, the echo cancellation signal EC1 can more effectively cancel the echo, so that the signal-to-noise ratio of the echo cancellation system S1 can be effectively improved.
In addition, the sampling frequency of the transmission signal TX2 may be determined according to the sampling frequency of the processing signal AFE _ O output by the analog front-end processing circuit 110. In some embodiments, if the processing signal AFE _ O has the third sampling frequency, the second sampling frequency of the transmission signal TX2 output by the oversampling circuit 202 may be set to be half of the third sampling frequency or less. In this way, it is possible to avoid excessive system costs in the case where most of the echo has been cancelled. In some other embodiments, the second sampling frequency may be set equal to the third sampling frequency to eliminate more echo.
Refer to fig. 2. Fig. 2 is a schematic diagram of an echo cancellation system S2 according to some embodiments of the present application. The echo cancellation system S2 of fig. 2 is a poly-phase (poly-phase) system.
Specifically, the main differences between the echo cancellation system S2 in fig. 2 and the echo cancellation system S1 in fig. 1 are that the data transmission circuit 1000 of the echo cancellation system S2 further includes a memory 1131 and a memory 1132, and the echo cancellation circuit 2000 of the echo cancellation system S2 further includes a filter 2041 (which may be included in the filter circuit 204 in fig. 1), a filter 2042 (which may be included in the filter circuit 204 in fig. 1), a memory 207, a filter 2081 (which may be included in the filter circuit 208 in fig. 1), a filter 2082 (which may be included in the filter circuit 208 in fig. 1), a memory 216, a filter 2181, and a filter 2182. In some embodiments, the memory 1131, the memory 1132, the memory 207 and the memory 216 are implemented by registers capable of executing a first-in first-out (fifo) process, but the present application is not limited thereto.
The filter 2041 and the filter 2042 receive the TX signal TX1, wherein the filter circuit 2041 performs a filtering process on the TX signal TX1 according to a first phase (e.g., an odd phase) to output a filtered signal F1. The filter 2042 performs a filtering process on the TX1 according to the second phase (e.g., even phase) to output a filtered signal F2. How the filtering rms mechanism of the filter 2041 (or the filter 2042) is updated according to a high frequency leakage process to generate the filtered signal F1 (filtered signal F2) will be described in detail in the following paragraphs.
The random number generation circuit 206 generates a random number PN. The adder AD5 combines the filtered signal F1 and the random number PN to generate the digital signal DD 1. The shaping circuit 212 generates the shaping signal SD3 according to the digital signal DD1 and the filtered signal F2. The adder AD4 combines the shaping signal SD3 and the shaping signal SD 1. The digital-analog converter 214 generates the echo cancellation signal EC1 based on the combination of the shaping signal SD3 and the shaping signal SD 1. The analog front-end processing circuit 110 generates a processing signal AFE _ O1 according to an analog signal TXC1 corresponding to the transmission signal TX1, an echo cancellation signal EC1 and a reception signal RXC. The analog-to-digital conversion circuit 1121 samples the processing signal AFE _ O1 at a first phase (e.g., ODD phase) to generate the digital signal D _ ODD 1. Analog-to-digital conversion circuit 1122 samples the processed signal AFE _ O1 at a second phase (e.g., EVEN phase) to generate digital signal D _ EVEN 1.
On the other hand, the memory 207 outputs the inverted random number-PN to the filter 2081 and the filter 2082. The filter 2081 is coupled to the analog-to-digital converter 1131 through the adder AD 6. The filter 2082 is coupled to the analog-to-digital converter 1132 by an adder AD 7. The filter 2081, the adc 1131, and the adc 1121 correspond to a first phase (e.g., an odd phase). Filter 2082, analog-to-digital converter 1132, and analog-to-digital converter 1122 correspond to the second phase (e.g., even phase). In some embodiments, filter 2081 may be updated according to the output of adder AD6, and filter 2082 may be updated according to the output of adder AD 7.
In addition, the memory 216 transmits the transmission signal TX1 to the filter 2181 and the filter 2182. The combining circuit COM updates the filtering root mean square mechanisms of the filter 2041 and the filter 2042 through the updating circuit 220 according to the output of the adc 1131, the output of the adc 1132, the output of the filter 2181 and the output of the filter 2182.
As mentioned previously, the echo cancellation system S2 of fig. 2 employs a multi-phase system. That is, the echo cancellation system S2 separately processes signals of different phases. In this case, all components can operate at a lower frequency to achieve power saving. In addition, since the echo cancellation system S2 adopts a multi-phase system, the flexibility of circuit design is greater. For example, it will be more convenient to remove the path of one phase (e.g., odd phase or even phase) in the future.
Details regarding how the filtering rms mechanism of the filter 2041 (or the filter 2042) is updated according to the hf leakage procedure to generate the filtered signal F1 (filtered signal F2) will be described in the following paragraphs in conjunction with the echo cancellation system S2 of fig. 2. The filter 2041 is taken as an example, and the filter 2042 has similar operations, so the description is omitted.
The filter 2041 generates a filtered signal F1 according to the transmission signal TX1 and the filter coefficients of the filter 2041. The filter coefficients of the filter 2041 may be an array of coefficients (vector) comprising multiple levels (taps), and this array of coefficients may correspond to a particular shape of waveform. While filter 2041 may perform convolution operations on transmit signal TX1 according to its filter coefficients to generate filtered signal F1. In some embodiments, the filter coefficients of filter 2041 comprise 24 orders. The filter coefficients of the representative filter 2041 are a single-row array comprising 24 coefficients. However, the present application is not limited to this order, and other suitable orders are within the scope of the present application. When the order is less, the system has the advantage of saving power.
As previously described, the filter coefficients of filter 2041 may be updated according to a high frequency leakage process. In some embodiments, the operation circuit 222 coupled to the filter 2041 may obtain the coefficient accumulation array by the following equation (1):
Grad ACC ＝Grad ACC -M × ER × TX1 … formula (1)
Wherein Grad ACC For the coefficient accumulation array and the initial value of each order is 0, M represents the intensity value and can be adjusted according to the system design (e.g., if the accumulation rate or the update rate is larger, M can be designed to be larger), ER represents the error (which may represent the echo component that is not completely eliminated) reflected by the output of the memory 1131 (e.g., the operation circuit 222 can be coupled to the memory 1131 to receive the signal related to the error), and the transmission signal TX1 is a data array.
The coefficient accumulation array Grad according to the above equation (1) ACC Will continue to accumulate until the coefficient accumulation array Grad ACC When the first order in (1) is accumulated to more than one Least Significant Bit (LSB), the coefficient accumulation array Grad is accumulated ACC Subtract a least significant digit array (e.g., lsbuprate in equation (3) below) and continue accumulating again. The least significant bit array (i.e., lsbuprate) may be temporarily stored in the refresh circuit 220 coupled to the operation circuit 222, and the refresh circuit 220 may be implemented by a buffer, for example.
However, if there is a high frequency component in the system, the high frequency array of filter coefficients may be { +1, -1, +1 … … -1}, for example. The operation circuit 222 can obtain the high frequency component parameter by the following equation (2):
OmE ═ Σ (AECodd) - (aecaven) … equation (2)
Wherein AECodd represents the odd-order coefficient of the filter coefficients, aecaven represents the even-order coefficient of the filter coefficients, and OmE is the high frequency component parameter and is used to reflect the presence of the high frequency component. From the above equation (2), the high frequency component parameter OmE is the sum of the odd-order coefficients of the filter coefficients minus the sum of the even-order coefficients of the filter coefficients. The higher the value of the high frequency component parameter OmE, the higher the high frequency component.
The operation circuit 222 receives the filter coefficients of the filter 2041, and the update circuit 220 is capable of updating the filter coefficients of the filter 2041 in cooperation with the operation circuit 222 according to the current filter coefficients, the least significant digit array (temporarily stored in the update circuit 220), and a high frequency leakage array, as shown in the following formula (3):
AEC ═ AEC + LSBupdate + H _ LEAK … formula (3)
Where AEC to the left of the equal sign represents updated filter coefficients of filter 2041, AEC to the right of the equal sign represents current filter coefficients of filter 2041, and lsbuprate represents the cumulative coefficient array Grad mentioned in the preceding paragraph ACC The least significant bit array subtracted in (1), and H _ LEAK represents the high frequency leakage array.
The operation circuit 222 can obtain the high frequency leakage array H _ LEAK according to the following equation (4):
h _ LEAK ═ EN × AEC _ LSB × AEC' × sign { OmE } × C … formula (4)
Where EN represents an enabling value, AEC _ LSB represents the least significant bit, AEC' is the leakage array of filter 2041 and may be the inverse of the high frequency array of filter coefficients (e.g., { -1, +1, -1 … … +1} by multiplying the high frequency array of filter coefficients by-1), sign { OmE } represents the sign of high frequency component parameter OmE, and C represents a condition value. When the high frequency component parameter OmE is not zero, it represents that there is a high frequency component in the system, so the value of the enabling value EN is set to 1, so that the high frequency leakage array H _ LEAK is enabled. On the contrary, when the high frequency component parameter OmE is zero, it represents that the high frequency component is not present, so the value of the enable value EN is set to 0, and the high frequency leakage array H _ LEAK cannot be enabled. In some embodiments, the enabling value EN is set by another unit (e.g., a control unit of the echo cancellation system S2 or a control unit of the whole transceiver (transceiver)) coupled to the filter 2041 to control whether the filter coefficients of the filter 2041 are updated according to the high frequency leakage array H _ LEAK.
In addition, when the condition (abs { OmE }. gtoreq | nTAP × AEC _ LSB | is satisfied, the condition value C is set to 1, where abs { OmE } is the absolute value of the high-frequency component parameter OmE, and nTAP is the total order of the filter coefficients. In other words, when the absolute value of the high frequency component parameter OmE is greater than or equal to the absolute value of the product of the total order number nbap of the filter coefficients and the least significant bit AEC _ LSB (i.e., the condition value C is 1), the high frequency leakage array H _ LEAK output by equation (4) is equal to the product of the performance value EN, the least significant bit AEC _ LSB, the leakage array AEC', and the sign of the high frequency component parameter OmE. The high frequency leakage array H _ LEAK may be used to cancel out high frequency components (the high frequency array mentioned above) in the filter coefficients AEC of the filter 2041 to remove high frequency components in the system and avoid filter coefficients from drifting.
Conversely, when the above condition is not satisfied, the condition value C is set to 0. In other words, when the absolute value of the high frequency component parameter OmE is smaller than the absolute value of the product of the total order number nTAP of the filter coefficients and the least significant bit AEC _ LSB (i.e., the condition value C is 0), the high frequency leakage array H _ LEAK output by equation (4) is equal to zero.
In some embodiments, the high frequency leakage array H _ LEAK may be updated according to an update period. The update period may have a plurality of candidate values, and an appropriate value may be selected from the candidate values according to system requirements. When the refresh period is set shorter, the speed of leaking the high frequency component can be increased.
In addition, in some embodiments, the above-mentioned processing procedure may correspond to at least one level in the array. For example, the first update may be to one order of the array of filter coefficients, the second update to another order of the array of filter coefficients, and so on. In some embodiments, multiple orders in the array of filter coefficients may be updated in parallel (synchronously).
In addition, in some embodiments, the operation circuit 222 and the update circuit 220 may be integrated into a single circuit.
Based on the above, when there is a high frequency offset in the system (i.e. the high frequency component parameter OmE is not zero), the filter coefficient of the filter 2041 in the echo cancellation circuit is updated according to the high frequency leakage procedure (for example, the above equation (3)). Then, the filter 2041 performs convolution operation on the updated filter coefficients and the transmission signal TX1 to generate a filtered signal F1, and further generates an updated echo cancellation signal EC 1. In this way, the high frequency components in the filter coefficients can be continuously removed to avoid the filter coefficients from drifting, so that the system can operate normally and the snr of the echo cancellation system S2 can be maintained.
Refer to fig. 3. FIG. 3 is a graph of the operation times versus the SNR of the system. For the example of fig. 3, when the high frequency offset is not present (i.e. the high frequency component parameter OmE is zero) and the high frequency leakage procedure is not performed, the snr of the system is high. However, when the high frequency offset exists (i.e., the high frequency component parameter OmE is not zero) but the high frequency leakage procedure is not performed, the signal-to-noise ratio of the system will decrease with the number of operations. The snr of the system is maintained high when the high frequency offset exists (i.e., the high frequency component parameter OmE is not zero) and the high frequency leakage procedure is performed.
Refer to fig. 4. Fig. 4 is a flowchart of an echo cancellation method 400 according to some embodiments of the present application. The echo cancellation method 400 includes operations S410, S420, S430, and S440. For ease of understanding, the echo cancellation method 400 will be described in conjunction with the echo cancellation system S2 of fig. 2.
In operation S410, a transmission signal TX1 is received by the data transmission circuit 100. In operation S420, a filter signal F1 is generated by the filter 2041 in the echo cancellation circuit 200 according to the transmission signal TX1 and the filter coefficients. The filter coefficients of the filter 2041 are updated according to the high frequency leakage procedure (e.g., the above equation (3)) to suppress the high frequency components. In operation S430, an echo cancellation signal EC1 is generated by the echo cancellation circuit 200 according to the filtered signal F1. In operation S440, an output signal DO is generated by the data transmission circuit 100 according to the received signal RXC and the echo cancellation signal EC 1.
In summary, in the present application, the filter coefficients of the filter circuit in the echo cancellation circuit can be updated according to the high frequency leakage procedure. Therefore, the high frequency component can be suppressed to avoid signal drift, so that the echo cancellation system can operate normally.
Various functional components and modules have been disclosed herein. It will be apparent to those of ordinary skill in the art that functional blocks may be implemented by circuitry (whether dedicated circuitry or general purpose circuitry operating under control of one or more processors and coded instructions), which generally comprises transistors or other circuit elements that control the operation of the electrical circuits in accordance with the functions and operations described herein. It is further understood that the specific structure and interconnections of circuit elements may be generally determined by a compiler, such as a Register Transfer Language (RTL) compiler. The buffer delivery language compiler operates on scripts (scripts) that are fairly similar to assembly language code (assembly language code) and compiles the scripts into a form for layout or fabrication of the final circuit.
Although the present application has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the present application, and therefore the scope of the present application is to be determined by the appended claims.
[ notation ] to show
100,1000 data transmission circuit
102,1131,1132,207,216 internal memory
104 oversampling circuit
106 shaping circuit
108 digital-to-analog converter
110 analog front end processing circuit
112 analog-to-digital conversion circuit
1121,1122 analog-to-digital converter
114 parallel serial conversion circuit
116 serial parallel conversion circuit
118 filter circuit
1181,1182 Filter
200,300,2000 echo cancellation circuit
202 oversampling circuit
204,208,2181,2182 Filter circuit
206 random number generating circuit
2041,2042,2081,2082 Filter
210 oversampling circuit
212 shaping circuit
214 digital-to-analog converter
220 refresh circuit
222 arithmetic circuit
S1, S2 echo cancellation system
AD1, AD2, AD3, AD4, AD5, AD6, AD7 adder
TX1, TX2, TX3 and TX4
Parallel signal of PD
SRD sequence signal
RXC receiving signal
SD1, SD2, SD3 shaping signals
TXC, TXC1 analog signals
EC1, EC2 echo cancellation signals
DO output signal
AEC _ O, FO, DLF1, DLF2, F1, F2 filtered signals
PN random number
-PN inverse random number
CD1, CD2, CD3 operational signals
AFE _ O, AFE _ O1 processing signals
D _ ODD, D _ EVEN, DD1, D _ ODD1, D _ EVEN1 digital signals
COM combining circuit
Operations S410, S420, S430, S440
Claims (10)
1. An echo cancellation system, comprising:
a data transmission circuit for receiving a transmission signal; and
an echo cancellation circuit, including a first filter, wherein the first filter is used to generate a first filtering signal according to the transmission signal and a filter coefficient, wherein the filter coefficient is updated according to a high frequency leakage procedure, wherein the echo cancellation circuit is further used to generate an echo cancellation signal according to the first filtering signal,
the data transmission circuit is further used for generating an output signal according to a receiving signal and the echo cancellation signal.
2. The echo cancellation system according to claim 1, wherein said first filter performs a convolution operation according to said transmission data and said filter coefficients to generate said first filtered signal.
3. The echo cancellation system according to claim 1, wherein the filter coefficients are updated based on a current filter coefficient, a least significant digit array, and a high frequency leakage digit array.
4. The echo cancellation system according to claim 3, wherein a coefficient accumulation array accumulates according to an error value and a data array corresponding to the transmission signal, wherein the coefficient accumulation array subtracts the least significant bit array when a first order accumulation in the coefficient accumulation array exceeds a least significant bit.
5. The echo cancellation system according to claim 3, wherein the filter coefficients include coefficients having a plurality of orders, wherein the high frequency leakage array is equal to a product of a total order corresponding to the order of the filter coefficients and a sign of a least significant bit when an absolute value of a high frequency component parameter is greater than or equal to an absolute value of a product of the least significant bit, a leakage array of the filter coefficients, and the sign of the high frequency component parameter.
6. The echo cancellation system according to claim 5, wherein the high frequency component parameter is a sum of a plurality of odd-numbered orders of the orders minus a sum of a plurality of even-numbered orders of the orders.
7. The echo cancellation system according to claim 5, wherein said high frequency leakage array is equal to zero when said absolute value of said high frequency component parameter is less than said absolute value of a product of said total order of said filter coefficients and said least significant bit.
8. The echo cancellation system according to claim 3, wherein the high frequency leakage array is updated according to an update period, and the update period has a plurality of candidate values, wherein a decrease in the period length of the update period correspondingly increases the update speed of the high frequency leakage program.
9. The echo cancellation system according to claim 1, wherein the echo cancellation circuit further comprises: a second filter for generating a second filtered signal according to the transmission signal;
an adder for generating a digital signal according to the first filtered signal and a random number;
the shaping circuit is used for generating a first shaping signal according to the digital signal and the second filtering signal; and
a digital-to-analog converter for generating the echo cancellation signal according to the first shaping signal and a second shaping signal corresponding to the transmission signal.
10. An echo cancellation method, comprising:
receiving a transmission signal through a data transmission circuit;
generating a first filtering signal by a first filter in an echo cancellation circuit according to the transmission signal and a filter coefficient, wherein the filter coefficient is updated according to a high-frequency leakage program;
generating an echo cancellation signal according to the first filtering signal through the echo cancellation circuit; and
and generating an output signal according to a receiving signal and the echo cancellation signal through the data transmission circuit.
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| CN103179296A (en) * | 2011-12-26 | 2013-06-26 | 中兴通讯股份有限公司 | Echo canceller and echo cancellation method |
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| JPH05152999A (en) * | 1991-11-29 | 1993-06-18 | Nec Corp | Echo suppressing device |
| US6826279B1 (en) * | 2000-05-25 | 2004-11-30 | 3Com Corporation | Base band echo cancellation using laguerre echo estimation |
| CN1541456A (en) * | 2001-07-11 | 2004-10-27 | ������������ʽ���� | Multi-channel echo cancel method, multi-channel sound transfer method, stereo echo canceller, stereo sound transfer appts. and transfer function calculation appts. |
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