CN113746500B - Echo cancellation system and echo cancellation method - Google Patents
Echo cancellation system and echo cancellation method Download PDFInfo
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- CN113746500B CN113746500B CN202010466208.8A CN202010466208A CN113746500B CN 113746500 B CN113746500 B CN 113746500B CN 202010466208 A CN202010466208 A CN 202010466208A CN 113746500 B CN113746500 B CN 113746500B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/20—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other
- H04B3/23—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
An echo cancellation system comprises a data transmission circuit and an echo cancellation circuit. The data transmission circuit is used for receiving the first transmission signal. The first transmission signal has a first sampling frequency. The echo cancellation circuit is used for generating a second transmission signal according to the first transmission signal. The second transmission signal has a second sampling frequency. The second sampling frequency is greater than the first sampling frequency. The echo cancellation circuit is also used for generating an echo cancellation signal according to the second transmission signal. The data transmission circuit is also used for generating an output signal according to the received signal and the echo cancellation signal.
Description
Technical Field
The embodiments described in this disclosure relate to a communication technology, and more particularly, to an echo cancellation system (echo cancelling system) and an echo cancellation method.
Background
As communication technology has evolved, various communication systems have been developed and applied in many different applications. In a communication system employing Full-Duplex technology, there are a transmission signal and a reception signal on a pair of transmission lines. When the impedances of the two transmission lines are not matched or the hybrid architecture of the receiving device is not matched, the transmission signal may be introduced into the received signal. This can cause Echo (Echo) and can affect the signal-to-noise ratio (SNR) of the communication system.
Disclosure of Invention
Some embodiments of the present disclosure relate to an echo cancellation system. The echo cancellation system comprises a data transmission circuit and an echo cancellation circuit. The data transmission circuit is used for receiving the first transmission signal. The first transmission signal has a first sampling frequency. The echo cancellation circuit is used for generating a second transmission signal according to the first transmission signal. The second transmission signal has a second sampling frequency. The second sampling frequency is greater than the first sampling frequency. The echo cancellation circuit is also used for generating an echo cancellation signal according to the second transmission signal. The data transmission circuit is also used for generating an output signal according to the received signal and the echo cancellation signal.
Some embodiments of the present disclosure relate to an echo cancellation system. The echo cancellation system comprises a data transmission circuit and an echo cancellation circuit. The data transmission circuit is used for receiving the first transmission signal. The echo cancellation circuit comprises a first filter, a second filter and a digital-to-analog converter. The first filter is used for generating a first filtering signal according to the first transmission signal. The first filtered signal is combined with a random number to form a first digital signal. The second filter is used for generating a second filtering signal according to the first transmission signal. The digital-to-analog converter is used for generating an echo cancellation signal based on the first transmission signal and a shaping signal corresponding to the first digital signal and the second filtering signal. The data transmission circuit is also used for generating an output signal according to the received signal and the echo cancellation signal.
Some embodiments of the present disclosure relate to an echo cancellation method. The echo cancellation method comprises the following steps: receiving a first transmission signal through a data transmission circuit, wherein the first transmission signal has a first sampling frequency; generating a second transmission signal according to the first transmission signal by the echo cancellation circuit, wherein the second transmission signal has a second sampling frequency, and the second sampling frequency is greater than the first sampling frequency; generating an echo cancellation signal according to the second transmission signal through an echo cancellation circuit; and generating an output signal according to the received signal and the echo cancellation signal by the data transmission circuit.
In summary, in the echo cancellation system and the echo cancellation method of the present disclosure, the echo cancellation circuit generates the echo cancellation signal according to the signal having the higher sampling frequency. In this way more noise will be removed to improve the signal to noise ratio of the echo cancellation system.
Drawings
The foregoing and other objects, features, advantages and embodiments of the present disclosure will be apparent from the following description in which:
fig. 1 is a schematic diagram of an echo cancellation system according to some embodiments of the present disclosure;
fig. 2 is a schematic diagram of an echo cancellation system according to some embodiments of the present disclosure; and
fig. 3 is a flow chart of an echo cancellation method drawn according to some embodiments of the present disclosure.
Detailed Description
The term "coupled," as used herein, may also refer to "electrically coupled," and the term "connected" may also refer to "electrically connected. "coupled" and "connected" may also mean that two or more elements co-operate or interact with each other.
Reference is made to fig. 1. Fig. 1 is a schematic diagram of an echo cancellation system S1 drawn according to some embodiments of the present disclosure. In some embodiments, the echo cancellation system S1 is applied to an Ethernet (Ethernet) system.
In some embodiments, the echo cancellation system S1 employs full duplex technology. That is, there is a pair of transmission lines in the system, and the two transmission lines have a transmission signal and a reception signal, respectively. For example, in fig. 1, the transmission signal of the echo cancellation system S1 is the transmission signal TX1. The received signal of the echo cancellation system S1 is the received signal RXC. In some embodiments, the transmission signal TX1 may be generated by encoding a signal from a medium access control layer (MAC layer), but the disclosure is not limited thereto.
For example, in fig. 1, the echo cancellation system S1 includes a data transmission circuit 100, an echo cancellation circuit 200, and an echo cancellation circuit 300. In some embodiments, the echo cancellation circuit 200 is configured to generate the echo cancellation signal EC1 to cancel a majority of the echo in the analog-side cancellation system. The echo cancellation circuit 300 is configured to generate an echo cancellation signal EC2 to cancel the remaining echo at the digital end.
Specifically, the data transmission circuit 100 receives a transmission signal TX1, wherein the transmission signal TX1 has a first sampling frequency (e.g., 400 megahertz (MHz)). The echo cancellation circuit 200 receives the transmission signal TX1 and performs an over-sampling (oversampling) procedure on the transmission signal TX1 to generate a transmission signal TX2, wherein the transmission signal TX2 has a second sampling frequency (e.g., 800 megahertz) that is greater than the first sampling frequency. The echo cancellation circuit 200 generates an echo cancellation signal EC1 according to the transmission signal TX2. Then, the data transmission circuit 100 generates the output signal DO according to the analog signal TXC, the receiving signal RXC, the echo cancellation signal EC1 and the echo cancellation signal EC 2. The influence of the echo on the signal can be counteracted by the echo counteraction signal EC1 and the echo counteraction signal EC2, so that the signal-to-noise ratio of the echo counteraction system S1 is improved.
In some embodiments, the data transmission circuit 100 includes a memory 102, an oversampling circuit 104, a shaping circuit 106, a digital-to-analog converter 108, an analog front end processing circuit 110, an analog-to-digital conversion circuit 112, a parallel-to-serial conversion circuit 114, an adder AD1, a serial-to-parallel conversion circuit 116, a filter circuit 118, and an adder AD2. The analog-to-digital conversion circuit 112 includes an analog-to-digital converter 1121 and an analog-to-digital converter 1122. The filter circuit 118 includes a filter 1181 and a filter 1182.
In some embodiments, the echo cancellation circuit 200 includes an over-sampling circuit 202, a filtering circuit 204, an adder AD3, a random number generation circuit 206, a filtering circuit 208, an over-sampling circuit 210, a shaping circuit 212, an adder AD4, and a digital-to-analog converter 214.
In operation, the memory 102 receives the transmission signal TX1. In some embodiments, the memory 102 is implemented with registers capable of executing a first-in-first-out (FIFO) program, but the disclosure is not limited thereto. The memory 102 then passes the transmission signal TX1 to the over-sampling circuit 104 and the over-sampling circuit 202.
The over-sampling circuit 104 performs an over-sampling procedure on the transmission signal TX1 to generate a transmission signal TX3, wherein the transmission signal TX3 has a third sampling frequency (e.g., 1.6 gigahertz) that is greater than the second sampling frequency. Then, the shaping circuit 106 generates the shaping signal SD1 according to the transmission signal TX 3. Digital-to-analog converter 108 converts the shaped signal SD1 in digital form into an analog signal TXC in analog form. The analog signal TXC may be processed by a transformer and output to a network cable or other electronic component.
On the other hand, the over-sampling circuit 202 performs an over-sampling procedure on the transmission signal TX1 to generate a transmission signal TX2. As described above, the transmission signal TX2 has the second sampling frequency. The filtering circuit 204 may then perform a filtering process on the transmission signal TX2 in conjunction with a filtered least mean square (filtered least mean squared, fxLMS) scheme to generate a filtered signal aec_o. The random number generation circuit 206 generates a random number PN. In some embodiments, the random number PN is a pseudo-noise sequence (pseudo-noise sequence), but the disclosure is not limited thereto. The adder AD3 combines the filtered signal aec_o and the random number PN to generate the operation signal CD1. The over-sampling circuit 210 performs an over-sampling procedure on the operation signal CD1 to generate the transmission signal TX4. The transmission signal TX4 also has a third sampling frequency. That is, the sampling frequency of the transmission signal TX4 is set to be equal to the sampling frequency of the transmission signal TX 3. Shaping circuit 212 generates shaping signal SD2 according to transmission signal TX4. Adder AD4 combines shaped signal SD2 and shaped signal SD1 to generate operation signal CD2. The digital-to-analog converter 214 converts the digital form of the operation signal CD2 into an analog form of the echo cancellation signal EC1.
In some embodiments, if the analog signal TXC is introduced into the receiving transmission line, an echo will be created. That is, analog front end processing circuit 110 receives analog signal TXC. The analog front-end processing circuit 110 generates a processing signal afe_o according to the analog signal TXC, the echo cancellation signal EC1 from the echo cancellation circuit 200, and the receiving signal RXC. The processing signal afe_o also has a third sampling frequency. The analog-to-digital conversion circuit 112 generates a digital signal d_odd and a digital signal d_even according to the processing signal afe_o. In some embodiments, the digital signal D_ODD is generated by the analog-to-digital converter 1121 operating at a first sampling frequency and sampling the processing signal AFE_O at a first phase (e.g., ODD phase), and the digital signal D_EVEN is generated by the analog-to-digital converter 1122 operating at a first sampling frequency and sampling the processing signal AFE_O at a second phase (e.g., EVEN phase). Next, the parallel-serial conversion circuit 114 converts the digital signal d_odd and the digital signal d_even in parallel form into a serial signal SRD in serial form.
In addition, the random number PN is subjected to an inversion process to generate an inverted random number-PN. The filter circuit 208 generates a filtered signal FO according to the inverse random number-PN. Adder AD1 combines filtered signal FO and serial signal SRD in serial form to generate operation signal CD3 in serial form. The serial-parallel conversion circuit 116 converts the operation signal CD3 in serial form into the parallel signal PD in parallel form. The filter 1181 operates according to the first sampling frequency and samples the parallel signal PD with a first phase (e.g., an odd phase) to generate a filtered signal DLF1. The filter 1182 operates according to the first sampling frequency and samples the parallel signal PD with a second phase (e.g., an even phase) to generate the filtered signal DLF2. In some embodiments, the filter 1181 and the filter 1182 are implemented as low-pass filters, but the disclosure is not limited thereto. Adder AD2 combines filtered signal DLF1, filtered signal DLF2 and echo cancellation signal EC2 to generate output signal DO.
In some embodiments, the filtered least mean square mechanism of the filtering circuit 204 is updated based on the transmission signal TX2, the serial signal SRD (which may reflect the error) in serial form, and the filtering circuit 208 (e.g., the filter coefficient), so that the echo cancellation circuit 200 generates the echo cancellation signal EC1 capable of more effectively canceling the echo to improve the signal-to-noise ratio of the echo cancellation system S1.
In some related art, the echo cancellation circuit generates an echo cancellation signal according to a signal having a lower sampling frequency. In these related art techniques, the echo cancellation signal cannot effectively cancel the echo, and thus the signal-to-noise ratio of the communication system cannot be effectively improved.
In the present disclosure, the echo cancellation circuit 200 generates the echo cancellation signal EC1 according to the transmission signal TX2 having a higher sampling frequency (a second sampling frequency, for example, 800 mhz). In this way, the echo cancellation signal EC1 can more effectively cancel the echo, so that the signal-to-noise ratio of the echo cancellation system S1 is effectively improved.
In addition, the sampling frequency of the transmission signal TX2 can be determined according to the sampling frequency of the processing signal afe_o outputted from the analog front end processing circuit 110. In some embodiments, if the processing signal afe_o has the third sampling frequency, the second sampling frequency of the transmission signal TX2 output by the over-sampling circuit 202 may be set to be half or less than the third sampling frequency. In this way, excessive system costs can be avoided in case a large part of the echo has been counteracted. In some other embodiments, the second sampling frequency may be set equal to the third sampling frequency to cancel more echo.
Reference is made to fig. 2. Fig. 2 is a schematic diagram of an echo cancellation system S2 drawn according to some embodiments of the present disclosure. The echo cancellation system S2 of fig. 2 employs a polyphase (poly-phase) system.
Specifically, the main difference between the echo cancellation system S2 of fig. 2 and the echo cancellation system S1 of fig. 1 is that the data transmission circuit 1000 of the echo cancellation system S2 includes a memory 1131 and a memory 1132. The echo cancellation circuit 2000 of the echo cancellation system S2 comprises a filter circuit 2041 (which may be included in the filter circuit 204 of fig. 1), a filter circuit 2042 (which may be included in the filter circuit 204 of fig. 1), a memory 207, a filter circuit 2081 (which may be included in the filter circuit 208 of fig. 1), a filter circuit 2082 (which may be included in the filter circuit 208 of fig. 1), a memory 216, a filter 2181, and a filter 2182. In some embodiments, memory 1131, memory 1132, memory 207, and memory 216 are implemented with registers that are capable of executing first-in-first-out programs, but the disclosure is not limited thereto.
The filter circuit 2041 and the filter circuit 2042 receive the transmission signal TX1, wherein the filter circuit 2041 performs a filtering process on the transmission signal TX1 according to a first phase (e.g., an odd phase) to output a filtered signal F1. The filter circuit 2042 performs a filtering process on the transmission signal TX1 according to a second phase (e.g., an even phase) to output a filtered signal F2. The random number generation circuit 206 generates a random number PN. Adder AD5 combines filtered signal F1 with random number PN to generate digital signal DD1. The shaping circuit 212 generates a shaping signal SD3 according to the digital signal DD1 and the filtered signal F2. The digital-to-analog converter 214 generates the echo cancellation signal EC1 based on a combination of the shaping signal SD3 and the transmission signal TX1. The analog front-end processing circuit 110 generates a processing signal afe_o1 according to an analog signal TXC1 corresponding to the transmission signal TX1, an echo cancellation signal EC1, and a reception signal RXC. The analog-to-digital conversion circuit 1121 samples the processed signal afe_o1 with a first phase (e.g., an ODD phase) to generate a digital signal d_odd1. The analog-to-digital conversion circuit 1122 samples the processed signal afe_o1 with a second phase (e.g., an EVEN phase) to generate a digital signal d_even1.
On the other hand, the memory 207 outputs the inverted random number-PN to the filter 2081 and the filter 2082. The filter 2081 is coupled to the analog-to-digital converter 1131 through an adder AD 6. The filter 2082 is coupled to the analog-to-digital converter 1132 through an adder AD 7. The filter 2081, the analog-to-digital converter 1131, and the analog-to-digital converter 1121 correspond to a first phase (e.g., an odd phase). The filter 2082, the analog-to-digital converter 1132, and the analog-to-digital converter 1122 correspond to a second phase (e.g., an even phase). In some embodiments, filter 2081 may be updated according to the output of adder AD6, and filter 2082 may be updated according to the output of adder AD 7.
In addition, the memory 216 transmits the transmission signal TX1 to the filter circuit 2181 and the filter circuit 2182. The output of the filter circuit 2181 and the output of the filter circuit 2182 are changed according to the filter coefficients of the filter circuits 2081 and 2082, respectively (e.g., the path of the signal that can be coupled to the filter circuit 204 through the filter circuit 208 in fig. 1). The combining circuit COM updates the filtered least mean square mechanism of the filter circuit 2041 and the filter circuit 2042 by the updating circuit 220 according to the output of the analog-to-digital converter 1131, the output of the analog-to-digital converter 1132, the output of the filter circuit 2181, and the output of the filter circuit 2182.
As described above, the echo cancellation system S2 of fig. 2 employs a polyphase system. That is, the echo cancellation system S2 processes signals of different phases separately. In this case, all the devices can be operated at a lower frequency to achieve the power saving effect. In addition, since the echo cancellation system S2 adopts a multiphase system, the flexibility of the circuit design is greater. For example, it will be more convenient in the future to remove paths of one of the phases (e.g., the odd phase or the even phase).
Reference is made to fig. 3. Fig. 3 is a flow chart of an echo cancellation method 3000 drawn according to some embodiments of the present disclosure. The echo cancellation method 3000 includes operations S310, S320, S330, and S340.
In some embodiments, the echo cancellation method 3000 is applied to the echo cancellation system S1 of fig. 1, but the disclosure is not limited thereto. For ease of understanding, the echo cancellation method 3000 will be discussed in connection with the echo cancellation system S1 of fig. 1.
In operation S310, a transmission signal TX1 is received by the data transmission circuit 100, wherein the transmission signal TX1 has a first sampling frequency.
In operation S320, the echo cancellation circuit 200 generates a transmission signal TX2 according to the transmission signal TX1, wherein the transmission signal TX2 has a second sampling frequency, and the second sampling frequency is greater than the first sampling frequency. In some embodiments, the over-sampling procedure is performed on the transmission signal TX1 by the over-sampling circuit 202 to generate the transmission signal TX2. The sampling frequency of the transmission signal TX2 may be more than twice the sampling frequency of the transmission signal TX1.
In operation S330, an echo cancellation signal EC1 is generated by the echo cancellation circuit 200 according to the transmission signal TX2. Since the transmission signal TX2 has a higher second sampling frequency, the echo cancellation circuit 200 generates the echo cancellation signal EC1 that more effectively cancels the echo.
In operation S340, the output signal DO is generated by the data transmission circuit 100 according to the received signal RXC and the echo cancellation signal EC1. In some embodiments, the echo cancellation signal EC1 may cancel a majority of the echo in the system at the analog end to improve the signal-to-noise ratio of the echo cancellation system S1.
In the present disclosure, echoes in the system can be more effectively eliminated. Accordingly, the signal-to-noise ratio of the system can be improved. In addition, the accuracy of the number of significant digits (Effective number of bits, ENOB) of the system can also be reduced to save costs. Furthermore, the signal jitter (jitter) requirement can be reduced, and the operation can be performed in any section.
In summary, in the echo cancellation system and the echo cancellation method of the present disclosure, the echo cancellation circuit generates the echo cancellation signal according to the signal having the higher sampling frequency. In this way more noise will be removed to improve the signal to noise ratio of the echo cancellation system.
Various functional elements and blocks are disclosed herein. It will be apparent to one of ordinary skill in the art that functional blocks may be implemented by circuits, whether special purpose circuits or general purpose circuits operating under the control of one or more processors and encoded instructions, that generally include transistors or other circuit elements to control the operation of an electrical circuit in accordance with the functions and operations described herein. It will further be appreciated that the specific structure and interconnection of circuit elements in general may be determined by a compiler (e.g., a register transfer language (Register Transfer Language, RTL) compiler). The register transfer language compiler operates on a script (script) that is quite similar to the assembly language code (assembly language code), compiling the script into a form for layout or making the final circuit.
While the present disclosure has been disclosed in terms of embodiments, it is not intended to limit the disclosure to such embodiments, and various changes and modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the disclosure, and therefore the scope of the disclosure should be considered as limited only by the appended claims.
Description of the reference numerals
100,1000 data transmission circuit
102,1131,1132,207,216 memory
104 over-sampling circuit
106 shaping circuit
108 digital-to-analog converter
110 analog front-end processing circuit
112 analog-to-digital conversion circuit
1121,1122 analog to digital converter
114 parallel-serial conversion circuit
116 serial-parallel conversion circuit
118 Filter Circuit
1181,1182 Filter
200,300,2000 echo cancellation circuit
202 over-sampling circuit
204,208,2181,2182 Filter Circuit
206 random number generating circuit
2041,2042,2081,2082 Filter
210 over-sampling circuit
212 shaping circuit
214 digital-to-analog converter
220 update circuit
S1, S2 echo cancellation system
AD1, AD2, AD3, AD4, AD5, AD6, AD7, adder
TX1, TX2, TX3, TX4: transmission signal
PD parallel signals
SRD serial signal
RXC receiving signal
SD1, SD2, SD3 shaping signals
TXC, TXC1 analog signals
Ec1, EC2 echo cancellation signal
DO: output Signal
AEC_O, FO, DLF1, DLF2, F1, F2: filtered signal
PN random number
-PN-inverse random number
CD1, CD2, CD3 arithmetic signal
AFE_O, AFE_O1 processing signals
D_ODD, D_EVEN, DD1, D_ODD1, D_EVEN1 digital signal
COM-combining circuit
3000 echo cancellation method
S310, S320, S330, S340 operation
Claims (5)
1. An echo cancellation system comprising:
a data transmission circuit for receiving a first transmission signal, wherein the first transmission signal has a first sampling frequency; and
the echo cancellation circuit is used for generating a second transmission signal according to the first transmission signal, wherein the second transmission signal has a second sampling frequency, the second sampling frequency is larger than the first sampling frequency, the echo cancellation circuit is also used for generating an echo cancellation signal according to the second transmission signal, and the data transmission circuit is also used for generating an output signal according to a receiving signal and the echo cancellation signal;
wherein the data transmission circuit comprises:
a first over-sampling circuit for generating a third transmission signal according to the first transmission signal, wherein the third transmission signal has a third sampling frequency, and the third sampling frequency is greater than the second sampling frequency;
the first shaping circuit is used for generating a first shaping signal according to the third transmission signal;
the first digital-to-analog converter is used for generating an analog signal according to the first shaping signal;
an analog front-end processing circuit for generating a processing signal according to the analog signal, the echo cancellation signal and a received signal, wherein the processing signal has the third sampling frequency; and
an analog-to-digital conversion circuit for generating at least one digital signal according to the processing signal, wherein the output signal is generated based on the at least one digital signal;
wherein the echo cancellation circuit comprises:
a second oversampling circuit configured to generate the second transmission signal according to the first transmission signal;
a first filter circuit for performing a filter procedure on the second transmission signal to generate a first filtered signal;
a third over-sampling circuit for generating a fourth transmission signal according to the first filtered signal and a random number, wherein the fourth transmission signal has the third sampling frequency;
the second shaping circuit is used for generating a second shaping signal according to the fourth transmission signal;
an adder for generating an operation signal according to the first shaping signal and the second shaping signal; and
the second digital-to-analog converter is used for generating the echo cancellation signal according to the operation signal.
2. The echo cancellation system of claim 1, wherein the second sampling frequency is more than twice the first sampling frequency.
3. The echo cancellation system of claim 1, wherein the second sampling frequency is one half of the third sampling frequency.
4. The echo cancellation system of claim 1, wherein the echo cancellation circuit further comprises:
a random number generation circuit for generating the random number; and
a second filter circuit for generating a second filter signal according to an inverted random number corresponding to the random number,
wherein the first filter circuit is updated based on the at least one digital signal and the second filter circuit.
5. An echo cancellation method for an echo cancellation system according to any one of claims 1 to 4, comprising:
receiving a first transmission signal through a data transmission circuit, wherein the first transmission signal has a first sampling frequency;
generating a second transmission signal according to the first transmission signal through an echo cancellation circuit, wherein the second transmission signal has a second sampling frequency, and the second sampling frequency is greater than the first sampling frequency;
generating an echo cancellation signal according to the second transmission signal through the echo cancellation circuit; and
and generating an output signal according to the received signal and the echo cancellation signal by the data transmission circuit.
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Citations (3)
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| US5553014A (en) * | 1994-10-31 | 1996-09-03 | Lucent Technologies Inc. | Adaptive finite impulse response filtering method and apparatus |
| JP2001102923A (en) * | 2000-07-31 | 2001-04-13 | Hitachi Ltd | Method and device for digital signal processing |
| JP2004228939A (en) * | 2003-01-23 | 2004-08-12 | Mitsubishi Electric Corp | Echo processor and voice processor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20030112887A1 (en) * | 2001-12-18 | 2003-06-19 | Sang Tzu Hsien | Method and system for implementing weighted vector error echo cancellers |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5553014A (en) * | 1994-10-31 | 1996-09-03 | Lucent Technologies Inc. | Adaptive finite impulse response filtering method and apparatus |
| JP2001102923A (en) * | 2000-07-31 | 2001-04-13 | Hitachi Ltd | Method and device for digital signal processing |
| JP2004228939A (en) * | 2003-01-23 | 2004-08-12 | Mitsubishi Electric Corp | Echo processor and voice processor |
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