CN114977403A - Battery management module, battery management system and chip packaging structure - Google Patents
Battery management module, battery management system and chip packaging structure Download PDFInfo
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- 238000004806 packaging method and process Methods 0.000 title description 5
- 238000012544 monitoring process Methods 0.000 claims abstract description 152
- 238000002955 isolation Methods 0.000 claims abstract description 42
- 238000005070 sampling Methods 0.000 claims description 63
- 238000004891 communication Methods 0.000 claims description 36
- 230000001360 synchronised effect Effects 0.000 claims description 33
- 238000006243 chemical reaction Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 abstract description 10
- 230000008569 process Effects 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 16
- 239000003990 capacitor Substances 0.000 description 7
- 238000009966 trimming Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
- H01M2010/4278—Systems for data transfer from batteries, e.g. transfer of battery parameters to a controller, data transferred between battery controller and main controller
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
- Y02T10/00—Road transport of goods or passengers
- Y02T10/60—Other road transportation technologies with climate change mitigation effect
- Y02T10/70—Energy storage systems for electromobility, e.g. batteries
Abstract
According to an embodiment of the present invention, a battery management module, a battery management system and an integrated circuit thereof are disclosed for managing a plurality of battery cells coupled in series, the battery management module includes at least two battery monitoring chips, each battery monitoring chip includes at least one battery monitoring unit, the battery monitoring unit is configured to monitor status information of the corresponding battery cell; a processor chip configured to control the at least two battery monitor chips; the battery monitoring chip and the processor chip are communicated in an isolation mode. The battery monitoring chip is manufactured by adopting a low-voltage semiconductor process, and is low in cost.
Description
Technical Field
The invention relates to the field of power electronics, in particular to a battery management module, a battery management system and a chip packaging structure.
Background
A Battery Management System (BMS) is an electronic circuit that manages a rechargeable battery pack by measuring state information of the rechargeable battery pack, which is further used to control the usage and balancing mechanisms of the batteries, and calculating derived data such as the state of charge and the safety state. With the widespread use of electric vehicles, BMSs are widely used for high-power batteries in which a large number of rechargeable batteries are connected in series for supplying high-voltage power.
As shown in fig. 1, which is a block diagram of a battery management circuit in the prior art, a monolithic integrated circuit, i.e., a chip IC, is used to monitor the voltage of M batteries, and if the maximum voltage of each battery is 6V, the withstand voltage of the port vc (n) reaches (6 × M) V. In high-power battery applications in which multiple strings of batteries are connected in series, such as automobiles, the highest port vc (n) may be more than 100V, in such applications, a chip IC needs to be manufactured by using a high-voltage semiconductor process, the process requirement is extremely high, the cost is high, and the chip IC usually uses a high-voltage multiplexing circuit to measure the voltages of a series of battery cells through an analog-to-digital conversion channel, which may cause some delays between battery measurements, thereby causing a delay in the status report of the whole system.
Disclosure of Invention
In view of the above, the present invention provides a battery management module, a battery management system and a chip package structure, so as to solve the technical problems of high process requirement, high cost and delay between battery measurements in the prior art.
The embodiment of the invention provides a battery management module, which is used for managing a plurality of battery units which are coupled in series and comprises the following components: at least two battery monitoring chips, each battery monitoring chip including at least one battery monitoring unit configured to monitor status information of a corresponding battery cell; a processor chip configured to control the at least two battery monitor chips; the battery monitoring chip and the processor chip are communicated in an isolation mode.
In one embodiment, the processor chip includes a synchronization circuit configured to send out a synchronous sampling signal to the at least two battery monitor chips in parallel to synchronously sample the state information of the battery units corresponding to the at least two battery monitor chips.
In one embodiment, the processor chip further includes a plurality of first transceiver modules, the synchronization circuit is configured to detect states of the plurality of first transceiver modules, when it is detected that the plurality of first transceiver modules are ready to receive a synchronous sampling signal, the synchronization circuit sends the synchronous sampling signal to the plurality of first transceiver modules in parallel, and the plurality of first transceiver modules send the synchronous sampling signal to the at least two battery monitor chips in an isolated manner.
In one embodiment, the battery monitoring chips comprise at least one second transceiver module, and the plurality of first transceiver modules transmit the synchronous sampling signals to the corresponding second transceiver modules in an isolated manner so as to synchronously sample the state information of the battery units corresponding to the at least two battery monitoring chips.
In one embodiment, the battery monitoring chip further includes a control circuit, the second transceiver module sends the received synchronous sampling signal to the control circuit, and the control circuit controls a sampling start time and a sampling time according to the synchronous sampling signal.
In one embodiment, the battery monitoring chip comprises at least one analog-to-digital conversion circuit and a timing circuit, wherein each battery monitoring unit corresponds to one analog-to-digital conversion circuit and is configured to convert an analog signal of the state information of the corresponding battery unit into a digital signal; the control circuit controls the timing circuit to set the sampling time according to the synchronous sampling signal so as to set the sampling time of the analog-to-digital conversion circuit.
In one embodiment, the battery monitor chip further comprises a fine tuning circuit configured to adjust the sampling time set by the timing circuit to enable fully synchronous communication between each battery monitor chip and the processor chip.
In one embodiment, each battery monitoring unit corresponds to one second transceiver module to perform isolated communication with the corresponding first transceiver module.
In one embodiment, each battery monitoring chip comprises at least two battery monitoring units and a multiplexer, each battery monitoring chip corresponds to one second transceiver module, and the at least two battery monitoring units share one second transceiver module through the multiplexer.
In one embodiment, the at least two battery monitor chips are coupled in series, and communication between two adjacent battery monitor chips is performed in an isolated manner.
In one embodiment, the isolation communication is configured as one of transformer isolation, capacitive isolation, and optical coupling isolation.
In one embodiment, the battery monitoring chip is configured to monitor a first battery pack to which N battery cells are sequentially coupled in series, and includes a supply voltage port coupled to a highest voltage terminal of the first battery pack and a ground reference port coupled to a lowest voltage terminal of the first battery pack.
In one embodiment, the battery monitoring chip further includes N +1 input ports, where the N +1 input ports are respectively coupled to the highest voltage end of the first battery pack, the common end of two adjacent battery units in the first battery pack, and the lowest voltage end of the first battery pack.
In one embodiment, the battery management module is configured to manage a second battery pack in which M battery cells are sequentially coupled in series, and the processor chip includes a supply voltage port coupled to a highest voltage terminal of the second battery pack and a ground reference port coupled to a lowest voltage terminal of the second battery pack.
In one embodiment, the battery management module is configured to manage a second battery pack in which M battery cells are coupled in series, and the processor chip includes a supply voltage port coupled to a highest voltage terminal of the second battery pack through a voltage conversion circuit and a ground reference port coupled to a lowest voltage terminal of the second battery pack.
An embodiment of the present invention further provides a chip packaging structure, including: the battery management module is described above.
An embodiment of the present invention further provides a battery management system, including: at least two battery management modules are connected in series, and the two adjacent battery management modules are communicated through a daisy chain.
Compared with the prior art, the technical scheme of the invention has the following advantages: the battery management module of the present invention is used for managing a plurality of battery cells coupled in series, and includes: at least two battery monitoring chips, each battery monitoring chip including at least one battery monitoring unit configured to monitor status information of a corresponding battery cell; a processor chip configured to control the at least two battery monitor chips; the battery monitoring chip and the processor chip are communicated in an isolation mode. Optionally, the battery management module is packaged in an integrated circuit. The battery monitoring chip is manufactured by adopting a low-voltage semiconductor process, and is low in cost. In addition, the plurality of battery monitoring chips in the battery management module share one processor chip, and the processor chip can transmit synchronous sampling signals to each battery monitoring chip in parallel so as to synchronously sample the plurality of battery monitoring chips in the battery management module, so that the state information of one or more battery units corresponding to each battery monitoring chip is sampled, and the state report delay of the system is reduced. Optionally, serial isolation communication may be performed between two adjacent battery monitoring chips in the battery management module, and when communication between any one of the battery monitoring chips and the processor chip is disconnected, the serial isolation communication between the two adjacent battery monitoring chips may be used as an alternative path, so that the communication robustness is enhanced. In addition, in the battery monitoring module, the electric potentials of each chip are different, the battery monitoring chip and the processing chip and the two adjacent battery monitoring chips are communicated in an isolation mode, the direct-current voltage difference between the different chips is isolated, and the common-mode interference is effectively eliminated.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a circuit diagram of a prior art battery management circuit;
FIG. 2 is a circuit diagram of a first embodiment of a battery management module and a battery monitor chip according to the present invention;
FIG. 3 is a circuit schematic of an embodiment of a trimming circuit and timing circuit of the present invention;
FIG. 4 is a circuit diagram of a second embodiment of a battery monitor chip according to the present invention;
FIG. 5 is a circuit diagram of a third embodiment of a battery monitor chip according to the present invention;
FIG. 6 is a circuit diagram of a fourth embodiment of a battery monitor chip according to the present invention;
FIG. 7 is a schematic circuit diagram of a battery management module and a battery monitor chip according to a fifth embodiment of the present invention;
FIG. 8 is a circuit diagram of a first embodiment of a battery management system according to the present invention;
fig. 9 is a circuit diagram of a battery management system according to a second embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
Fig. 2 is a circuit diagram of a battery management module and a battery monitoring chip according to a first embodiment of the invention. As shown in fig. 2, the battery management module 10 is used for managing the state information of the battery b11 and the battery b12 connected in series, the battery management module 10 includes a battery monitoring chip 11, a battery monitoring chip 12 and a processor chip 2, and the battery monitoring chip 12 is an upper chip of the battery monitoring chip 11. Wherein the state information includes battery voltage, current, and/or temperature, etc. The battery monitoring chip 11 is used for monitoring the state information of the battery b 11; the battery monitoring chip 12 is used for monitoring the state information of the battery b 12; the processor chip 2 is used to control the battery monitor chip 11 and the battery monitor chip 12. The battery monitor chip 11 and the battery monitor chip 12 both communicate with the processor chip 2 in an isolated manner.
The battery monitoring chip 11 includes a battery monitoring unit 111 and a control circuit, the battery monitoring unit 111 includes a low pass filter, an analog-to-digital conversion circuit, a digital filter and a second transceiver module, the low pass filter is coupled to the battery b11 for filtering a received analog signal representing battery status information, an output of the low pass filter is coupled to an input of the analog-to-digital conversion circuit, an output of the analog-to-digital conversion circuit is coupled to an input of the digital filter, and an output of the digital filter is coupled to an input of the second transceiver module. The control circuit is used for receiving the command transmitted by the second transceiver module and performing corresponding control according to the specific command; and the control circuit is also used for receiving and processing the sampling information of the battery voltage, current or temperature, etc., storing the sampling information and transmitting the sampling information to the processor chip 2 through the second transceiver module. The control circuit is also used for controlling the digital filter. In this embodiment, the control circuit includes a storage unit for storing the sampling information. In other embodiments, the battery monitoring unit 111 further comprises a memory module coupled between the digital filter and the second transceiver module. The control circuit is used for controlling the digital filter and the storage module. The internal structures of the battery monitoring chip 12 and the battery monitoring chip 11 are similar, and are not described herein again, and the working processes of the battery monitoring chip 12 and the battery monitoring chip 11 are also similar, and the following description will take the battery monitoring chip 11 as an example.
The processor chip 2 includes two first transceiver modules, a processor module and a synchronization circuit, the two first transceiver modules are respectively used for communicating with a second transceiver module in the battery monitoring chip 11 and the battery monitoring chip 12, and the processor module is used for processing and storing sampling information received by the first transceiver modules and controlling the battery monitoring chip 11 and the battery monitoring chip 12. The synchronous circuit is used for sending synchronous sampling signals to the battery monitoring chip 11 and the battery monitoring chip 12 in parallel so as to synchronously sample the state information of the battery b11 and the battery b 12.
Specifically, the synchronization circuit is used for detecting the states of the two first transceiver modules, and when detecting that the two first transceiver modules are ready to receive the synchronous sampling signal, the first transceiver modules are set to operate in a transmitting state, the synchronization circuit sends the synchronous sampling signal to the two first transceiver modules in parallel, the two first transceiver modules send the synchronous sampling signal to the battery monitoring chip 11 and the second transceiver module of the battery monitoring chip 12 in an isolating mode, and after the synchronous sampling signal is sent, the first transceiver modules are set to operate in a receiving state. Specifically, the synchronization circuit detects a state of the first transceiver module, and when it is detected that the first transceiver module provides a synchronization state display signal, it indicates that the first transceiver module is ready to receive a synchronization sampling signal, that is, the first transceiver module is waiting for the processor chip to send the synchronization sampling signal. After receiving the battery state information corresponding to each battery monitoring unit, the processor module temporarily stores the battery state information into a storage unit in the processor module, and transmits data to other cascaded battery management modules or MCUs in a daisy chain communication mode.
The battery monitoring chip 11 further includes a timing circuit, the second transceiver module sends the received synchronous sampling signal to the control circuit, and the control circuit controls the sampling start time and controls the timing circuit to set the sampling time by recognizing the synchronous sampling signal, so as to set the sampling time of the analog-to-digital conversion circuit in each battery monitoring unit, thereby synchronously sampling the state information of the battery b11 and the battery b 12.
Because each timing circuit has slight difference brought by the manufacturing process, even if each timing circuit sets the sampling time according to the synchronous sampling signal, the same set time length of different battery monitoring chips has difference. Further, the battery monitor chip 11 further includes a fine tuning circuit, which is used to adjust or calibrate the sampling time, so as to enable fully synchronous communication between each battery monitor chip and the processor chip in an isolated manner.
FIG. 3 provides a circuit schematic of an embodiment of a trimming circuit and timing circuit; the fine tuning circuit comprises resistors R1-R (N +1) and power switches Q1-QN, resistors R1-R (N +1) are coupled between a power supply VCC and a grounding end in series, the power switches Q1-QN are respectively connected with the resistors R1-RN in parallel in a one-to-one correspondence mode, control ends of the power switches Q1-QN are used for respectively receiving signals code 1-codeN, and the common ends of the resistors RN and R (N +1) generate fine tuning voltage Vtrim. And the codes 1-codeN are selected according to the synchronous sampling signals. The timing circuit comprises a power switch S1, a capacitor C2 and an inverter NOT, the trimming voltage Vtrim is applied to a control terminal of the power switch S1, a first power terminal of the power switch S1 is coupled to a power source VCC, a second power terminal of the power switch S1 is coupled to one terminal of the capacitor C2, the other terminal of the capacitor C2 is coupled to an output terminal of the inverter NOT, an input terminal of the inverter NOT receives a timing pulse signal V1 generated by the timing circuit, and an output terminal of the inverter is used for generating a trimmed pulse signal V1'. Optionally, the timing circuit further includes a capacitor C1, and the capacitor C1 is coupled between the control terminal of the power switch S1 and the ground terminal. The trimming voltage Vtrim can further trim the sampling duration in the timing circuit by changing the equivalent capacitance of the timing circuit, thereby eliminating the small difference caused by the manufacturing process and ensuring the further improvement of the synchronization performance.
The present invention only provides an example of a fine tuning circuit and a timing circuit, but the present invention is not limited to this, and any scheme of fine tuning the sampling time set by the timing circuit to achieve fully synchronous communication between each battery monitor chip and the processor chip can be used in the first embodiment shown in fig. 2.
Further, in this embodiment, the first transceiver module and the second transceiver module are bidirectional transceivers, and in other embodiments, the first transceiver module and the second transceiver module may be implemented by a combination of a unidirectional receiver and a unidirectional transmitter, which is not limited in this disclosure.
Preferably, the battery management module is packaged in an integrated circuit (i.e., a single sealed chip) by using a semiconductor packaging technology.
Further, there is a corresponding relationship between the numbers of the first transceiver module and the second transceiver module, and the first transceiver module and the second transceiver module communicate in an isolation manner, in this embodiment, the isolation communication is capacitive isolation, which is not limited in this disclosure. In other embodiments, the isolation communication may be other types of isolation communication, such as transformer isolation, optical coupling isolation, and the like. It should be noted that fig. 2 illustrates the concept of capacitive isolation by using one capacitor, and in practice, there is not necessarily only one capacitor, for example, a differential capacitive isolation is used for communication, and any capacitive isolation method is within the scope of the present application.
In the present embodiment, the battery monitor chip 12 includes a supply voltage port VDD, a ground reference port GND and two input ports, wherein the two input ports are respectively coupled to two ends of the battery b12, the supply voltage port VDD is coupled to a high potential end of the battery b12, and the ground reference port GND is coupled to a common end of the battery b11 and the battery b 12. The battery monitor chip 11 includes a supply voltage port VDD, a ground reference port GND and two input ports, wherein the two input ports are respectively coupled to two ends of the battery b11, the supply voltage port VDD is coupled to a common terminal of the battery b11 and the battery b12, and the ground reference port GND is coupled to a low potential terminal of the battery b 11. The processor chip 2 includes a supply voltage port VDD coupled to a high potential terminal of the battery b12 and a ground reference port GND coupled to a low potential terminal of the battery b 11. Namely: the battery b11 supplies power to the battery monitoring chip 11, the battery b12 supplies power to the battery monitoring chip 12, and the battery pack formed by the battery b11 and the battery b12 in series supplies power to the processor chip 2. In addition, in this embodiment, the battery monitor chip 11, the battery monitor chip 12 and the processor chip 2 further include a communication port for isolated communication between the first transceiver module and the second transceiver module, but the present invention is not limited thereto. In further embodiments, the battery monitor chip 11, the battery monitor chip 12 and the processor chip 2 do not include a communication port or partially include a communication port.
In this embodiment, the battery management module includes two battery monitoring chips, but the present invention is not limited thereto, and in other embodiments, the battery management module may include more than two battery monitoring chips to monitor the state information of more battery units.
In this embodiment, each of the battery monitoring chips includes a battery monitoring unit for monitoring status information of a battery unit, but the present invention is not limited thereto. FIG. 4 is a schematic circuit diagram of a second embodiment of the battery monitor chip of the present invention; compared with the battery monitoring chip in the first embodiment, the differences are that: the battery monitoring chip includes a battery monitoring unit 111 and a battery monitoring unit 112, the battery monitoring unit 111 and the battery monitoring unit 112 are respectively used for monitoring status information of the battery b111 and the battery b112, such as battery voltage, wherein each battery monitoring unit includes a second transceiver module. Optionally, each battery monitoring unit includes a separate isolated communication port. The battery monitoring unit 111 and the battery monitoring unit 112 in the same battery monitoring chip simultaneously receive instructions from the timing circuit to perform sampling, so that the battery monitoring unit 111 and the battery monitoring unit 112 can perform synchronous sampling. In the present embodiment, the battery monitor chip includes a supply voltage port VDD, a ground reference port GND, and three input ports coupled to a high-potential terminal of the battery b112, a common terminal of the battery b111 and the battery b112, and a low-potential terminal of the battery b111, respectively; the supply voltage port VDD is coupled to the high potential terminal of the battery b1112, and the ground reference port GND is coupled to the low potential terminal of the battery b111, that is: the battery pack formed by the battery b111 and the battery b112 connected in series supplies power to the battery monitoring chip. In the second embodiment, each battery monitoring chip includes two battery monitoring units, but the present invention is not limited thereto, and in other embodiments, each battery monitoring chip may include more than two battery monitoring units for monitoring status information of a plurality of battery units, where each battery monitoring unit monitors one battery unit correspondingly. In the present invention, the battery management module includes a plurality of battery monitoring chips, and the number of battery monitoring units included in each battery monitoring chip may be the same or different, which is not limited in the present invention.
In other embodiments, the battery monitoring chip correspondingly monitors a battery pack in which N battery cells are sequentially coupled in series, the battery monitoring chip includes a supply voltage port VDD, a ground reference port GND and N +1 input ports, the supply voltage port VDD is coupled to a highest voltage end of the battery pack in which the N battery cells are coupled in series, the ground reference port GND is coupled to a lowest voltage end of the battery pack in which the N battery cells are coupled in series, and the N +1 input ports are respectively coupled to a highest voltage end of the battery pack in which the N battery cells are coupled in series, a common end of two adjacent battery cells in the battery pack in which the N battery cells are coupled in series, and a lowest voltage end of the battery pack formed by connecting the N battery cells in series. Namely, a battery pack to which a plurality of battery cells corresponding to one battery monitor chip are coupled in series supplies power to the battery monitor chip. Furthermore, one battery management module correspondingly monitors the battery pack in which the M battery cells are sequentially coupled in series, and the processor chip includes a supply voltage port VDD and a ground reference port GND, wherein the supply voltage port VDD is coupled to the highest voltage end of the battery pack in which the M battery cells are coupled in series, and the ground reference port GND is coupled to the lowest voltage end of the battery pack in which the M battery cells are coupled in series. Namely, a battery pack in which a plurality of battery units corresponding to one battery management module are coupled in series supplies power to a processor chip in the battery management module. In this embodiment, the supply voltage port is directly coupled to the highest voltage terminal of the second battery pack, which is not limited in this embodiment, and in other embodiments, the supply voltage port is coupled to the highest voltage terminal of the second battery pack through a voltage conversion circuit.
FIG. 5 is a circuit diagram of a third embodiment of a battery monitor chip according to the present invention; compared with the battery monitoring chip described in the second embodiment, the differences are that: the battery monitoring unit 111 and the battery monitoring unit 112 share one second transceiver module through a multiplexer. The advantages are that: the number of the first transceiver module and the second transceiver module is reduced, the number of the isolated communication circuits is reduced, and the cost is reduced.
FIG. 6 is a circuit diagram of a fourth embodiment of a battery monitor chip according to the present invention; compared with the battery monitoring chip described in the second embodiment, the differences are that: the battery monitoring unit 111 is used for current sampling. A resistor Rs is connected in series to the lowest end of the battery pack, and the battery monitoring unit 111 detects the current flowing through the battery pack by monitoring the voltage of the resistor Rs; and the low-pass filter in the battery monitoring unit 111 in the second embodiment is replaced by a programmable amplifying circuit PGA to realize gain adjustment of the current sampling signal. In this embodiment, the current sampling channel and the voltage sampling channel are on the same battery monitoring chip, so that the voltage and the current are sampled synchronously.
FIG. 7 is a schematic circuit diagram of a battery management module and a battery monitor chip according to a fifth embodiment of the present invention; compared with the battery monitoring chip in the first embodiment, the differences are that: the battery monitoring chip 11 and the battery monitoring chip 12 communicate with each other in an isolated manner. The isolation communication can be capacitance isolation communication, transformer isolation communication or optical coupling isolation communication.
In this embodiment, the second transceiver module in the battery monitor chip 11 and the second transceiver module in the battery monitor chip 12 perform isolated communication, and in other embodiments, the battery monitor chip 11 and the battery monitor chip 12 further include another transceiver module for performing isolated communication between the battery monitor chip 11 and the battery monitor chip 12.
Fig. 8 is a circuit diagram of a battery management system according to a first embodiment of the invention. The battery management system comprises a battery management module 101 and a battery management module 102, wherein the battery management module 102 is an upper module of the battery management module 101, the battery management module 101 comprises n battery monitoring chips 11-1 n for sampling the state information of batteries b 11-b 1n, and the battery management module 102 comprises n battery monitoring chips 21-2 n for sampling the state information of batteries b 21-b 2 n. The first battery module 101 and the second battery management module 102 communicate with each other through a daisy chain. Further, the daisy chain is coupled with an isolation module (not shown) to enable the first battery module 101 and the second battery management module 102 to communicate with each other through the isolated daisy chain, and the isolation module may be a capacitive isolation module or a transformer isolation module, which is not limited in the present invention. Specifically, the processor chips 2 in the first battery module 101 and the second management module 102 each include a third transceiver module, the two third transceiver modules communicate with each other through an isolated daisy chain, and the isolation module is coupled between the two third transceiver modules. Further, one isolation module or two isolation modules may be coupled between the two transceiver modules, which is not limited in the present invention.
It should be noted that, in the present invention, the battery management system may include a plurality of battery management modules, and the number of the battery monitoring chips included in each battery management module may be the same or different, which is not limited in the present invention.
Fig. 9 is a circuit diagram of a battery management system according to a second embodiment of the present invention. Compared with the battery management system described in the first embodiment shown in fig. 8, the differences are that: the battery management module 101 further includes a battery monitoring chip 10 for sampling current. A resistor Rs is connected in series to the lowermost end of the battery pack, and the battery monitoring chip 10 includes only one battery monitoring unit for detecting the current flowing through the battery pack by monitoring the voltage of the resistor Rs.
The invention provides a battery management module and a framework of a battery management system. The battery management module is used for monitoring the states of a plurality of battery units connected in series, the battery management module comprises at least two battery monitoring chips and a processor chip, each battery monitoring chip comprises at least one battery monitoring unit (one battery monitoring unit corresponds to one sampling channel, namely an ADC link), and the battery monitoring chips are communicated with the processor chip in an electric isolation mode. Specifically, the battery monitoring chip transmits battery state information to the processor chip; the processor chip sends a sampling command or synchronous sampling signal to the television monitoring chip to acquire the state information of the battery, wherein the state information comprises information such as voltage, current, temperature and the like. The isolated communication between the battery monitor chip and the processor chip is bidirectional. A plurality of battery monitoring chips in the battery management module can simultaneously carry out parallel communication with the same processor chip. Optionally, two adjacent battery monitoring chips communicate with each other in an isolated manner, and when the communication between any one of the battery monitoring chips and the processor chip is disconnected, the serial isolated communication between the two adjacent battery monitoring chips can be transmitted to the processor chip as an alternative path; or the serial isolation communication between two adjacent battery monitoring chips is utilized to carry out battery equalization and the like. In one embodiment, each battery management module is packaged in an integrated circuit by semiconductor packaging techniques. Optionally, the port of the integrated circuit is configured as a port of each chip in the battery management module. The battery management system comprises a plurality of battery management modules which are coupled in series, two adjacent battery management modules are communicated through an isolation daisy chain, and specifically, processor chips in the two adjacent battery management modules are communicated through the isolation daisy chain to manage the energy storage system with more battery units.
Although the embodiments have been described and illustrated separately, it will be apparent to those skilled in the art that some common techniques may be substituted and integrated between the embodiments, and reference may be made to one of the embodiments not explicitly described, or to another embodiment described.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (17)
1. A battery management module for managing a plurality of battery cells coupled in series, comprising:
at least two battery monitoring chips, each battery monitoring chip including at least one battery monitoring unit configured to monitor status information of a corresponding battery cell;
a processor chip configured to control the at least two battery monitor chips;
the battery monitoring chip and the processor chip are communicated in an isolation mode.
2. The battery management module of claim 1, wherein: the processor chip comprises a synchronization circuit which is configured to send out synchronous sampling signals to the at least two battery monitoring chips in parallel so as to synchronously sample the state information of the battery units corresponding to the at least two battery monitoring chips.
3. The battery management module of claim 2, wherein: the processor chip further comprises a plurality of first transceiver modules, the synchronization circuit is used for detecting states of the plurality of first transceiver modules, when the plurality of first transceiver modules are detected to be ready to receive synchronous sampling signals, the synchronization circuit sends the synchronous sampling signals to the plurality of first transceiver modules in parallel, and the plurality of first transceiver modules send the synchronous sampling signals to the at least two battery monitoring chips in an isolation mode.
4. The battery management module of claim 3, wherein: the battery monitoring chips comprise at least one second transceiver module, and the plurality of first transceiver modules transmit the synchronous sampling signals to the corresponding second transceiver modules in an isolated mode so as to synchronously sample the state information of the battery units corresponding to the at least two battery monitoring chips.
5. The battery management module of claim 4, wherein: the battery monitoring chip also comprises a control circuit, the second transceiver module sends the received synchronous sampling signal to the control circuit, and the control circuit controls the sampling start time and the sampling time according to the synchronous sampling signal.
6. The battery management module of claim 5, wherein:
the battery monitor chip includes at least one analog-to-digital conversion circuit and a timing circuit,
each battery monitoring unit corresponds to one analog-to-digital conversion circuit and is configured to convert an analog signal of the state information of the corresponding battery unit into a digital signal;
the control circuit controls the timing circuit to set the sampling time according to the synchronous sampling signal so as to set the sampling time of the analog-to-digital conversion circuit.
7. The battery management module of claim 6, wherein: the battery monitor chip further comprises a fine tuning circuit configured to adjust the sampling time set by the timing circuit so as to enable fully synchronous communication between each battery monitor chip and the processor chip.
8. The battery management module of claim 4, wherein: each battery monitoring unit corresponds to one second transceiver module so as to carry out isolated communication with the corresponding first transceiver module.
9. The battery management module of claim 4, wherein: each battery monitoring chip comprises at least two battery monitoring units and a multiplexer, each battery monitoring chip corresponds to one second transceiver module, and the at least two battery monitoring units share one second transceiver module through the multiplexer.
10. The battery management module of claim 1, wherein: the at least two battery monitoring chips are coupled in series, and communication is carried out between two adjacent battery monitoring chips in an isolation mode.
11. The battery management module of claim 1 or 10, wherein: the isolation communication is configured as one of transformer isolation, capacitive isolation, and opto-coupler isolation.
12. The battery management module of claim 1, wherein: the battery monitoring chip is configured to monitor a first battery pack to which N battery cells are sequentially coupled in series, and includes a supply voltage port coupled to a highest voltage end of the first battery pack and a reference ground port coupled to a lowest voltage end of the first battery pack.
13. The battery management module of claim 12, wherein: the battery monitoring chip further comprises N +1 input ports, and the N +1 input ports are respectively coupled to the highest voltage end of the first battery pack, the common end of two adjacent battery units in the first battery pack, and the lowest voltage end of the first battery pack.
14. The battery management module of claim 1, wherein: the battery management module is configured to manage a second battery pack in which M battery cells are sequentially coupled in series, and the processor chip includes a supply voltage port coupled to a highest voltage end of the second battery pack and a reference ground port coupled to a lowest voltage end of the second battery pack.
15. The battery management module of claim 1, wherein: the battery management module is configured to manage a second battery pack in which M battery cells are coupled in series, and the processor chip includes a supply voltage port coupled to a highest voltage end of the second battery pack through a voltage conversion circuit and a ground reference port coupled to a lowest voltage end of the second battery pack.
16. A chip package structure, comprising: the battery management module of any of claims 1-15.
17. A battery management system, comprising:
at least two battery management modules of any of claims 1-15 coupled in series, wherein the two adjacent battery management modules communicate with each other via a daisy chain.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210623647.4A CN114977403A (en) | 2022-06-02 | 2022-06-02 | Battery management module, battery management system and chip packaging structure |
| CN202310584540.8A CN116742162A (en) | 2022-06-02 | 2023-05-23 | Battery management module, battery management system and battery management chip packaging structure |
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| CN202210623647.4A CN114977403A (en) | 2022-06-02 | 2022-06-02 | Battery management module, battery management system and chip packaging structure |
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