CN112564724B - MBUS host computer receiving circuit - Google Patents
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- H—ELECTRICITY
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- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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Abstract
The invention discloses a MBUS host receiving circuit, comprising: according to the MBUS host receiving circuit provided by the invention, the acquisition module acquires a current signal in an MBUS bus and converts the current signal into a level signal, the isolation module realizes electrical isolation between the acquisition module and the signal processing module, the signal processing module divides the level signal output by the isolation module into two paths, the two paths of level signals carry out voltage reduction processing on one path of level signal and filter a high level signal in the other path of level signal to obtain a reference voltage, the signal processing module filters a static electric signal of a low voltage signal after voltage reduction by using the reference voltage to obtain the level signal, and the signal conversion module converts the level signal into a TTL signal and then transmits the TTL signal to a single chip microcomputer, so that a pure and stable TTL signal can be obtained without manually setting the reference voltage, and the accuracy and the stability of the high level signal received by the MBUS host are improved.
Description
Technical Field
The invention relates to the technical field of meter bus MBUS, in particular to a MBUS host receiving circuit.
Background
MBUS is an instrument bus with a master-slave structure, and is mainly characterized in that a half-duplex non-polar common twisted pair is adopted to simultaneously realize power supply and data transmission of all substations, and all the substations (confirmed by different IDs) are connected in parallel on the MBUS bus, and can adopt any bus topological structure. When the MBUS is applied to an energy consumption intelligent management system consisting of various instruments or acquisition terminals and other related equipment, the related data in the instruments can be acquired to a concentrator through the MBUS and then transmitted to a system master station by using a corresponding communication interface.
Fig. 1 is a diagram of an MBUS bus structure, which is divided into a master and a slave, wherein the master is an MBUS master circuit including an MBUS master transmission circuit and an MBUS master reception circuit, and the slave is a slave station connected in parallel to the MBUS bus. The MBUS host receiving circuit is used for receiving data reported by each substation and converting the data reported in a current mode into TTL digital signals capable of being processed by the single chip microcomputer. At present, the difficulty of most of the conventional receiving circuits of the MBUS host is that the reliability is poor when the receiving circuits reach a certain load capacity, especially the load comes from different manufacturers, so that most of the prior art adds a plurality of MBUS channels on the same host, and the circuit structure is complex.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defect in the prior art that when the load on the MBUS bus is large, the reliability of the MBUS host receiving circuit is poor, thereby providing an MBUS host receiving circuit.
In order to achieve the purpose, the invention provides the following technical scheme:
an embodiment of the present invention provides an MBUS host receiving circuit, including: the system comprises an acquisition module, a signal processing module and a signal conversion module, wherein the acquisition module is connected in series in a high-potential MBUS bus and is used for acquiring a current signal in the MBUS bus, and converting and amplifying the current signal to obtain a voltage signal; the signal processing module is connected with the output end of the acquisition module and comprises a voltage reduction module, a filtering isolation module and a signal amplification module, the voltage signal is subjected to voltage reduction by the voltage reduction module to obtain a low-voltage signal, meanwhile, the voltage signal is subjected to filtering processing by the filtering isolation module to obtain a reference voltage, and the low-voltage signal obtained after voltage reduction and the reference voltage are input into the signal amplification module to obtain a level signal; the input end of the signal conversion module is connected with the output end of the signal processing module, and the output end of the signal conversion module is externally connected with the single chip microcomputer and used for converting the level signal into a TTL level and outputting the TTL level to the single chip microcomputer; the acquisition module, the signal processing module and the signal conversion module are all powered by an external power supply.
In one embodiment, the acquisition module comprises: the device comprises a first resistor and a current detection chip, wherein the first resistor is connected into a high-potential MBUS bus in series and converts an acquired current signal into a voltage signal; the current detection chip is connected with the first resistor in parallel and amplifies the voltage signal.
In an embodiment, the MBUS host receiving circuit further includes an isolation module connected between the acquisition module and the signal processing module for electrically isolating the voltage signal.
In an embodiment, the output terminal of the isolation module is connected to the input terminal of the voltage-reducing module and the input terminal of the filtering isolation module.
In one embodiment, the isolation module comprises: and the positive phase input end of the first operational amplifier is connected with the output end of the acquisition module.
In an embodiment, the signal amplifying module includes a third operational amplifier, a non-inverting input terminal of which is connected to the output terminal of the voltage-reducing module, and an inverting input terminal of which is connected to the output terminal of the filtering and isolating module.
In one embodiment, the voltage reduction module includes: the anode of the diode is connected with the output end of the isolation module, and the cathode of the diode is connected with the positive phase end of the third operational amplifier through the fifth resistor and is connected with the ground end through the fifth resistor and the sixth resistor in sequence.
In one embodiment, the filter isolation module includes: the filter module is an RC filter circuit and is connected between the isolation module and the second voltage follower, and a static electric signal is obtained through filtering; the second voltage follower is composed of a second operational amplifier, and the static electric signal is output to the inverting terminal of a third operational amplifier through the second voltage follower.
In one embodiment, the signal conversion module comprises a triode, a base electrode of the triode receives a level signal of the signal processing module, an emitting electrode of the triode is grounded, and a collector electrode of the triode is connected with the singlechip and is connected with an external power supply through a pull-up resistor.
The technical scheme of the invention has the following advantages:
the invention provides a MBUS (bus) host receiving circuit which comprises an acquisition module, a signal processing module and a signal conversion module, wherein the acquisition module acquires a current signal in an MBUS bus and converts the current signal into a voltage signal, the signal processing module divides the voltage signal into two paths, one path of voltage signal is subjected to voltage reduction processing to obtain a low-voltage signal obtained after voltage reduction, the other path of voltage signal is subjected to filtering processing to obtain a reference voltage, then the low-voltage signal obtained after voltage reduction is operated and amplified based on the reference voltage to obtain a level signal, the signal conversion module converts the level signal into a TTL (transistor-transistor logic) signal and then transmits the TTL signal to a single chip microcomputer, so that a pure and stable TTL (transistor-transistor logic) signal can be obtained without manually setting the reference voltage, and the accuracy and the stability of a high-level signal received by the MBUS host are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a diagram of an MBUS bus structure provided by an embodiment of the present invention;
fig. 2 is a composition diagram of a specific example of the MBUS host receiving circuit according to an embodiment of the present invention;
fig. 3 is a specific circuit structure diagram of the MBUS host receiving circuit according to an embodiment of the present invention;
fig. 4 is a composition diagram of another specific example of the MBUS host receiving circuit according to the embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Examples
An embodiment of the present invention provides an MBUS host receiving circuit, which is applied to an occasion where data acquired by an intelligent meter needs to be read and received, and as shown in fig. 2, the receiving circuit includes: the device comprises an acquisition module 1, a signal processing module 2 and a signal conversion module 3.
The acquisition module 1 is connected in series in a high-potential MBUS bus (MBUS + bus) and is used for acquiring a current signal in the MBUS + bus, converting and amplifying the current signal to obtain a voltage signal;
the signal processing module 2 is connected with the output end of the acquisition module 1, and comprises a voltage reduction module 21, a filtering isolation module 22 and a signal amplification module 23, wherein a voltage signal is subjected to voltage reduction by the voltage reduction module 21 to obtain a low-voltage signal, meanwhile, the voltage signal is subjected to filtering treatment by the filtering isolation module 22 to obtain a reference voltage, and the low-voltage signal and the reference voltage obtained after voltage reduction are input into the signal amplification module 23 to obtain a level signal;
the input end of the signal conversion module 3 is connected with the output end of the signal processing module 2, and the output end of the signal conversion module is externally connected with the singlechip and is used for converting the level signal into a TTL level and outputting the TTL level to the singlechip;
the acquisition module 1, the signal processing module 2 and the signal conversion module 3 are all powered by an external power supply.
As shown in fig. 2, an acquisition module 1 according to an embodiment of the present invention is connected in series to an MBUS + bus, and acquires a current signal (the current signal includes an electrical signal sent from a slave and a static electrical signal in a line) in the MBUS + bus in real time, and converts and amplifies the current signal to obtain a voltage signal; a voltage reduction module 21 in the signal processing module 2 reduces the voltage of the voltage signal to obtain a low-voltage signal obtained after voltage reduction, and a filtering isolation module 22 filters out an electric signal sent by a slave in the voltage signal to obtain a static electric signal which is used as a reference voltage; the signal amplification module 23 performs comparison amplification on the basis of the reference voltage and a low-voltage signal obtained after voltage reduction, that is, amplifies an electric signal sent from a slave to obtain a level signal; the signal conversion module 3 converts the level signal into TTL level and outputs the TTL level to the single chip microcomputer, and the single chip microcomputer reads data information in the level signal.
According to the MBUS host receiving circuit provided by the invention, the acquisition module acquires a current signal in an MBUS bus and converts the current signal into a voltage signal, the isolation module realizes electrical isolation between the acquisition module and the signal processing module, the signal processing module divides the voltage signal output by the isolation module into two paths, one path of voltage signal is subjected to voltage reduction processing to obtain a low-voltage signal obtained after voltage reduction, the other path of voltage signal is subjected to filtering processing to obtain a reference voltage, then, the reference voltage and the low-voltage signal obtained after voltage reduction are compared and amplified to obtain a level signal, and the level signal is converted into a TTL signal by the signal conversion module 3 and then is transmitted to a single chip microcomputer, so that a pure and stable TTL signal can be obtained without manually setting the reference voltage, and the accuracy and the stability of the high-level signal received by the MBUS host are improved.
In a specific embodiment, as shown in fig. 3, the acquisition module 1 includes: the device comprises a first resistor R1 and a current detection chip U1, wherein the first resistor R1 is connected in series into an MBUS + bus and converts an acquired current signal into a voltage signal; the current detection chip U1 is connected with the first resistor R1 in parallel and amplifies the voltage signal.
As shown in fig. 3, a first terminal VIN-and a second terminal VIN + of the current detection chip U1 according to the embodiment of the present invention are both connected to the MBUS + bus, a third terminal V + is connected to an external power supply, a fourth terminal GND is grounded, and a fifth terminal OUT is connected to the isolation module 4 through a second resistor R11 and is grounded.
In a specific embodiment, as shown in fig. 4, the MBUS host receiving circuit further includes an isolation module 4 connected between the acquisition module 1 and the signal processing module 2 for electrically isolating the voltage signal.
As shown in fig. 4, an output end of the isolation module 4 according to the embodiment of the present invention is connected to an input end of the voltage-reducing module 21 and an input end of the filtering isolation module 22, and after the voltage signal is electrically isolated by the isolation module 4, the voltage signal is respectively transmitted to the voltage-reducing module 21 for voltage-reducing processing, and then transmitted to the filtering isolation module 22 for filtering processing.
As shown in fig. 3, the isolation module 4 includes: and a positive-phase input end of the first operational amplifier U2B is connected to a fifth end OUT of the current detection chip U1 through a third resistor R8, an inverted-phase input end thereof is connected to an output end thereof, a positive power supply end thereof is connected to an external power supply and to a ground end through a first capacitor C1, a negative power supply end thereof is connected to the ground end, and an output end thereof is connected to the voltage reduction module 21 and the filtering isolation module 22, respectively.
In one embodiment, as shown in fig. 3, the voltage reducing module 21 includes: the diode D1 has an anode connected to the output terminal of the isolation module 4, and a cathode connected to the positive-phase terminal of the third operational amplifier through the fifth resistor R2, and connected to the ground terminal through the fifth resistor R2 and the sixth resistor R4 in sequence.
In one embodiment, as shown in fig. 3, the filter isolation module 22 includes: a filter module 221 and a second voltage follower 222.
As shown in fig. 3, the filtering module 221 according to the embodiment of the present invention is an RC filtering circuit, and is connected between the isolation module 4 and the second voltage follower 222 to obtain a static electrical signal through filtering, in fig. 3, the fourth resistor R9 and the second capacitor C3 form an RC filtering circuit, and the filtering circuit here may be other circuits having the same function, which is not limited herein and is not described again.
As shown in fig. 3, the second voltage follower 222 according to the embodiment of the invention is composed of a second operational amplifier U3A, the static electrical signal is output to the inverting terminal of the third operational amplifier through the second voltage follower 222, the non-inverting input terminal of the second operational amplifier U3A is connected to the output terminal of the first operational amplifier U2B through a fourth resistor R9 and is connected to the ground terminal through a second capacitor C3, the inverting input terminal thereof is connected to the output terminal thereof, the positive power terminal thereof is connected to the external power source and is connected to the ground terminal through a third capacitor C2, the negative power terminal thereof is connected to the ground terminal, and the output terminal thereof is connected to the signal amplification module 23.
As shown in fig. 3, the signal amplifying module 23 includes a third operational amplifier U2A, whose non-inverting input terminal is connected to the output terminal of the voltage-reducing module 21, and whose inverting input terminal is connected to the output terminal of the filtering and isolating module 22.
Because the level signal output by the isolation module 4 includes a static electric signal and a high level signal, the embodiment of the present invention provides the filtering isolation module 22, which passes through an RC filter circuit formed by the fourth resistor R9 and the second capacitor C3, the filter circuit can filter the high level signal and retain the static electric signal, the static electric signal is amplified by the second operational amplifier U3A to obtain a reference voltage and is transmitted to the signal amplification module 23, and the third operational amplifier U2A removes the static electric signal in the low voltage signal obtained after voltage reduction by using the reference voltage to obtain the level signal.
In a specific embodiment, as shown in fig. 3, the signal conversion module 3 includes a transistor V1, a base of the transistor V1 receives a level signal of the signal processing module 2, an emitter of the transistor V is grounded, a collector of the transistor V is connected to the single chip microcomputer and is connected to an external power supply through a pull-up resistor R3, and the transistor V1 converts a high level signal into a TTL level and outputs the TTL level to the single chip microcomputer.
Further, as shown in fig. 3, the current detection chip U1, the first resistor R1 and the second resistor R11 of the embodiment of the invention form an acquisition module 1, wherein a voltage output by the OUT terminal of the current detection chip U1 is V OUT ＝R1*I R1 * R11/5 k.OMEGA.in the formula, V OUT For the voltage output from the OUT terminal of the current detection chip U1, R1 is the resistance value of a first resistor R1, I R1 The current value of the first resistor R1 is 5k Ω related to the output parameter of the current detecting chip U1, which is only for illustration and not limited thereto.
The second capacitor C3 in the embodiment of the present invention filters the electrical signal sent from the slave in the voltage signal output by the isolation module 4, and only the static electrical signal in the line remains, and the static electrical signal is electrically isolated and the voltage signal is output to the signal amplification module 23 through the second operational amplifier U3A. The other path of level signal output by the isolation module 4 is stepped down by the step-down module 21 and then is transmitted to the signal amplification module 23, wherein the port voltage of the non-inverting input terminal of the third operational amplifier U2A is V U2A3 ＝(R4/(R2+R4))(V OUT -VD 1 ) In the formula V U2A3 R2 and R4 are the resistance values of the fifth resistor R2 and the sixth resistor R4, respectively, VD 1 Is the diode D1 voltage.
The third operational amplifier U2A performs a comparison operation based on the static electric signal output by the second operational amplifier U3A and the level signal output by the voltage-reducing module 21 to obtain an amplified electric signal sent by the slave, that is, a level signal, and transmits the amplified electric signal to the signal conversion module 3, and the signal conversion module 3 converts the level signal into a TTL level and outputs the TTL level to the MBUS host. Wherein the output voltage of the third operational amplifier U2A is V U2A1 ＝(1+R6/R5)*V U2A3 –(R6/R5)*V U3A3 In the formula, V U2A1 R5 and R6 are resistance values of the seventh resistor R5 and the eighth resistor R6, respectively, which are output voltages of the signal conversion module 3.
According to the MBUS host receiving circuit provided by the invention, the acquisition module acquires a current signal in an MBUS bus and converts the current signal into a voltage signal, the isolation module realizes electrical isolation between the acquisition module and the signal processing module, the signal processing module divides the voltage signal output by the isolation module into two paths, the voltage signal is subjected to voltage reduction processing on one path of voltage signal, an electric signal sent by a slave machine contained in the other path of voltage signal is filtered to obtain a voltage signal only retaining a static electric signal, the voltage signal is taken as a reference voltage, then comparison operation is carried out on the basis of the reference voltage and a low-voltage signal obtained after voltage reduction to obtain an amplified electric signal sent by the slave machine, namely a level signal, the level signal is converted into a TTL signal by the signal conversion module and then is transmitted to a single chip microcomputer, so that a pure and stable TTL signal can be obtained without manually setting the reference voltage, and the accuracy and stability of the high-level signal received by the MBUS host are improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the spirit or scope of the invention.
Claims (9)
1. An MBUS host receiver circuit, comprising: an acquisition module, a signal processing module and a signal conversion module, wherein,
the acquisition module is connected in series in the MBUS bus with high potential and is used for acquiring a current signal in the MBUS bus, and converting and amplifying the current signal to obtain a voltage signal; the current signals comprise electric signals sent from a slave and static electric signals in a line;
the signal processing module is connected with the output end of the acquisition module and comprises a voltage reduction module, a filtering isolation module and a signal amplification module, wherein the voltage signal is subjected to voltage reduction by the voltage reduction module to obtain a low-voltage signal, meanwhile, the filtering isolation module filters an electric signal sent by a slave machine in the voltage signal to obtain a static electric signal, the static electric signal is used as a reference voltage, the low-voltage signal obtained after the voltage reduction and the reference voltage are input into the signal amplification module, and the static electric signal in the low-voltage signal after the voltage reduction is removed by the reference voltage to obtain a level signal;
the input end of the signal conversion module is connected with the output end of the signal processing module, and the output end of the signal conversion module is externally connected with a single chip microcomputer and used for converting the level signal into a TTL level and outputting the TTL level to the single chip microcomputer;
the acquisition module, the signal processing module and the signal conversion module are all powered by an external power supply.
2. The MBUS host receiving circuit of claim 1, wherein the acquisition module comprises: a first resistor and a current detection chip, wherein,
the first resistor is connected into the high-potential MBUS bus in series and converts the acquired current signal into a voltage signal;
the current detection chip is connected with the first resistor in parallel and amplifies the voltage signal.
3. The MBUS master receiver circuit of claim 1, further comprising an isolation module coupled between the acquisition module and the signal processing module for electrically isolating the voltage signal.
4. The MBUS host receiver circuit of claim 3, wherein an output of the isolation module is connected to an input of the voltage dropping module and an input of the filter isolation module.
5. The MBUS host receive circuit of claim 3, wherein the isolation module comprises: and the positive phase input end of the first operational amplifier is connected with the output end of the acquisition module.
6. The MBUS host receiver circuit of claim 3, wherein the signal amplification module comprises a third operational amplifier having a non-inverting input terminal connected to the output terminal of the voltage reduction module and an inverting input terminal connected to the output terminal of the filtering isolation module.
7. The MBUS host receive circuit of claim 6, wherein the voltage-dropping module comprises: a diode, a fifth resistor and a sixth resistor, wherein,
and the anode of the diode is connected with the output end of the isolation module, and the cathode of the diode is connected with the positive phase end of the third operational amplifier through a fifth resistor and is connected with the ground end through the fifth resistor and the sixth resistor in sequence.
8. The MBUS host receive circuit of claim 6, wherein the filter isolation module comprises: a filter module and a second voltage follower, wherein,
the filtering module is an RC filtering circuit, is connected between the isolation module and the second voltage follower and obtains a static electric signal through filtering;
the second voltage follower is composed of a second operational amplifier, and the static electric signal is output to the inverting terminal of the third operational amplifier through the second voltage follower.
9. The MBUS host receiving circuit of claim 1, wherein the signal conversion module comprises a triode, a base electrode of the triode receives the level signal of the signal processing module, an emitting electrode of the triode is grounded, a collector electrode of the triode is connected with a single chip microcomputer, and the collector electrode of the triode is connected with an external power supply through a pull-up resistor.
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| CN112564724A (en) | 2021-03-26 |
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Address after: Zhengtai Instrument Measurement Industrial Park, No.1 Liangce Road, Beibaixiang Town, Leqing City, Wenzhou City, Zhejiang Province, 325603 Patentee after: ZHEJIANG CHINT INSTRUMENT & METER Co.,Ltd. Address before: 325603 Wenzhou Daqiao Industrial Park, Yueqing City, Wenzhou City, Zhejiang Province Patentee before: ZHEJIANG CHINT INSTRUMENT & METER Co.,Ltd. |