CN113296436B - Slave station equipment based on MBUS bus analog circuit - Google Patents

Slave station equipment based on MBUS bus analog circuit Download PDF

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CN113296436B
CN113296436B CN202110494084.9A CN202110494084A CN113296436B CN 113296436 B CN113296436 B CN 113296436B CN 202110494084 A CN202110494084 A CN 202110494084A CN 113296436 B CN113296436 B CN 113296436B
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resistor
electrically connected
circuit
triode
diode
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CN113296436A (en
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陈富光
汪芳君
谭龙
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Ningbo Water Meter Group Co Ltd
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Ningbo Water Meter Group Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25257—Microcontroller

Abstract

The invention discloses slave station equipment based on an MBUS bus analog circuit, which comprises a main control panel circuit and an MBUS bus; the MBUS bus comprises a signal conditioning circuit, a signal acquisition module and an output current control module; the input end of the signal conditioning circuit is electrically connected with the master station equipment, the output end of the signal conditioning circuit is electrically connected with the main control panel circuit through the signal acquisition module, and the signal conditioning circuit is used for receiving data signals sent by the master station equipment and sending the data signals to the main control panel circuit through the signal conditioning circuit and the signal acquisition module so as to realize data transmission from the master station equipment to the slave station equipment; one end of the output current control module is connected with the main control panel circuit, and the other end of the output current control module is connected with the signal conditioning circuit, and the output current control module is used for transmitting data signals of the main control panel circuit to the master station equipment through the signal conditioning circuit. The invention adopts the analog circuit to replace the existing special MBUS control chip so as to realize the data communication between the master station equipment and the slave station equipment and further reduce the cost of the MBUS bus.

Description

Slave station equipment based on MBUS bus analog circuit
Technical Field
The invention relates to bus control, in particular to slave station equipment based on a MBUS bus analog circuit.
Background
The meter bus MBUS is a novel bus structure, which is used for taking two nonpolar transmission lines as a power supply line and a transmission line for transmitting serial data respectively, and a plurality of terminal devices can be hung on the MBUS bus in parallel. The MBUS bus is used for intelligently managing devices related to each instrument, such as collecting and transmitting related data or signals to a master station. The MBUS bus has the characteristics of simple structure, low manufacturing cost, high reliability and the like. However, when the conventional MBUS bus is implemented, a dedicated MBUS control chip is generally adopted, and the MBUS control chip is high in cost, and meanwhile, the space of a terminal product control board is increased, so that the MBUS bus is not beneficial to large-scale application.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide slave station equipment based on an MBUS bus analog circuit, which can solve the problems of high cost, increased occupied space and the like when an MBUS bus is realized by adopting a special MBUS control chip in the prior art.
The purpose of the invention is realized by adopting the following technical scheme:
the slave station equipment based on the MBUS bus analog circuit comprises a main control panel circuit and an MBUS bus; the MBUS bus comprises a signal conditioning circuit, a signal acquisition module and an output current control module; one end of the signal conditioning circuit is electrically connected with the main station equipment, and the other end of the signal conditioning circuit is electrically connected with the main control panel circuit through the signal acquisition module, and is used for receiving data signals sent by the main station equipment and sending the data signals to the main control panel circuit through the signal acquisition module for analysis and processing; one end of the output current control module is electrically connected with the main control panel circuit, and the other end of the output current control module is electrically connected with the signal conditioning circuit, and is used for transmitting the data signals sent by the main control panel circuit to the master station equipment through the signal conditioning circuit.
Furthermore, the power output end of the signal conditioning circuit is electrically connected with the main control panel circuit and used for supplying power to the main control panel circuit.
Further, the signal conditioning circuit comprises a first input end POWER +, a second input end POWER +, a thermistor PTC, a transient diode TVS, a diode D1, a diode D2, a diode D3, a diode D4, a diode Z1, a triode Q6, a triode Q7, a triode Q8, a triode Q9, a capacitor C10, a capacitor C11, a capacitor C12, a resistor R26 and a resistor R27;
the first input end POWER + and the second input end POWER-are electrically connected with the master station equipment; the first input end POWER + is connected between the diode D2 and the diode D4 through the thermistor PTC, and the second input end POWER-is connected between the diode D1 and the diode D3;
one end of the transient diode TVS is electrically connected with the first input end POWER + through the thermistor PTC, and the other end of the transient diode TVS is electrically connected with the second input end POWER-;
the anode of the diode D1 is electrically connected with the output end VBUS, and the cathode of the diode D1 is grounded through the diode D3; the anode of the diode D2 is electrically connected with the output end VBUS, and the cathode of the diode D4 is grounded;
the emitter of the triode Q6 is electrically connected with the output end VBUS, the collector of the triode Q6 is grounded through a resistor R26, and the base of the triode Q6 is connected between the resistor R27 and the triode Q7; one end of the resistor R27 is electrically connected with the output end VBUS, and the other end of the resistor R27 is also electrically connected with the emitting electrode of the triode Q7; the base of the triode Q7 is connected between the resistor R26 and the collector of the triode Q6, and the collector is connected between the diode Z1 and the base of the triode Q8;
the negative electrode of the diode Z1 is grounded, and the positive electrode of the diode Z1 is electrically connected with the base electrode of the triode Q8;
the emitter of the triode Q8 is electrically connected with the base of the triode Q9, and the base is grounded through a capacitor C10; an emitter of the triode Q9 is grounded through a filter circuit consisting of a capacitor C12 and a capacitor C11, a base is electrically connected with the output end VBUS, and the emitter is electrically connected with a power supply end VCPU; the output end VBUS is electrically connected with the input end of the signal acquisition module; the power supply end VCPU is electrically connected with the main control panel circuit.
Further, the device also comprises a bus interface terminal; the master station equipment is electrically connected with the signal conditioning circuit through a bus interface terminal; the first input terminal POWER + is electrically connected to the port 1 of the bus interface terminal, and the second input terminal POWER-is electrically connected to the port 2 of the bus interface terminal.
Further, the signal acquisition module comprises a voltage dividing resistor R8 and a voltage dividing resistor R9; the output end VBUS of the signal conditioning circuit is electrically connected with the main control panel circuit through a voltage dividing resistor R8; the voltage dividing resistor R8 is also grounded through a voltage dividing resistor R9.
Further, the main control board circuit comprises a chip U1, a resistor R7, a resistor R1, a capacitor C1, a capacitor C2 and a capacitor C3; the port 25 of the chip U1 is electrically connected to the output terminal VCPU of the signal conditioning circuit through a resistor R7, the port 6 is grounded through a capacitor C2, the port 10 is grounded through a capacitor C3, the port 12 is grounded through a capacitor C1, the port 11 is grounded, and the port 6 is also electrically connected to the output terminal VCPU of the signal conditioning circuit through a resistor R1; the port 27 of the chip U1 is connected between the voltage dividing resistor R8 and the voltage dividing resistor R9 of the signal acquisition module.
Further, the output current control module comprises a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a transistor Q1, a transistor Q2 and a triode Q3; the port 24 of the chip U1 of the main control board circuit is electrically connected with the base of the triode Q1 through a resistor R11; the emitter of the triode Q1 is electrically connected with a power supply end VCPU of the signal conditioning circuit, and the collector is grounded through a resistor R10; the base electrode of the triode Q2 is connected between the collector electrode of the triode Q1 and the resistor R10 through the resistor R12, the collector electrode is electrically connected with the output end VBUS of the signal conditioning circuit through the resistor R20, and the emitter electrode is grounded through the resistor R13; the base electrode of the triode Q3 is connected between the collector electrode of the triode Q1 and the resistor R10 through the resistor R22, the collector electrode is electrically connected with the output end VBUS of the signal conditioning circuit through the resistor R21, and the emitter electrode is grounded through the resistor R23;
when the port 24 of the chip U1 of the main control panel circuit is at a high level, the transistor Q1, the transistor Q2, and the transistor Q3 are cut off, and the current of the signal conditioning circuit is less than 1.5 MA;
when the port 24 of the chip U1 of the main control board circuit is at low level, the triode Q1 is turned on, and the current range of the signal conditioning circuit is 11 MA-20 MA.
Further, the main control board circuit periodically reads a voltage value signal of the port 27 of the detection chip U1 to determine whether the MBUS bus is a null voltage or a pass voltage, and further determines whether the system is in a data transmission state or a data waiting state.
Further, when the system is in a data transmission state, the main control board circuit periodically reads the voltage signal of the port 27 of the chip U1, and converts the voltage signal of the port 27 of the chip U1 into a data signal by combining the MBUS electrical standard, the baud rate and the MBUS communication protocol; the master board circuit takes the logic level of the voltage signal at the port 27 of the chip U1 as a start flag of the data signal.
Compared with the prior art, the invention has the beneficial effects that:
the invention adopts an analog circuit to replace the existing special MBUS control chip, namely, adopts a MBUS bus circuit consisting of a signal conditioning circuit, a signal acquisition module and an output current control module, integrates the MBUS bus circuit on the slave station equipment and is electrically connected with a master control circuit of the slave station equipment, realizes data communication between the slave station equipment and the master station equipment, realizes the MBUS bus function, reduces the cost of the MBUS bus and does not occupy more space of the equipment.
Drawings
Fig. 1 is a schematic connection diagram of a MBUS bus and a master station device in a slave station device based on an MBUS bus analog circuit provided by the present invention;
FIG. 2 is a diagram of the signal conditioning circuit of FIG. 1;
FIG. 3 is a circuit diagram of the main control board circuit of FIG. 1;
FIG. 4 is a circuit diagram of the signal acquisition module of FIG. 1;
FIG. 5 is a circuit diagram of the bus interface terminal of FIG. 1;
fig. 6 is a circuit diagram of an output current control module provided by the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and the detailed description, and it should be noted that any combination of the embodiments or technical features described below can be used to form a new embodiment without conflict.
The invention provides slave station equipment based on an MBUS bus analog circuit, which is integrated into master station equipment by adopting the analog circuit instead of a traditional special MBUS control chip to realize data communication between the slave station equipment and the master station equipment. Preferably, as shown in fig. 1-6, the present embodiment includes an MBUS bus and a main control board circuit. The master control board circuit is a master controller of the slave station equipment. In addition, the slave station device further has other functional modules, which are not specifically described in this embodiment.
Preferably, the MBUS bus includes a signal conditioning circuit, a signal acquisition module, and an output current control module. One end of the MBUS bus is connected with the master station equipment, and the other end of the MBUS bus is connected with the main control panel circuit.
Specifically, one end of the signal conditioning circuit is electrically connected with the master station device, and the other end of the signal conditioning circuit is electrically connected with the main control panel circuit through the signal acquisition module, and is used for receiving the data signal issued by the master station device and issuing the data signal to the main control panel circuit through the signal acquisition module.
One end of the output current control module is electrically connected with the main control panel circuit, and the other end of the output current control module is electrically connected with the signal conditioning circuit, and is used for transmitting the data signal generated by the main control panel circuit to the main station equipment through the signal conditioning circuit.
The MBUS bus provided by this embodiment can implement data communication between the slave device and the master device, for example, data signals sent by the master device are sent to the slave device, or acquired data of the slave device are uploaded to the master device, thereby implementing an MBUS bus function.
Preferably, the signal conditioning circuit is further electrically connected with the master station device through a bus interface terminal. Can realize that the installation of slave station equipment and main website equipment is more convenient through bus interface terminal, directly realize inserting the slave station equipment into main website equipment through pluggable bus interface terminal, simple to operate, easy operation.
Preferably, as shown in fig. 3, the main control board circuit comprises a chip U1, a resistor R7, a resistor R1, a capacitor C1, a capacitor C2 and a capacitor C3. The port 25 of the chip U1 is electrically connected to the power supply terminal VCPU of the signal conditioning circuit through a resistor R7, the port 6 is grounded through a capacitor C2, the port 10 is grounded through a capacitor C3, the port 12 is grounded through a capacitor C1, the port 11 is grounded, and the port 6 is also electrically connected to the power supply terminal VCPU of the signal conditioning circuit through a resistor R1; the port 27 of the chip U1 is connected between the voltage dividing resistor R8 and the voltage dividing resistor R9 of the signal acquisition module.
As shown in fig. 2, the signal conditioning circuit includes a first input POWER +, a second input POWER-, a thermistor PTC, a transient diode TVS, a diode D1, a diode D2, a diode D3, a diode D4, a diode Z1, a transistor Q6, a transistor Q7, a transistor Q8, a transistor Q9, a capacitor C10, a capacitor C11, a capacitor C12, a resistor R26, and a resistor R27.
One end of a first input end POWER + is connected with the main station equipment, the other end of the first input end POWER + is connected between an access diode D2 and a diode D4 through a thermistor PTC, one end of a second input end POWER-is connected with the main station equipment, and the other end of the second input end POWER-is connected between a diode D1 and a diode D3.
One end of the transient diode TVS is electrically connected with the first input end POWER + through the thermistor PTC, and the other end is electrically connected with the second input end POWER-.
Diode D1, diode D2, diode D3, and diode D4 form a rectifier bridge. The anode of the diode D1 is electrically connected to the output terminal VBUS, and the cathode is grounded through the diode D3; the anode of the diode D2 is electrically connected to the output terminal VBUS, and the cathode is grounded through a diode D4.
The emitter of the triode Q6 is electrically connected with the output end VBUS, the collector is grounded through a resistor R26, and the base is connected between the resistor R27 and the triode Q7. One end of the resistor R27 is electrically connected to the output terminal VBUS, and the other end is further electrically connected to the emitter of the transistor Q7. The base of the triode Q7 is connected between the resistor R26 and the collector of the triode Q6, and the collector is connected between the diode Z1 and the base of the triode Q8.
The cathode of the diode Z1 is grounded, and the anode is electrically connected with the base of the triode Q8.
The emitter of the triode Q8 is electrically connected to the base of the triode Q9, and the base is grounded through a capacitor C10. The emitter of the transistor Q9 is grounded through a filter circuit composed of a capacitor C12 and a capacitor C11, the base is electrically connected to the output terminal VBUS, and the emitter is electrically connected to a power supply terminal VCPU.
The power end VCPU is electrically connected to the port 25 of the chip U1 through the resistor R7 of the main control board circuit, and is electrically connected to the port 6 of the chip U1 through the resistor R1 of the main control board circuit, so as to provide power to the main control board circuit. That is, the signal conditioning circuit in this embodiment is not only used to forward the data signal of the terminal device, but also can supply power to the main control board circuit to ensure stable operation of the MBUS bus based on the analog circuit.
More preferably, the signal conditioning circuit is electrically connected with the master station device through a bus interface terminal. As shown in fig. 5, the bus interface terminal P1 includes a port 1 and a port 2. The port 1 is electrically connected to the first input POWER +, and the port 2 is electrically connected to the second input POWER-. And the bus interface terminal P1 is used for realizing data transmission of the signal conditioning circuits of the master station device and the slave station device.
In this embodiment, the first input POWER + and the second input POWER-do not have polarity, that is, when the master device is electrically connected to the signal conditioning circuit through the bus interface terminal P1, the port 1 and the port 2 of the bus interface terminal P1 are wirelessly distinguished.
Specifically, in the present embodiment, a rectifier bridge is formed by the diode D1, the diode D2, the diode D3, and the diode D4, so that the polarity reversal connection resisting function of the MBUS bus is ensured. That is, when the master station device is electrically connected to the signal conditioning circuit through the bus interface terminal P1, if the electromotive force of the first input terminal POWER + is higher than the electromotive force of the second input terminal POWER +, the diode D2 and the diode D4 of the rectifier bridge are turned on, and the diode D1 and the diode D3 are turned off; conversely, if the electromotive force of the first input terminal POWER + is lower than the electromotive force of the second input terminal POWER +, the diodes D1 and D3 of the rectifier bridge are turned on, and the diodes D2 and D4 are turned off. Therefore, no matter the master station device is connected with the signal conditioning circuit through the bus interface terminal P1, the system power supply voltage can be ensured to be always in the positive polarity state as long as the difference of the electromotive forces of the first input terminal and the second input terminal is ensured. Like this, when the user is connected to master station equipment on the slave station equipment again, need not to distinguish positive negative pole, direct through bus interface terminal with master station equipment with the signal conditioning circuit electric connection of MBNUS bus can, avoid connecting the mistake.
More preferably, when the first input terminal POWER + and the second input terminal POWER-are in a bus connection state, that is, the signal conditioning circuit of the slave device is connected to the master device through the bus interface terminal P1, according to the electrical standard of the MBUS bus, as long as the voltage difference between the first input terminal POWER + and the second input terminal POWER-is ensured to be >10V, the stability of the POWER supply voltage of the POWER supply terminal VCPU, that is, 2.8V, is ensured through the transistor Q6, the transistor Q7, the transistor Q8, and the transistor Q9, and the stable operation of the main control board circuit is ensured. From the above, the signal conditioning circuit provided by the invention can realize data communication between the master control board circuit of the slave station equipment and the master station equipment, and can also supply power to the master control board circuit of the slave station equipment so as to supply power to other modules of the slave station equipment, thereby ensuring normal operation of the slave station equipment.
Preferably, as shown in fig. 4, the signal acquisition module includes a voltage dividing resistor R8 and a voltage dividing resistor R9. The output end VBUS is further electrically connected to the port 27 of the chip U1 of the main control board circuit through a voltage dividing resistor R8. The voltage dividing resistor R8 is also grounded through a voltage dividing resistor R9. The signal acquisition module can transmit the data signal issued by the master station equipment to the main control panel circuit; meanwhile, the pressure divider also plays a role in voltage division.
The bus voltage VBUS can be converted into the voltage V by the voltage dividing resistors R8 and R9 of the signal acquisition moduleAD-VHHSo as to meet the proper voltage signal of the input level range of the main control board circuit.
Specifically, the output voltage V is known according to the circuit of the signal acquisition moduleAD-VHHThe relationship with the output voltage of the power supply terminal VBUS of the signal conditioning circuit is as follows:
Figure BDA0003053636610000081
wherein, VAD-VHHIs the output voltage, V, of the signal acquisition moduleVBUSRepresenting the output voltage of the supply terminal VBUS of the signal conditioning circuit.
From the above formula, the output voltage V of the signal acquisition module can be ensured by the resistances of the divider resistor R8 and the divider resistor R9 and the electrical standard of the MBUS busAD-VHH<And 2.8, the voltage input standard of the main control board circuit is met.
In the embodiment, the working mode of the MBUS bus is simulated through the analog circuit to replace the existing special control chip for the MBUS so as to realize the function of the MBUS bus. Meanwhile, during data transmission, the master control board circuit of the slave station device identifies the data signal in a mode of dynamically identifying the reference level of the bus voltage, namely, the bus voltage reference level is dynamically identified within the allowable range of power consumption, so that data communication between the master station device and the slave station device is realized.
According to the electrical standard of the MBUS bus, the voltage range of the mark (logic level "1") is defined as: 24V-42V; the null (logic level "0") voltage range is specified as: the bus absolute voltage is >12V, and the blank signal voltage is less than the mark signal voltage by more than 10V.
To determine whether the MBUS bus is in a mark state or a space state, it is determined according to a logic level. Therefore, in order to effectively recognize the logic level, it is necessary to determine the reference voltage of the MBUS bus. In this embodiment, the voltage value V at the output end of the signal acquisition module is periodically readAD-VHHAnd according to the voltage value VAD-VHHReal-time updating of maximum voltage V of main control board circuitmax。
According to the MBUS electrical standard, the null sign voltage is less than the mark voltage by more than 10V, VΔThe voltage is the divided voltage value of 10V voltage at the output end of the signal acquisition module. Wherein, the first and the second end of the pipe are connected with each other,
Figure BDA0003053636610000091
physically representing the minimum difference between the blank and mark voltages identified in the controller. Setting selection Vref＝Vmax-V.DELTA.when VAD-VHH>VrefThe communication signal is logic level 1, otherwise it is logic 0. Wherein Vref is a reference level used in the controller to determine the logic level of the bus signal. In this embodiment, the following are set: when the signal V is collectedAD-VHHGreater than VrefIf so, the logic level of the bus is considered to be 1; otherwise, the logic level of the bus is 0.
Preferably, the embodiment calculates the ideal pulse width duration Tf required by each bit signal according to the baud rate, and sets the bit duration specified range [ Tf-Td, Tf + Td ] of the baud rate using the ideal pulse width duration Tf as a reference value]And thus the byte information transmitted on the bus, where Td represents the baud rate pulse width duration error. Thus, the output voltage V of the signal acquisition module is periodically read within the allowable range of power consumptionAD-VHHWhen the level holding duration of (2) is within the specified bit duration range, the signal level of the bit is determined.
Preferably, according to the communication protocol, the present embodiment sets a byte information bit to include a start bit, a data bit, a check bit and a stop bit. It is assumed that one byte of information includes n bits. That is, according to the above-described identification method, when the communication level signal of n bits is identified, it is considered that one byte information analysis is completed.
More preferably, the embodiment further sets all bytes to start with the start bit of low level and end with the stop bit of high level, so that the voltage signal V is used to analyze a frame of communication dataVD-VHHWhen the logic level of the data is 0, the data is used as an initial mark for analyzing the communication data, otherwise, the data is considered to be always in a mark voltage detection stage, so that the bus voltage is ensured to be updated in real time.
As is known from the MBUS bus standard, a signal transmitted from a master device to a master control board circuit of a slave device is generally expressed by a change in current value. Typically current values below 1.5MA represent a logical "1"; when transmitting '0', the main control board circuit increases the current to 11 MA-20 MA by control.
Preferably, the first input end of the output current control module is electrically connected to the main control board circuit, the power end is electrically connected to the power end VCPU of the signal conditioning circuit, and the second output end is electrically connected to the signal conditioning circuit, and is configured to control a current level in the signal conditioning circuit according to a control signal sent by the main control board circuit, and to transmit a data signal sent by the main control board circuit to the master station device through the signal conditioning circuit.
More specifically, as shown in fig. 6, the output current control module includes a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a transistor Q1, a transistor Q2, and a transistor Q3. The port 24 of the chip U1 of the master station device is electrically connected to the base of the transistor Q1 through a resistor R11.
The emitter of the triode Q1 is electrically connected to the power supply terminal VCPU of the signal conditioning circuit, and the collector is grounded through a resistor R10.
The base of the triode Q2 is connected between the collector of the triode Q1 and the resistor R10 through the resistor R12, the collector is electrically connected with the output end VBUS of the signal conditioning circuit through the resistor R20, and the emitter is grounded through the resistor R13.
The base of the triode Q3 is connected between the collector of the triode Q1 and the resistor R10 through the resistor R22, the collector is electrically connected with the output end VBUS of the signal conditioning circuit through the resistor R21, and the emitter is grounded through the resistor R23.
When the port 24 of the chip U1 of the main control board circuit is at a high level, the transistor Q1, the transistor Q2, and the transistor W3 are turned off, and the current of the bus signal conditioning circuit is less than 1.5 MA. Namely: when the communication transmits a "1" level signal, the port 24 of the chip U1 of the main control panel circuit is at a high level, the transistor Q1, the transistor Q2, and the transistor Q3 are turned off, and at this time, the consumed current is determined by the quiescent current of the main control panel circuit, that is, the quiescent current of the main control panel circuit is less than 1.5MA, and meets the MBUS electrical standard.
When the port 24 of the chip U1 of the main control board circuit is at low level, the triode Q1 is turned on, and the current range of the bus signal conditioning circuit is 11 MA-20 MA. When the communication transmits a '0' level signal, the port 24 of the chip U1 of the main control panel circuit is at a low level, at this time, the triode Q1 is conducted, and according to the characteristics of the current-limiting resistor R12, the current-limiting resistor R22, the triode Q2 and the triode Q3, the current consumed on the bus at this time meets the electric industry standard of MBUS, and the electric industry standard meets the requirements of 11 MA-20 MA.
The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are within the protection scope of the present invention.

Claims (8)

1. The slave station equipment based on the MBUS bus analog circuit is characterized by comprising a main control panel circuit and an MBUS bus; the MBUS bus comprises a signal conditioning circuit, a signal acquisition module and an output current control module; one end of the signal conditioning circuit is electrically connected with the main station equipment, and the other end of the signal conditioning circuit is electrically connected with the main control panel circuit through the signal acquisition module, and is used for receiving data signals sent by the main station equipment and sending the data signals to the main control panel circuit through the signal acquisition module for analysis and processing; one end of the output current control module is electrically connected with the main control panel circuit, and the other end of the output current control module is electrically connected with the signal conditioning circuit and is used for transmitting the data signal sent by the main control panel circuit to the master station equipment through the signal conditioning circuit; the signal conditioning circuit comprises a first input end POWER +, a second input end POWER-, a thermistor PTC, a transient diode TVS, a diode D1, a diode D2, a diode D3, a diode D4, a diode Z1, a triode Q6, a triode Q7, a triode Q8, a triode Q9, a capacitor C10, a capacitor C11, a capacitor C12, a resistor R26 and a resistor R27;
the first input end POWER + and the second input end POWER-are electrically connected with the master station equipment; the first input end POWER + is connected between the diode D2 and the diode D4 through the thermistor PTC, and the second input end POWER-is connected between the diode D1 and the diode D3;
one end of the transient diode TVS is electrically connected with the first input end POWER + through the thermistor PTC, and the other end of the transient diode TVS is electrically connected with the second input end POWER-;
the anode of the diode D1 is electrically connected with the output end VBUS, and the cathode of the diode D1 is grounded through the diode D3; the anode of the diode D2 is electrically connected with the output end VBUS, and the cathode of the diode D2 is grounded through the diode D4;
the emitter of the triode Q6 is electrically connected with the output end VBUS, the collector of the triode Q6 is grounded through a resistor R26, and the base of the triode Q6 is connected between the resistor R27 and the triode Q7; one end of the resistor R27 is electrically connected with the output end VBUS, and the other end of the resistor R27 is also electrically connected with the emitting electrode of the triode Q7; the base of the triode Q7 is connected between the resistor R26 and the collector of the triode Q6, and the collector is connected between the diode Z1 and the base of the triode Q8;
the cathode of the diode Z1 is grounded, and the anode is electrically connected with the base of the triode Q8;
the emitter of the triode Q8 is electrically connected with the base of the triode Q9, and the base is grounded through a capacitor C10; an emitter of the triode Q9 is grounded through a filter circuit consisting of a capacitor C12 and a capacitor C11, a base is electrically connected with the output end VBUS, and the emitter is electrically connected with a power supply end VCPU; the output end VBUS is electrically connected with the input end of the signal acquisition module; the power supply end VCPU is electrically connected with the main control panel circuit.
2. A slave station apparatus according to claim 1, wherein the power supply output of the signal conditioning circuit is electrically connected to the main control board circuit for supplying power to the main control board circuit.
3. A slave station device according to claim 1 which further comprises bus interface terminals; the master station equipment is electrically connected with the signal conditioning circuit through a bus interface terminal; the first input terminal POWER + is electrically connected to the port 1 of the bus interface terminal, and the second input terminal POWER-is electrically connected to the port 2 of the bus interface terminal.
4. The MBUS bus analog circuit-based slave station device of claim 1, wherein the signal acquisition module comprises a divider resistor R8 and a divider resistor R9; the output end VBUS of the signal conditioning circuit is electrically connected with the main control panel circuit through a voltage dividing resistor R8; the voltage dividing resistor R8 is also grounded through a voltage dividing resistor R9.
5. A slave station device based on a MBUS bus analogue circuit according to claim 4, wherein the master control board circuit comprises a chip U1, a resistor R7, a resistor R1, a capacitor C1, a capacitor C2 and a capacitor C3; the port 25 of the chip U1 is electrically connected to the output end VCPU of the signal conditioning circuit through a resistor R7, the port 6 is grounded through a capacitor C2, the port 10 is grounded through a capacitor C3, the port 12 is grounded through a capacitor C1, the port 11 is grounded, and the port 6 is also electrically connected to the output end VCPU of the signal conditioning circuit through a resistor R1; the port 27 of the chip U1 is connected between the voltage dividing resistor R8 and the voltage dividing resistor R9 of the signal acquisition module.
6. A slave device based on a MBUS bus analogue circuit according to claim 5, wherein the output current control module comprises a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a transistor Q1, a transistor Q2 and a transistor Q3; the port 24 of the chip U1 of the main control board circuit is electrically connected with the base of the triode Q1 through a resistor R11; the emitter of the triode Q1 is electrically connected with a power supply end VCPU of the signal conditioning circuit, and the collector is grounded through a resistor R10; the base electrode of the triode Q2 is connected between the collector electrode of the triode Q1 and the resistor R10 through the resistor R12, the collector electrode is electrically connected with the output end VBUS of the signal conditioning circuit through the resistor R20, and the emitter electrode is grounded through the resistor R13; the base electrode of the triode Q3 is connected between the collector electrode of the triode Q1 and the resistor R10 through the resistor R22, the collector electrode is electrically connected with the output end VBUS of the signal conditioning circuit through the resistor R21, and the emitter electrode is grounded through the resistor R23;
when the port 24 of the chip U1 of the main control panel circuit is at a high level, the transistor Q1, the transistor Q2, and the transistor Q3 are cut off, and the current of the signal conditioning circuit is less than 1.5 MA;
when the port 24 of the chip U1 of the main control board circuit is at low level, the triode Q1 is turned on, and the current range of the signal conditioning circuit is 11 MA-20 MA.
7. The slave station device based on the MBUS bus analog circuit, according to claim 6, wherein the master control board circuit periodically reads the voltage signal of the port 27 of the detection chip U1 to determine whether the MBUS bus is a null voltage or a mark voltage, and further determines whether the system is in a data transmission state or a data waiting state.
8. The slave station device based on the MBUS bus analog circuit, as claimed in claim 7, wherein when the system is in the data transmission state, the master control board circuit periodically reads the voltage signal of the port 27 of the chip U1, and converts the voltage signal of the port 27 of the chip U1 into a data signal in combination with the MBUS electrical standard, baud rate and MBUS communication protocol; the master board circuit takes the logic level of the voltage signal at the port 27 of the chip U1 as a start flag of the data signal.
CN202110494084.9A 2021-05-07 2021-05-07 Slave station equipment based on MBUS bus analog circuit Active CN113296436B (en)

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Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010001593A (en) * 1999-06-07 2001-01-05 정선종 Cell switching apparatus based on bus
DE10014955A1 (en) * 2000-03-22 2001-10-11 Enerlyt Potsdam Gmbh En Umwelt M-bus slave with data communications device e.g. for remote read-out of consumption/demand meters and counters, uses slave unit for providing remote data transmission into external data networks
CN102298345A (en) * 2011-05-20 2011-12-28 深圳市骏普科技开发有限公司 Communication method of M-BUS (meter-BUS)
CN202166856U (en) * 2011-05-20 2012-03-14 深圳市骏普科技开发有限公司 Slave receiving circuit of M-BUS
CN102483334A (en) * 2009-07-17 2012-05-30 伊特伦法国公司 Energy meter supplied by an m-bus
CN202887437U (en) * 2012-10-18 2013-04-17 天津市金硕科技投资集团有限公司 Remote meter reading system used for MBUS (Meter Bus) interface central heating meter and pulse interface water meter
CN103926862A (en) * 2014-04-03 2014-07-16 天津炳华科技研发有限公司 Micro-power-consumption M-bus slave end circuit for intelligent instrument communication and communication method thereof
CN203982576U (en) * 2014-06-24 2014-12-03 杭州海兴电力科技股份有限公司 M-BUS slave telecommunication circuit
CN206975450U (en) * 2017-05-17 2018-02-06 艾特仪表科技（深圳）有限公司 A kind of mbus circuits of opto-electrical direct reader
CN207909332U (en) * 2017-10-16 2018-09-25 瑞纳智能设备股份有限公司 A kind of high-power MBUS master circuits
CN209028810U (en) * 2018-12-13 2019-06-25 湖南常德牌水表制造有限公司 A kind of M-Bus main website multi-channel intelligent meter reading remote transmission device
CN111223286A (en) * 2019-10-18 2020-06-02 北京研华兴业电子科技有限公司 Meter BUS-based data acquisition device and method
CN211699196U (en) * 2020-03-24 2020-10-16 宁波水表(集团)股份有限公司 Receiving circuit of M-Bus instrument Bus

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8269622B2 (en) * 2009-03-17 2012-09-18 Jetlun Corporation Method and system for intelligent energy network management control system

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010001593A (en) * 1999-06-07 2001-01-05 정선종 Cell switching apparatus based on bus
DE10014955A1 (en) * 2000-03-22 2001-10-11 Enerlyt Potsdam Gmbh En Umwelt M-bus slave with data communications device e.g. for remote read-out of consumption/demand meters and counters, uses slave unit for providing remote data transmission into external data networks
CN102483334A (en) * 2009-07-17 2012-05-30 伊特伦法国公司 Energy meter supplied by an m-bus
CN102298345A (en) * 2011-05-20 2011-12-28 深圳市骏普科技开发有限公司 Communication method of M-BUS (meter-BUS)
CN202166856U (en) * 2011-05-20 2012-03-14 深圳市骏普科技开发有限公司 Slave receiving circuit of M-BUS
CN202887437U (en) * 2012-10-18 2013-04-17 天津市金硕科技投资集团有限公司 Remote meter reading system used for MBUS (Meter Bus) interface central heating meter and pulse interface water meter
CN103926862A (en) * 2014-04-03 2014-07-16 天津炳华科技研发有限公司 Micro-power-consumption M-bus slave end circuit for intelligent instrument communication and communication method thereof
CN203982576U (en) * 2014-06-24 2014-12-03 杭州海兴电力科技股份有限公司 M-BUS slave telecommunication circuit
CN206975450U (en) * 2017-05-17 2018-02-06 艾特仪表科技（深圳）有限公司 A kind of mbus circuits of opto-electrical direct reader
CN207909332U (en) * 2017-10-16 2018-09-25 瑞纳智能设备股份有限公司 A kind of high-power MBUS master circuits
CN209028810U (en) * 2018-12-13 2019-06-25 湖南常德牌水表制造有限公司 A kind of M-Bus main website multi-channel intelligent meter reading remote transmission device
CN111223286A (en) * 2019-10-18 2020-06-02 北京研华兴业电子科技有限公司 Meter BUS-based data acquisition device and method
CN211699196U (en) * 2020-03-24 2020-10-16 宁波水表(集团)股份有限公司 Receiving circuit of M-Bus instrument Bus

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