CN114976841A - Pulse driving circuit and ultrafast laser - Google Patents
Pulse driving circuit and ultrafast laser Download PDFInfo
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- CN114976841A CN114976841A CN202210918818.6A CN202210918818A CN114976841A CN 114976841 A CN114976841 A CN 114976841A CN 202210918818 A CN202210918818 A CN 202210918818A CN 114976841 A CN114976841 A CN 114976841A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S3/00—Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
- H01S3/09—Processes or apparatus for excitation, e.g. pumping
- H01S3/091—Processes or apparatus for excitation, e.g. pumping using optical pumping
- H01S3/094—Processes or apparatus for excitation, e.g. pumping using optical pumping by coherent light
- H01S3/094076—Pulsed or modulated pumping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S3/00—Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
- H01S3/005—Optical devices external to the laser cavity, specially adapted for lasers, e.g. for homogenisation of the beam or for manipulating laser pulses, e.g. pulse shaping
- H01S3/0057—Temporal shaping, e.g. pulse compression, frequency chirping
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Abstract
The invention provides a pulse driving circuit and an ultrafast laser, wherein the pulse driving circuit comprises: a delay circuit for delaying and outputting the initial phase pulse signal to generate a phase delay pulse signal; and the and operation circuit is used for performing and operation on the initial phase pulse signal and the phase delay pulse signal or performing and operation on at least two paths of the phase delay pulse signals to obtain a narrow pulse width pulse signal. The ultrafast laser includes: the pulse driving circuit; a power amplifier which amplifies the pulse train signal into a pulse current; a seed light generating device for generating seed light using the pulse current; and the laser generating device generates ultrafast laser by utilizing the seed light. The pulse driving circuit and the ultrafast laser have smaller volumes and high reliability.
Description
Technical Field
The invention relates to the technical field of ultrafast lasers, in particular to a pulse driving circuit and an ultrafast laser.
Background
In some high-precision ultrafast pulse laser products on the market, there are many application occasions that need to use an electric drive signal function with an extremely narrow pulse width, for example, the drive electric pulse requirement with a pulse width near 100ps, and the pulse can be directly used for driving a seed light generating device of an ultrafast laser product after being amplified by a radio frequency amplification tube.
In some existing applications of ultrafast lasers, some ultrafast lasers generate high-frequency narrow pulses through optical compression, and the pulse generation and Burst menu functions are realized through an acousto-optic AOM frequency selection scheme. The existing scheme has high composition complexity and high cost. Because optical pulse generation and devices such as acousto-optic AOM are used at the same time, the debugging difficulty and reliability are lower. In the production process of large-scale industrial products and possible ultrafast laser consumer products, a lot of labor and material cost is increased, and the requirements of small, fine, real and wide adaptation range of industrial products are not met.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a pulse driving circuit, which is used to solve the problems of high complexity and high cost in the prior art.
To achieve the above and other related objects, the present invention provides a pulse driving circuit, comprising:
a delay circuit for delaying and outputting the initial phase pulse signal to generate a phase delay pulse signal;
and the and operation circuit is used for performing and operation on the initial phase pulse signal and the phase delay pulse signal or performing and operation on at least two paths of the phase delay pulse signals to obtain a narrow pulse width pulse signal.
In an embodiment of the invention, the pulse driving circuit further includes an or operation circuit, and the or operation circuit combines a plurality of the narrow pulse width pulse signals into a pulse train signal.
In an embodiment of the present invention, the pulse driving circuit further includes a signal distribution circuit for distributing the initial phase pulse signal into an initial phase first replica signal and an initial phase second replica signal;
the phase-delayed pulse signal is generated by the delay circuit delaying the initial phase first replica signal to output;
the AND operation circuit is used for performing AND operation on the initial phase first replica signal and the phase delay pulse signal.
In an embodiment of the invention, the pulse driving circuit further includes a programmable circuit, and the initial phase pulse signal is generated by the programmable circuit.
In an embodiment of the invention, the delay time of the delay circuit is adjustable, and the control signal of the delay time is generated by the programmable circuit.
In an embodiment of the invention, the and operation circuit includes a plurality of and operation chips, the and operation chips have enable terminals, and enable signals are generated by the programmable circuit.
In an embodiment of the present invention, the model of the and operation chip is SY10EP series model.
In an embodiment of the present invention, the initial phase pulse signal is a differential signal, the differential signal includes a positive signal and a negative signal, the and operation chip performs and operation on each path of the positive signal, and the and operation chip further performs and operation on each path of the negative signal.
In one embodiment of the invention, the initial phase pulse signal comprises a first differential signal and a second differential signal generated by the programmable circuit, the pulse drive circuit further comprises a signal distribution circuit comprising a first differential fan-out buffer and a second differential fan-out buffer, the first differential fan-out buffer distributing the first differential signal into a first differential first replica signal, a first differential second replica signal, a first differential third replica signal, and a first differential fourth replica signal;
the second differential fan-out buffer distributes the second differential signal into a second differential first replica signal, a second differential second replica signal, a second differential third replica signal, and a second differential fourth replica signal;
the delay circuit comprises a first delay chip and a second delay chip, the first delay chip delays and outputs the first differential second replica signal to generate a first phase delay pulse signal, and the first delay chip also delays and outputs the second differential first replica signal to generate a second phase delay pulse signal;
the second delay chip delays and outputs the second differential fourth replica signal to generate a third phase delay pulse signal, and the second delay chip also delays and outputs the first differential third replica signal to generate a fourth phase delay pulse signal;
the AND operation circuit comprises a first AND operation chip, a second AND operation chip, a third AND operation chip and a fourth AND operation chip, wherein the first AND operation chip performs AND operation on the first differential first replica signal and the first phase delay pulse signal, the second AND operation chip performs AND operation on the second phase delay pulse signal and the second differential second replica signal, the third AND operation chip performs AND operation on the second differential third replica signal and the third phase delay pulse signal, and the fourth AND operation chip performs AND operation on the fourth phase delay pulse signal and the first differential fourth replica signal.
To achieve the above and other related objects, the present invention also provides an ultrafast laser, including:
the pulse generator adopts the pulse driving circuit;
a power amplifier which amplifies the pulse train signal into a pulse current;
a seed light generating device for generating seed light using the pulse current;
and the laser generating device generates ultrafast laser by utilizing the seed light.
As described above, the pulse driving circuit and the ultrafast laser according to the present invention have the following advantageous effects: the volume is small, and the reliability is high.
Drawings
Fig. 1 is a block diagram of a pulse driving circuit according to an embodiment of the invention.
Fig. 2 is a schematic structural diagram of a signal distribution circuit in a pulse driving circuit according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of a delay circuit in a pulse driving circuit according to an embodiment of the invention.
Fig. 4 is a schematic structural diagram of an and operation circuit in a pulse driving circuit according to an embodiment of the invention.
Fig. 5 is a schematic diagram of a pulse width compression circuit according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a pulse driving circuit according to another embodiment of the invention.
Fig. 7 is a schematic diagram of the compressed pulse width of the and operation circuit of fig. 6.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1 to 7, the present invention provides a pulse driving circuit including a delay circuit and an and operation circuit. The delay circuit delays and outputs the initial phase pulse signal to generate a phase delay pulse signal. And operation circuit and operates initial phase pulse signal and phase delay pulse signal, or AND operates at least two paths of phase delay pulse signal, and obtains narrow pulse width pulse signal.
In this embodiment, the main function of the pulse driving circuit is to delay the signal, so as to provide an input signal with a different phase from the operational circuit. In this embodiment, the delay circuit may have only one input or multiple inputs. When the delay circuit has only one input, one of the two input signals of the AND operation circuit comes from the phase delay pulse signal output by the delay circuit, and the other comes from the initial phase pulse signal which does not pass through the delay circuit. Referring to fig. 5, the pulse width of the narrow pulse width pulse signal output from the arithmetic circuit is an overlapping portion of the phase delay pulse signal and the initial phase pulse signal, so that the pulse width of the narrow pulse width pulse signal is smaller than the phase delay pulse signal or the initial phase pulse signal, and pulse width compression is realized.
When the delay circuit has multiple inputs, the two input signals of the arithmetic circuit may be both from the phase-delayed pulse signals output from the delay circuit, and pulse width compression can be realized by using the phase difference between the two phase-delayed pulse signals. Specifically, the present embodiment does not limit the type and number of delay chips for specific sampling in the delay circuit. Taking the example of using multiple delay chips, different delay chips can generate different delay times through element parameter selection or programming, so as to generate two phase delay pulse signals with different phases at the output end of the delay circuit.
The present embodiment makes a phase difference between different pulse signals by a delay circuit, and realizes pulse width compression by extracting an overlapping portion of two pulse signals having different phases with an arithmetic circuit. Compared with the prior art that the pulse width is compressed through an optical device, the pulse width compression device is smaller in size and higher in reliability.
In other application occasions, a plurality of narrow pulses are needed to be combined and output so as to realize the Burst function of the laser, the functions of waveform online adjustment and the like are needed to be carried out on the output of seed light pulses to match the process requirement of precision cold processing, no special semiconductor components are needed, the index requirement exceeds the upper limit of the physical resolution of most of the existing products, and a driving circuit which has narrow pulse width, adjustable parameters, simple and clear composition circuit and simple physical realization is needed, so that the driving circuit has important significance for improving the stability of the whole system, reducing the cost and debugging difficulty and adapting to the requirements of various ultrafast lasers.
In order to facilitate the laser to realize Burst function, in this embodiment, referring to fig. 1, the pulse driving circuit further includes an or operation circuit, or the or operation circuit combines a plurality of narrow pulse width pulse signals into a pulse train signal. The or operation circuit is connected with the output end of the and operation circuit, and outputs multiple parallel narrow pulse width pulse signals with the operation circuit, phase difference can be generated between the narrow pulse width pulse signals through the arrangement of the parameter delay circuit, or the operation circuit can combine the multiple narrow pulse width pulse signals into one path to be output by utilizing the phase difference, and the number of pulses is increased.
In the present embodiment, referring to fig. 2, the pulse driving circuit further includes a signal distribution circuit for distributing the initial phase pulse signal into an initial phase first replica signal and an initial phase second replica signal; the phase delay pulse signal is generated by delaying and outputting the initial phase first copy signal by a delay circuit; the AND operation circuit is used for AND operation of the initial phase first replica signal and the phase delay pulse signal.
Specifically, in this embodiment, the signal distribution circuit includes one or more fan-out chips, such as differential fan-out chips. The fan-out chip can play a role in signal relay, can play a role in reducing signal reflection on a high-speed low-voltage differential signal transmission path, enhances the signal transmission capability and reduces noise. Meanwhile, the output signal of the fan-out chip is synchronous with the input signal, and the two output fan-out signals are in-phase signals. Therefore, the first output signal (such as the first replica signal of the initial phase) of the fan-out chip and the second output signal (such as the second replica signal of the initial phase) of the fan-out chip are strictly synchronous with the input signal, so that less adjustment workload of the signal delay node can be realized, and only the delay needs to be adjusted according to the pulse width parameter requirement of the actual driving signal. In existing driver circuits that do not use fan-out chips, when the wiring is not in specification, additional correction code is required to make the pulse width compression adjustment range fall between the specification upper and lower limit parameters of the delay chip. This embodiment is through using fan-out chip, according to actual observation, can use the delay range of the line delay chip of back level full, reaches higher utilization ratio, need not to use partial range to close the time error of circuit wiring and transmission, can shorten more than 50% with debugging and test time.
In this embodiment, the pulse driving circuit further includes a programmable circuit, and the initial phase pulse signal is generated by the programmable circuit. Specifically, the programmable circuit may be PAL, PLD, CPLD, FPGA, or the like. The reference repetition frequency can be edited and set through the programmable circuit.
In this embodiment, the delay time of the delay circuit is adjustable, and the control signal of the delay time is generated by the programmable circuit. Specifically, the delay circuit comprises a plurality of delay chips, and the model of the delay chip can adopt NB6L295MMNG or other brands of equivalent models, etc.). Through on-line programming of the programmable circuit, the delay time of each delay chip can be conveniently set, so that the phase difference and the overlapping area of two pulse signals participating in the operation can be finely adjusted, and the width of the narrow pulse width pulse signal can be adjusted on line.
In this embodiment, the and operation circuit includes a plurality of and operation chips, each of the and operation chips has an enable terminal, and the enable signal is generated by the programmable circuit. Through on-line programming of the programmable circuit, whether each AND operation chip works or not can be set, so that a part of narrow pulse width pulse signals can be selected selectively to be used as the input of subsequent OR operation. Generally, the more each and operation chip is in the enabled state, the greater the number of Burst pulses.
Specifically, the and operation chip is a multi-way and gate. Specifically, the and operation chip is SY10EP series. Further, the SY10EP series AND operation chip is selected from Microchip corporation. In another embodiment, the SN74AC series from TI or other brands of the same type are selected as the operation chip.
In the present embodiment, referring to fig. 6, the signal distribution circuit includes one-to-two fan-out chips, and the delay circuit includes a line delay chip. And the one-to-two fan-out chip outputs a first fan-out signal and a second fan-out signal, and the first fan-out signal is converted into a first fan-out delay signal through the line delay chip. And inputting the first fan-out delay signal and the second fan-out signal into the operational circuit to perform pulse width compression to obtain a narrow pulse width pulse signal. The pulse width compression principle in this embodiment refers to fig. 7.
In this embodiment, the or operation circuit includes a plurality of or operation chips, or the or operation chip has an enable terminal, and the enable signal is generated by the programmable circuit. Through the on-line programming of the programmable circuit, whether each OR operation chip works or not can be set, and finally the number of Burst pulses can be adjusted. Specifically, the or operation chip is a multi-way and gate. In one embodiment, the OR chip is model number Onsemi MC100EP series. In another embodiment, the or operation chip is a single-ended or gate, such as the CD4078B model of TI corporation.
In this embodiment, the initial phase pulse signal is a differential signal, the differential signal includes a positive signal and a negative signal, the and operation chip performs and operation on each positive signal, and the and operation chip further performs and operation on each negative signal. Similarly, the or operation circuit performs or operation on each positive electrode signal, and the or operation circuit performs or operation on each negative electrode signal. For example, referring to fig. 5, the and operation chip performs and operation on the pulse signal LVDS-INPUT-P1 and the pulse signal LVDS-INPUT-P2 to obtain the narrow-pulse-width pulse signal OUPUT-P. And the AND operation chip performs AND operation on the pulse signal LVDS-INPUT-N1 and the pulse signal LVDS-INPUT-N2 to obtain a narrow pulse width pulse signal OUPUT-N. In the embodiment, the pulse width compression can be realized under the application condition of high speed by adopting the differential signal, and the signal is transmitted to the receiving end without distortion to the maximum extent. Specifically, in an embodiment, the pulse driving circuit further includes a signal distribution circuit and an interface resistor network for impedance matching, so as to achieve the purpose of signal transmission interaction.
The OR operation circuit combines and outputs each path of narrow pulse width pulse signal OUPUT-P, or the operation circuit also combines and outputs each path of narrow pulse width pulse signal OUPUT-N.
Specifically, referring to FIG. 2, in this embodiment, the initial phase pulse signal includes a first differential signal (including LVDS-INPUT-N1 and LVDS-INPUT-P1) and a second differential signal (including LVDS-INPUT-N2 and LVDS-INPUT-P2) generated by the programmable circuit, and the pulse driving circuit further includes a signal distribution circuit including a first differential FAN-OUT buffer (FAN-OUT-CHIP-1) and a second differential FAN-OUT buffer (FAN-OUT-CHIP-2), the first differential FAN-OUT buffer distributing the first differential signal as a first differential first replica signal (including LVDS-N1-1 and LVDS-P1-1), a first differential second replica signal (including LVDS-N1-2 and LVDS-P1-2), a first differential third replica signal (including LVDS-N1-3 and LVDS-P1-3) to generate the first differential signal and the second differential FAN-OUT-CHIP-2), and the first differential FAN-OUT-CHIP-2 And a first differential fourth replica signal (comprising LVDS-N1-4 and LVDS-P1-4).
The second differential fan-out buffer distributes the second differential signal into a second differential first replica signal (including LVDS-N2-1 and LVDS-P2-1), a second differential second replica signal (including LVDS-N2-2 and LVDS-P2-2), a second differential third replica signal (including LVDS-N2-3 and LVDS-P2-3), and a second differential fourth replica signal (including LVDS-N2-4 and LVDS-P2-4).
The DELAY circuit includes a first DELAY CHIP (CHANNEL-DELAY-CHIP-1) that DELAYs an output of the first differential second replica signal to generate a first phase DELAY pulse signal (including LVDS-N1-2-DELAY and LVDS-P1-2-DELAY), and a second DELAY CHIP (CHANNEL-DELAY-CHIP-2) that DELAYs an output of the second differential first replica signal to generate a second phase DELAY pulse signal (including LVDS-N2-1-DELAY and LVDS-P2-1-DELAY).
The second DELAY chip DELAYs the output of the second differential fourth replica signal to generate a third phase-delayed pulse signal (including LVDS-N2-4-DELAY and LVDS-P2-4-DELAY), and the second DELAY chip also DELAYs the output of the first differential third replica signal to generate a fourth phase-delayed pulse signal (including LVDS-N1-3-DELAY and LVDS-P1-3-DELAY).
The AND operation circuit comprises a first AND operation chip (& -1), a second AND operation chip (& -2), a third AND operation chip (& -3) and a fourth AND operation chip (& -4), wherein the first AND operation chip carries out AND operation on a first differential first replica signal and a first phase delay pulse signal, the second AND operation chip carries out AND operation on a second phase delay pulse signal and a second differential second replica signal, the third AND operation chip carries out AND operation on a second differential third replica signal and a third phase delay pulse signal, and the fourth AND operation chip carries out AND operation on a fourth phase delay pulse signal and a first differential fourth replica signal.
The invention also provides an ultrafast laser which comprises a pulse generator, a power amplifier, a seed light generating device and a laser generating device. The pulse generator adopts the pulse driving circuit in any of the above embodiments, the power amplifier (e.g., the amplifier tube, the radio frequency driving unit) amplifies the pulse train signal into a pulse current, the seed light generating device (seed laser generating pump) generates seed light by using the pulse current, and the laser generating device generates ultrafast laser by using the seed light.
The invention realizes fan-out, delay, logic pulse width compression and multi-narrow pulse width combination of the pulse input signal by using the fan-out chip, the delay chip, the AND operation chip and the OR operation chip. The output pulse number-editable large-current narrow pulse width signal is used as the electric drive of the light generated by the earliest stage signal of the ultrafast laser product.
The signal is fanned out through a fanout chip, delayed through a delay chip, subjected to differential phase and operation through an operation chip, subjected to signal combination through an OR operation chip, and finally output to a power amplifier.
The pulse width of an output pulse signal is indirectly adjusted by editing parameters of a delay chip, the number of Burst pulses is set by controlling the enabling or disabling of a multipath AND gate and an OR gate, an implementation principle of 0-4 Burst pulse editing output is shown in FIG. 5, and the adjustment requirement of more Burst pulse numbers can be met by increasing the number of paths of a logic link of the same principle. The invention realizes the on-line adjustment of the Burst pulse width and the number.
The invention uses the circuit to realize the mode to replace the original function which can be stably realized by a plurality of optical modules, and has the expansibility of setting the number of pulse widths, the invention is extended to design and optimize, and more electric control methods can be derived.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A pulse drive circuit, comprising:
a delay circuit for delaying and outputting the initial phase pulse signal to generate a phase delay pulse signal;
and the and operation circuit is used for performing and operation on the initial phase pulse signal and the phase delay pulse signal or performing and operation on at least two paths of the phase delay pulse signals to obtain a narrow pulse width pulse signal.
2. A pulse drive circuit as claimed in claim 1, further comprising an or circuit that combines a plurality of said narrow pulse width pulse signals into a pulse train signal.
3. A pulse driving circuit according to claim 2, further comprising a signal distribution circuit for distributing the initial phase pulse signal into an initial phase first replica signal and an initial phase second replica signal;
the phase-delayed pulse signal is generated by the delay circuit delaying the initial phase first replica signal to output;
the AND operation circuit is used for performing AND operation on the initial phase first replica signal and the phase delay pulse signal.
4. A pulse drive circuit as defined in claim 1, further comprising a programmable circuit, the initial phase pulse signal being generated by the programmable circuit.
5. A pulse driving circuit as claimed in claim 4, wherein the delay circuit has an adjustable delay time, and the control signal for the delay time is generated by the programmable circuit.
6. The pulse driving circuit according to claim 4, wherein the AND operation circuit comprises a plurality of AND operation chips having enable terminals, and an enable signal is generated by the programmable circuit.
7. The pulse driving circuit as claimed in claim 6, wherein the and operation chip is a model number of SY10EP series.
8. The pulse driving circuit according to claim 6, wherein the initial phase pulse signal is a differential signal, the differential signal includes a positive signal and a negative signal, the and operation chip performs an and operation on each of the positive signals, and the and operation chip further performs an and operation on each of the negative signals.
9. The pulse drive circuit of claim 4 wherein the initial phase pulse signal comprises a first differential signal and a second differential signal generated by the programmable circuit, the pulse drive circuit further comprising a signal distribution circuit comprising a first differential fan-out buffer and a second differential fan-out buffer, the first differential fan-out buffer distributing the first differential signal into a first differential first replica signal, a first differential second replica signal, a first differential third replica signal, and a first differential fourth replica signal;
the second differential fan-out buffer distributes the second differential signal into a second differential first replica signal, a second differential second replica signal, a second differential third replica signal, and a second differential fourth replica signal;
the delay circuit comprises a first delay chip and a second delay chip, the first delay chip delays and outputs the first differential second replica signal to generate a first phase delay pulse signal, and the first delay chip also delays and outputs the second differential first replica signal to generate a second phase delay pulse signal;
the second delay chip delays and outputs the second differential fourth replica signal to generate a third phase delay pulse signal, and the second delay chip also delays and outputs the first differential third replica signal to generate a fourth phase delay pulse signal;
the AND operation circuit comprises a first AND operation chip, a second AND operation chip, a third AND operation chip and a fourth AND operation chip, wherein the first AND operation chip performs AND operation on the first differential first replica signal and the first phase delay pulse signal, the second AND operation chip performs AND operation on the second phase delay pulse signal and the second differential second replica signal, the third AND operation chip performs AND operation on the second differential third replica signal and the third phase delay pulse signal, and the fourth AND operation chip performs AND operation on the fourth phase delay pulse signal and the first differential fourth replica signal.
10. An ultrafast laser, comprising:
a pulse generator using the pulse drive circuit according to any one of claims 1 to 9;
a power amplifier which amplifies the pulse train signal into a pulse current;
a seed light generating device for generating seed light using the pulse current;
and the laser generating device generates ultrafast laser by utilizing the seed light.
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| CN212011593U (en) * | 2020-04-27 | 2020-11-24 | 厦门彼格科技有限公司 | Ultra-high-speed laser driving circuit with adjustable pulse width |
| CN113904210A (en) * | 2021-10-09 | 2022-01-07 | 深钛智能科技(苏州)有限公司 | Programmable ultrafast pulse laser generator |
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