CN114975648A - Solar cell, preparation method thereof and photovoltaic module - Google Patents
Solar cell, preparation method thereof and photovoltaic module Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 239000004065 semiconductor Substances 0.000 claims abstract description 73
- 238000002161 passivation Methods 0.000 claims abstract description 54
- 230000007423 decrease Effects 0.000 claims abstract description 41
- 230000002829 reductive effect Effects 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims description 31
- 230000008569 process Effects 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 238000013532 laser treatment Methods 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 239000008393 encapsulating agent Substances 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 abstract description 25
- 230000002349 favourable effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 214
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 22
- 229910052710 silicon Inorganic materials 0.000 description 22
- 239000010703 silicon Substances 0.000 description 22
- 238000009792 diffusion process Methods 0.000 description 20
- 229910052581 Si3N4 Inorganic materials 0.000 description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 16
- 230000003247 decreasing effect Effects 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000006798 recombination Effects 0.000 description 5
- 238000005215 recombination Methods 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 239000002390 adhesive tape Substances 0.000 description 4
- ILAHWRKJUDSMFH-UHFFFAOYSA-N boron tribromide Chemical compound BrB(Br)Br ILAHWRKJUDSMFH-UHFFFAOYSA-N 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000002313 adhesive film Substances 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 229910052755 nonmetal Inorganic materials 0.000 description 2
- -1 polyethylene octene Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 239000000806 elastomer Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000005038 ethylene vinyl acetate Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
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- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
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- H01L31/042—PV modules or arrays of single PV cells
- H01L31/048—Encapsulation of modules
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- Computer Hardware Design (AREA)
- Power Engineering (AREA)
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Abstract
The application relates to a solar cell, a preparation method thereof and a photovoltaic module, comprising the following steps: the semiconductor device comprises a semiconductor substrate, a first electrode and a second electrode, wherein the semiconductor substrate comprises a front surface and a back surface which are oppositely arranged; the grid line electrode group comprises a first front grid line electrode and a second front grid line electrode which are adjacently arranged, and the doping amount of the doped conducting layer is gradually reduced from the first front grid line electrode to the symmetrical central area of the first front grid line electrode and the second front grid line electrode; a back passivation layer and a back gate line electrode on the back of the semiconductor substrate. The doped conducting layer of the solar cell gradually rises from the symmetrical center region of the first front grid line electrode and the second front grid line electrode to the current of the first front grid line electrode, and the transmission resistance gradually decreases, so that the doped conducting layer is favorable for transverse transmission of the current in the doped conducting layer, the series resistance is reduced, and the cell efficiency is improved.
Description
[ technical field ] A method for producing a semiconductor device
The application relates to the technical field of solar photovoltaic modules, in particular to a solar cell, a preparation method of the solar cell and a photovoltaic module.
[ background of the invention ]
In crystalline silicon solar cells, a uniformly doped layer in contact with an electrode cannot meet two requirements simultaneously: on one hand, the light doping is needed to reduce Auger recombination and Shockley-Read-Hall recombination and improve the spectral response of short wave bands; on the other hand, heavy doping is needed to form high surface concentration, so that ohmic contact is formed between the silicon wafer and the metal electrode. Selective doping is often achieved using localized doping techniques to improve cell efficiency.
The local doping technology acts on the emitter, so that a Selective Emitter (SE) can be realized; the local doping technology acts on the back surface electric field, so that the local back surface electric field can be contacted with the local electrode, however, the existing selective emitter cannot well match the transmission requirement of current, the reduction of series resistance is limited, and the efficiency improvement of the solar cell is limited.
[ summary of the invention ]
In order to overcome the defects, the application provides the solar cell, the preparation method thereof and the photovoltaic module, which can improve the transverse transmission of current, reduce the series resistance and further improve the cell efficiency.
In a first aspect, an embodiment of the present application provides a solar cell, including:
the semiconductor device comprises a semiconductor substrate, a first electrode and a second electrode, wherein the semiconductor substrate comprises a front surface and a back surface which are oppositely arranged;
the grid line electrode group comprises a first front grid line electrode and a second front grid line electrode which are arranged adjacently, the doping amount of the doped conducting layer is gradually reduced from the first front grid line electrode to the symmetrical central area of the first front grid line electrode and the second front grid line electrode, and/or the doping amount of the doped conducting layer is gradually reduced from the second front grid line electrode to the symmetrical central area of the first front grid line electrode and the second front grid line electrode;
and the back passivation layer and the back grid line electrode are positioned on the back of the semiconductor substrate.
In combination with the first aspect, the doping concentration of the doped conductive layer decreases sequentially from the first front gate line electrode to the symmetric central regions of the first front gate line electrode and the second front gate line electrode, and/or the doping concentration of the doped conductive layer decreases sequentially from the second front gate line electrode to the symmetric central regions of the first front gate line electrode and the second front gate line electrode.
In combination with the first aspect, the thickness of the doped conductive layer decreases sequentially from the first front gate line electrode to the symmetric central regions of the first front gate line electrode and the second front gate line electrode, and/or the thickness of the doped conductive layer decreases sequentially from the second front gate line electrode to the symmetric central regions of the first front gate line electrode and the second front gate line electrode.
With reference to the first aspect, the heights of the front passivation layers sequentially decrease from the first front gate line electrode to the symmetric central regions of the first front gate line electrode and the second front gate line electrode, and/or the heights of the front passivation layers sequentially decrease from the second front gate line electrode to the symmetric central regions of the first front gate line electrode and the second front gate line electrode.
With reference to the first aspect, the doped conductive layer includes N doped conductive regions from the first front gate line electrode to the symmetric central regions of the first front gate line electrode and the second front gate line electrode, where N is greater than or equal to 3, and the lengths of the N doped conductive regions decrease sequentially from the first front gate line electrode to the symmetric central regions of the first front gate line electrode and the second front gate line electrode; and/or the lengths of the N doped conductive regions are sequentially decreased from the second front grid line electrode to the symmetrical central regions of the first front grid line electrode and the second front grid line electrode.
In combination with the first aspect, the doping element in the doped conductive layer includes at least one of boron, gallium, phosphorus, and arsenic.
With reference to the first aspect, the doped conductive layer has a doping concentration difference of 1E18cm -3 ～9E20cm -3 。
With reference to the first aspect, the doping concentration of the doped conductive layer at the bottom of the first front gate line electrode is 1E19cm -3 ～1E21cm -3 (ii) a And/or the doping concentration of the doped conducting layer at the bottom of the second front grating electrode is 1E19cm -3 ～1E21cm -3 。
In a second aspect, the present application provides a method for manufacturing a solar cell, comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a front surface and a back surface which are oppositely arranged;
forming a doped conducting layer and a front passivation layer on the front surface of the semiconductor substrate and forming a plurality of grid line electrode groups on the front passivation layer, wherein the grid line electrode groups comprise a first front grid line electrode and a second front grid line electrode which are arranged adjacently, the doping amount of the doped conducting layer is sequentially reduced from the first front grid line electrode to the symmetrical central regions of the first front grid line electrode and the second front grid line electrode, and/or the doping amount of the doped conducting layer is sequentially reduced from the second front grid line electrode to the symmetrical central regions of the first front grid line electrode and the second front grid line electrode;
and forming a back passivation layer and a back grid line electrode on the back of the semiconductor substrate.
With reference to the second aspect, after the forming of the doped conductive layer on the front surface of the semiconductor substrate and before the forming of the front passivation layer, the method further includes: and performing multiple laser treatments on the doped conducting layer to enable the thickness of the doped conducting layer to sequentially decrease from the first front grid line electrode to the symmetrical central regions of the first front grid line electrode and the second front grid line electrode, and/or performing multiple laser treatments on the doped conducting layer to enable the thickness of the doped conducting layer to sequentially decrease from the second front grid line electrode to the symmetrical central regions of the first front grid line electrode and the second front grid line electrode.
In combination with the second aspect, the doped conductive layer is formed by a mask process, such that the doping concentration of the doped conductive layer decreases sequentially from the first front gate line electrode to the symmetric central regions of the first front gate line electrode and the second front gate line electrode, and/or the doped conductive layer is formed by a mask process, such that the doping concentration of the doped conductive layer decreases sequentially from the second front gate line electrode to the symmetric central regions of the first front gate line electrode and the second front gate line electrode.
In a third aspect, an embodiment of the present application provides a photovoltaic module, which includes a cover plate, an encapsulant layer, and a solar cell string, where the solar cell string includes a plurality of solar cells described in the first aspect.
Compared with the prior art, the method has the following steps:
the doping amount of the doped conducting layer is gradually reduced from the symmetrical center regions of the first front grid line electrode and the second front grid line electrode, namely the doping regions of the first front grid line electrode and the symmetrical center regions of the first front grid line electrode and the second front grid line electrode are gradually weakened, so that the current of the doped conducting layer from the symmetrical center regions of the first front grid line electrode and the second front grid line electrode to the first front grid line electrode is gradually increased, the transmission resistance is gradually reduced, the transverse transmission of the current in the doped conducting layer is facilitated, the series resistance is reduced, and the battery efficiency is improved. Similarly, the doping amount of the doped conducting layer is gradually decreased from the second front grid line electrode to the symmetrical central regions of the first front grid line electrode and the second front grid line electrode, and the transverse transmission of current in the doped conducting layer can be facilitated, so that the series resistance is reduced, and the battery efficiency is improved. The solar cell can further realize gradient doping on the basis of realizing selective doping, and can remarkably improve the conversion efficiency of the solar cell.
Additional features and advantages of embodiments of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of embodiments of the present application. The objectives and other advantages of the embodiments of the application will be realized and attained by the structure particularly pointed out in the written description and drawings.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
FIG. 1 is a first schematic structural diagram of a solar cell of the present application;
FIG. 2 is a schematic structural diagram of a solar cell of the present application;
FIG. 3 is a third schematic structural view of a solar cell of the present application;
FIG. 4 is a schematic diagram of a doped conductive layer with varying thickness for a solar cell according to the present application;
FIG. 5 is a flow chart of the solar cell fabrication process of the present application;
FIG. 6 is a schematic structural diagram of a semiconductor substrate according to the present application;
FIG. 7 is a schematic structural diagram illustrating the formation of a heavily doped layer on a surface of a semiconductor substrate according to the present application;
FIG. 8 is a schematic structural diagram of a doped conductive layer with varying thickness prepared by laser thinning a heavily doped layer according to the present application;
FIG. 9 is a schematic structural diagram of a front passivation layer and a back passivation layer formed on the front and back surfaces of a semiconductor substrate according to the present application;
FIG. 10 is a schematic structural diagram of the present application for forming a doped conductive layer with varying doping concentrations;
fig. 11 is a schematic structural view of a photovoltaic module according to the present application.
Reference numerals:
1-a semiconductor substrate;
2-doping a conductive layer;
3-front passivation layer;
4-front grid line electrode group;
41-a first front gate line electrode;
42-a second front gate line electrode;
5-a back side passivation layer;
6-back grid line electrode;
7-heavily doped layer;
8-symmetrical central regions of the first front gate line electrode and the second front gate line electrode;
1000-a photovoltaic module;
100-solar cell;
200-a first cover plate;
300-a first encapsulation glue layer;
400-a second packaging glue layer;
500-second cover plate.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be noted that the terms "upper", "lower", "left", "right", and the like used in the embodiments of the present invention are described in terms of the drawings, and should not be construed as limiting the embodiments of the present invention. In addition, in this context, it will also be understood that when an element is referred to as being "on" or "under" another element, it can be directly on "or" under "the other element or be indirectly on" or "under" the other element via an intermediate element.
It should be noted that the steps shown in the flowcharts of the figures can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowcharts, the order of the steps of the embodiments is not limited to be executed in the order arranged in the present specification, and in some cases, the steps shown or described may be executed in an order different from the order shown or described according to specific needs.
In a crystalline silicon solar cell, a uniformly doped layer in contact with an electrode cannot simultaneously reduce recombination and improve ohmic contact between a silicon wafer and a metal electrode, and further, a selective emitter is developed, namely, a local doping technology is adopted to realize selective doping so as to improve the efficiency of the cell. According to the existing selective emitter, the doped conducting layer forms high doping in the metal electrode area, so that good ohmic contact is realized, series resistance is reduced, low doping is formed in the non-metal electrode area, auger recombination and Shockley-Read-Hall recombination are reduced, the spectral response of a short wave band is improved, and the efficiency of a battery is improved.
However, in the conventional selective emitter, a uniform low-doped region is formed in the non-metal electrode region, which cannot well match the current transmission requirement, so that the decrease of the series resistance is limited, and the efficiency also has a space for improving.
Therefore, in order to further improve the conversion efficiency of the solar cell, the present application proposes a solar cell, as shown in fig. 1, comprising:
the semiconductor device comprises a semiconductor substrate 1, wherein the semiconductor substrate 1 comprises a front surface and a back surface which are oppositely arranged;
the gate line electrode group 4 comprises a first front gate line electrode 41 and a second front gate line electrode 42 which are adjacently arranged, the doping amount of the doped conductive layer 2 is sequentially decreased from the first front gate line electrode 41 to a symmetrical central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, and/or the doping amount of the doped conductive layer 2 is sequentially decreased from the second front gate line electrode 42 to a symmetrical central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42;
a back passivation layer 5 and a back grid line electrode 6 positioned on the back of the semiconductor substrate 1.
In the above scheme, the doping amount of the doped conductive layer 2 is set to decrease from the first front gate line electrode 41 to the symmetric center region 8 of the first front gate line electrode 41 and the second front gate line electrode 42 in sequence, that is, the doped region from the first front gate line electrode 41 to the symmetric center region 8 of the first front gate line electrode 41 and the second front gate line electrode 42 is gradually weakened, so that the current of the doped conductive layer 2 from the symmetric center region 8 of the first front gate line electrode 41 and the second front gate line electrode 42 to the first front gate line electrode 41 is gradually increased, the transmission resistance is gradually reduced, thereby facilitating the transverse transmission of the current in the doped conductive layer 2, reducing the series resistance, and improving the battery efficiency. Similarly, the doping amount of the doped conductive layer 2 decreases gradually from the second front gate line electrode 42 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, which is also beneficial to the transverse transmission of current in the doped conductive layer 2, thereby reducing the series resistance and improving the battery efficiency. The solar cell can further realize gradient doping on the basis of realizing selective doping, and can remarkably improve the conversion efficiency of the solar cell.
It is to be understood that the central region 8 of symmetry of the first front gate line electrode 41 and the second front gate line electrode 42 refers to a region close to the axis of symmetry of the first front gate line electrode 41 and the second front gate line electrode 42. Preferably, the symmetric center region 8 of the first front gate line electrode 41 and the second front gate line electrode 42 refers to a region formed by the symmetric axes of the first front gate line electrode 41 and the second front gate line electrode 42.
In some embodiments, as shown in fig. 2, the doping amount of the doped conductive layer 2 decreases sequentially from the first front gate line electrode 41 to the symmetry axis of the first front gate line electrode 41 and the second front gate line electrode 42, and/or the doping amount of the doped conductive layer 2 decreases sequentially from the second front gate line electrode 42 to the symmetry axis of the first front gate line electrode 41 and the second front gate line electrode 42.
In this application, the solar cell of this application still includes a plurality of positive main grid lines that are located on the passivation layer of positive, and grid line electrode group 4 refers to the electrode group that two adjacent vice grid lines are constituteed, and main grid line and vice grid line meet perpendicularly mutually, and vice grid line collects the electric current and transmits to on the main grid line, and main grid line direct connection battery external lead.
The front surface of the semiconductor substrate 1 is a surface facing the sun (i.e., a light receiving surface), and the back surface of the semiconductor substrate 1 is a surface facing away from the sun (i.e., a backlight surface).
In some embodiments, the semiconductor substrate 1 is an N-type silicon substrate (or silicon wafer) and may also be a P-type silicon substrate (or silicon wafer), where the N-type silicon substrate is, for example, one of a polycrystalline silicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the P-type silicon substrate is, for example, one of a polycrystalline silicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the specific type of the semiconductor substrate 1 is not limited in the present embodiment.
In some embodiments, the thickness of the semiconductor substrate 1 is 60 μm to 240 μm, and may be 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm, 240 μm, or the like, which is not limited herein.
In some embodiments, an emitter (not shown in the drawings) may be formed on the surface of the doped conductive layer 2 as required. The emitter is a P-type emitter or an N-type emitter, when the semiconductor substrate 1 is an N-type silicon substrate, the emitter is a P-type emitter, and the P-type emitter is a boron-doped diffusion layer or a gallium-doped diffusion layer; when the semiconductor substrate 1 is a P-type silicon substrate, the emitter is an N-type emitter, the N-type emitter is a boron-doped diffusion layer or a gallium-doped diffusion layer, and the boron-doped diffusion layer, the gallium-doped diffusion layer, the boron-doped diffusion layer and the gallium-doped diffusion layer are emitters formed by diffusing doping source atoms to a certain depth on the front surface through a diffusion process by using corresponding doping sources. Illustratively, when fabricating the boron-doped diffusion layer, the dopant source may be liquid boron tribromide or boron trichloride.
In some embodiments, in the solar cell of the present application, the doping amount of the doped conductive layer 2 between the adjacent first front grid line electrode 41 and the second front grid line electrode 42 is first decreased and then increased. That is, the doping amount of the conductive doping layer 2 positioned at the bottom of the first front gate line electrode 41 or the conductive doping layer 2 positioned at the bottom of the second front gate line electrode 42 is the largest.
It is understood that the doped conductive layer 2 may also function as an emitter, and may also be formed inside the semiconductor substrate 1 as a whole with the semiconductor substrate 1, or of course may also be formed outside the semiconductor substrate 1 as a separate layer structure.
In some embodiments, in order to improve the transmission of current in the doped conductive layer, the doping amount of the region close to the gate line electrode needs to be larger, the doping amount of the region far away from the gate line electrode needs to be smaller, and the doped conductive layer can form a certain gradient, so as to facilitate the transmission of current, therefore, in order to meet the requirement of the doping amount, the present application is implemented in the following specific manner:
as shown in fig. 3, in the present application, the doping concentration of the doped conductive layer 2 is set to decrease gradually from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, so that the doped region of the doped conductive layer from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42 is gradually weakened, the total doping amount is gradually reduced, the current gradually increases, and the transmission resistance gradually decreases, thereby facilitating the transverse transmission of the current in the doped conductive layer 2, improving the fill factor, and further improving the battery efficiency. For the same reason, the doping concentration of the doped conductive layer 2 is sequentially decreased from the second front grid line electrode 42 to the symmetric central regions 8 of the first front grid line electrode 41 and the second front grid line electrode 42, so that the doping amount of the doped conductive layer 2 is sequentially decreased from the first front grid line electrode 41 to the symmetric central regions 8 of the first front grid line electrode 41 and the second front grid line electrode 42, thereby facilitating the transverse transmission of current in the doped conductive layer 2, improving the fill factor, and further improving the cell efficiency. Certainly, the doping concentration distribution of the doped conductive layer 2 is controlled at the same time, so that the doping concentration of the doped conductive layer 2 is reduced from the first front-surface gate line electrode 41 to the second front-surface electrode gate line 42 and then increased, that is, the transmission resistance of the symmetric central region between the first front-surface gate line electrode 41 and the second front-surface electrode gate line 42 is minimum, which is beneficial to transmitting current to the first front-surface gate line electrode 41 and the second front-surface electrode gate line 42, thereby improving the filling factor and further improving the battery efficiency. Of course, the central region 8 of symmetry of the first front gate line electrode 41 and the second front gate line electrode 42 may also be a symmetry axis of the first gate line electrode 41 and the second gate line electrode 42.
According to the method, the thickness of the doped conducting layer 2 is gradually reduced from the first front grid line electrode 41 to the symmetrical center region 8 of the first front grid line electrode 41 and the second front grid line electrode 42, so that the doping amount of the doped conducting layer 2 is gradually reduced from the first front grid line electrode 41 to the symmetrical center region 8 of the first front grid line electrode 41 and the second front grid line electrode 42, the transverse transmission of current in the doped conducting layer 2 is facilitated, the filling factor is improved, and the battery efficiency is improved. Illustratively, as shown in fig. 4, the thicknesses of the doped conductive layer 2 are L1, L2 and L3 in sequence from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, and L1 > L2 > L3, so that the doping amount of the doped conductive layer 2 decreases in sequence from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42. For the same reason, the thickness of the doped conductive layer 2 is controlled to decrease from the second front gate line electrode 42 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, so that the transverse transmission of the current in the doped conductive layer 2 is improved, the fill factor is improved, and the cell efficiency is further improved. Certainly, the thickness distribution of the doped conductive layer 2 is controlled at the same time, so that the thickness of the doped conductive layer 2 is reduced from the first front gate line electrode 41 to the second front gate line 42 and then increased, the doping amount of the symmetric central region from the first front gate line electrode 41 to the second front gate line is the minimum, that is, the transmission resistance is the minimum, and the current is favorably transmitted to the first front gate line electrode 41 and the second front gate line 42, thereby improving the filling factor and further improving the battery efficiency.
In some embodiments, when the thickness of the doped conductive layer 2 decreases sequentially from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, since the front passivation layer 3 is disposed on the surface of the doped conductive layer 2, the height of the front passivation layer 3 decreases sequentially from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, that is, the front passivation layer 3 has a certain gradient height; when the thickness of the doped conductive layer 2 decreases sequentially from the second front gate line electrode 42 to the symmetric central regions 8 of the first front gate line electrode 41 and the second front gate line electrode 42, the height of the front passivation layer 3 decreases sequentially from the second front gate line electrode 42 to the symmetric central regions 8 of the first front gate line electrode 41 and the second front gate line electrode 42.
It can be understood that, in the present application, the thickness gradient change of the doped conductive layer 2 is set, the doping concentration change of the doped conductive layer 2 is set singly, or the two types of combinations can be set, so that the doping amount of the doped conductive layer 2 is first reduced and then increased from the first front surface gate line electrode 41 to the second front surface electrode gate line 42, and the doping amount of the symmetric central region 8 of the first front surface gate line electrode 41 to the second front surface electrode gate line is the minimum.
In some embodiments, the doping element in the doped conductive layer 2 comprises at least one of boron, gallium, phosphorus and arsenic. When the semiconductor substrate 1 is an N-type substrate, the doping element in the doped conductive layer 2 includes at least one of boron and gallium; when the semiconductor substrate 1 is a P-type substrate, the doping element in the doped conductive layer 2 includes at least one of phosphorus and arsenic.
In some embodiments, the doped conductive layer 2 has a doping concentration difference of 1E18cm -3 ～9E20cm -3 For example, it may be 1E18cm -3 、5E18cm -3 、1E19cm -3 、5E19cm -3 、1E20cm -3 、5E20cm -3 And 9E20cm -3 The doping concentration difference of the doped conducting layer 2 is controlled within the range, so that the current and the open voltage are improved, and the transverse resistance loss is ensured to be small.
In some embodiments, the doping concentration of the doped conductive layer 2 at the bottom of the first front gate line electrode 41 is 1E19cm -3 ～1E21cm -3 For example, it may be 1E19cm -3 、5E19cm -3 、1E20cm -3 、5E20cm -3 And 1E21cm -3 The doping concentration of the doped conductive layer 2 on the second front grid line electrode 42 is 1E19cm -3 ～1E 21cm -3 For example, it may be 1E19cm -3 、5E19cm -3 、1E20cm -3 、5E20cm -3 And 1E21cm -3 By controlling the doping concentration of the doped conducting layer 2 at the grid line electrode within the range, the doped conducting layer 2 between the semiconductor substrate 1 and the grid line electrode is ensured to be heavily doped, so that the semiconductor substrate 1 and the grid line electrode are in good ohmic contact.
In some embodiments, the front passivation layer 3 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and the like, or any combination thereof, and the front passivation layer 3 can generate a good passivation effect on the semiconductor substrate 1, which can help to improve the conversion efficiency of the battery. It should be noted that the front passivation layer 3 may also function to reduce reflection of incident light, and in some examples, may also be referred to as an anti-reflection layer.
In some embodiments, the thickness of the front passivation layer 3 ranges from 10nm to 120nm, and specifically may be 10nm, 20nm, 30nm, 42nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, or 120nm, and may also be other values within the above range, which is not limited herein.
In some embodiments, the back passivation layer 5 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like, or any combination thereof. When the back passivation layer 5 is a stacked silicon nitride layer and a stacked silicon oxide layer or a stacked silicon nitride layer and a stacked silicon oxynitride layer, the silicon nitride layer is located on the surface of the doped conductive layer, and the silicon oxide layer or the silicon oxynitride layer is located on the surface of the silicon nitride layer.
In some embodiments, the thickness of the back gate line electrode 6 is in a range of 70nm to 120nm, specifically 70nm, 80nm, 90nm, 100nm, or 120nm, and may be other values within the above range, which is not limited herein.
In some embodiments, the front gate line electrode group 4 and the back gate line electrode group 6 are both metal gate line electrodes, and the material of the metal gate line electrodes includes at least one of copper, silver, aluminum, and nickel.
The back grid line electrode 6 includes a main grid line and an auxiliary grid line, the auxiliary grid line is connected with the main grid line, the auxiliary grid line is used for collecting current generated by the solar cell, and the main grid line is used for collecting current on the auxiliary grid line.
In some embodiments, the plurality of bus bars are equally spaced, so that each bus bar collects a more uniform current.
The present application further provides a method for manufacturing the solar cell, please refer to fig. 5, which is a flowchart of the method for manufacturing the solar cell of the present application, and the method includes the following steps:
providing a semiconductor substrate 1, wherein the semiconductor substrate 1 comprises a front surface and a back surface which are oppositely arranged;
forming a doped conductive layer 2 and a front passivation layer 3 on the front surface of the semiconductor substrate 1, and forming a plurality of gate line electrode sets 4 on the front passivation layer 3, wherein the gate line electrode sets 4 include a first front gate line electrode 41 and a second front gate line electrode 42 which are adjacently arranged, the doping amount of the doped conductive layer 2 is sequentially decreased from the first front gate line electrode 41 to a symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, and/or the doping amount of the doped conductive layer 2 is sequentially decreased from the second front gate line electrode 42 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42;
a back passivation layer 5 and a back gate line electrode 6 are formed on the back surface of the semiconductor substrate 1.
In the above scheme, the doping amount of the doped conductive layer 2 is set to decrease gradually from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, that is, the doping regions from the first front gate line electrode 41 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42 are gradually weakened, the total doping amount is gradually reduced, the current is gradually increased, and the transmission resistance is gradually reduced, so that the transverse transmission of the current in the doped conductive layer 2 is facilitated, the series resistance is reduced, and the battery efficiency is improved. Similarly, the doping amount of the doped conductive layer 2 decreases from the second front gate line electrode 42 to the symmetric central region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, which is also beneficial to the transverse transmission of current in the doped conductive layer 2, thereby reducing the series resistance and improving the battery efficiency. The solar cell can further realize gradient doping on the basis of realizing selective doping, and can remarkably improve the conversion efficiency of the solar cell.
In some embodiments, the front surface of the semiconductor substrate 1 is a surface facing the sun (i.e., a light receiving surface), and the back surface of the semiconductor substrate 1 is a surface facing away from the sun (i.e., a backlight surface).
Hereinafter, a method for manufacturing a solar cell according to the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments.
Step S100, referring to fig. 6, providing a semiconductor substrate 1;
in some embodiments, the semiconductor substrate 1 is an N-type silicon substrate or a P-type silicon substrate, and the silicon substrate may be a crystalline silicon substrate (silicon substrate), such as one of a polycrystalline silicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the specific type of the semiconductor substrate is not limited in the examples of the present application.
In some embodiments, the front and back surfaces of the semiconductor substrate 1 may be textured to form a textured or surface texture (e.g., pyramid structure). The texturing processing may be chemical etching, laser etching, mechanical method, plasma etching, and the like, and is not limited herein. Illustratively, the front and back surfaces of the semiconductor substrate 1 may be subjected to a texturing process using a NaOH solution, and thus a pyramid textured structure may be prepared due to anisotropy of the etching of the NaOH solution.
It can be understood that the surface of the semiconductor substrate 1 has a textured structure through texturing, so that a light trapping effect is generated, the light absorption quantity of the solar cell is increased, and the conversion efficiency of the solar cell is improved.
In some embodiments, before the texturing process, a step of cleaning the semiconductor substrate 1 may be further included to remove metal and organic contaminants from the surface.
In some embodiments, the emitter may be formed on the front surface of the semiconductor substrate 1 by any one or more of high temperature diffusion, slurry doping, or ion implantation. Specifically, the emitter is formed by diffusing boron atoms through a boron source. In some embodiments, the emitter is designed as a selective emitter structure. The boron source may be, for example, diffusion treated with boron tribromide, to transform the microcrystalline silicon phase of the crystalline silicon into a polycrystalline silicon phase. Since the surface of the semiconductor substrate 1 has a high concentration of boron, a borosilicate glass (BSG) layer is usually formed, and the BSG layer has a metal gettering effect, which may affect the normal operation of the solar cell and requires subsequent removal.
In step S201, as shown in fig. 7, a heavily doped layer 7 is formed on the front surface of the semiconductor substrate 1.
In some embodiments, the present application is not limited to the specific operation of forming the heavily doped layer 7. Illustratively, a conductive layer may be deposited on the surface of the semiconductor substrate 1 by any one of a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, and an atmospheric pressure chemical vapor deposition method, and then the conductive layer may be heavily doped to form the heavily doped layer 7.
In some embodiments, the heavily doped layer 7 may be formed by an in-situ doping process performed while the conductive layer is deposited.
In some embodiments, the heavily doped layer 7 has a doping concentration of 1E19cm -3 ～1E21cm -3 For example, it may be 1E19cm -3 、5E19cm -3 、1E20cm -3 、5E20cm -3 And 1E21cm -3 。
Step 202, processing the heavily doped layer 7 by adopting a multiple laser thinning processing technology, and converting the heavily doped layer 7 into the doped conducting layer 2, specifically:
dividing the heavily doped layer 7 into regions, so that the heavily doped layer 7 is divided into N regions from a preset first front gate line electrode 41 to a symmetrical center region 8 of the preset first front gate line electrode 41 and the preset second front gate line electrode 42, where N is greater than or equal to 3, which are regions 1, 2, and 3, … … N, and performing laser thinning treatment from the region 1 to the region N, respectively, to obtain a doped conductive layer 2, as shown in fig. 8, the thickness of the doped conductive layer 2 is sequentially decreased from the preset first front gate line electrode 41 to the symmetrical center region 8 of the first front gate line electrode 41 and the second front gate line electrode 42, so that the doping amount of the doped conductive layer 2 is sequentially decreased from the preset first front gate line electrode 41 to the symmetrical center region of the preset first front gate line electrode 41 and the preset second front gate line electrode 42; similarly, the heavily doped layer 7 is partitioned into M regions, where M is greater than or equal to 3 and is a region … … M from the region 1 to the region M, respectively, so as to obtain the doped conductive layer 2, and the thickness of the doped conductive layer 2 is gradually decreased from the predetermined second front gate line electrode 42 to the symmetric central region 8 of the predetermined first front gate line electrode 41 and the predetermined second front gate line electrode 42.
It is understood that the presetting of the first front gate line electrode 41 and the presetting of the second front gate line electrode 42 refer to positions of the gate line electrodes which are preset. I.e. the dashed lines of the first front gate line electrode 41 and the second front gate line electrode 42 in fig. 8, no gate line electrode has been actually formed in this step.
In some embodiments, the laser for the laser thinning process includes a laser with a wavelength of 200nm to 600nm, and the laser includes at least one of green light and ultraviolet light, but may also be a laser with other wavelength ranges, and is not limited herein.
In some embodiments, the laser frequency of the local laser processing is 100KHz to 1000KHz, and specifically may be 100KHz, 200KHz, 300KHz, 400KHz, 500KHz, 600KHz, 700KHz, 800KHz, 900KHz, and 1000 KHz.
In some embodiments, the integrated laser energy of the local laser treatment is 100w cm -2 ～100000w*cm -2 For example, it may be 100w cm -2 、500w*cm -2 、1000w*cm -2 、3000w*cm -2 、5000w*cm -2 、10000w*cm -2 、50000w*cm -2 And 100000w cm -2 。
It is understood that the type of laser and the laser intensity can be adjustedThe frequency of light, the energy of laser and the time of laser treatment are such that the thickness of the doped conductive layer 2 is graded such that the doped concentration difference of the doped conductive layer is 1E18cm -3 ～9E20cm -3 。
Step 203, as shown in fig. 9, a front passivation layer 3 and a back passivation layer 5 are formed on the surface of the doped conductive layer 2.
In some embodiments, the front passivation layer 3 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like, or any combination thereof. The front passivation layer 3 can generate a good passivation effect on the semiconductor substrate 1, and is helpful for improving the conversion efficiency of the cell. It should be noted that the front passivation layer 3 may also function to reduce reflection of incident light, and in some examples, may also be referred to as an anti-reflection layer.
In some embodiments, the thickness of the front passivation layer 3 ranges from 10nm to 120nm, and specifically may be 10nm, 20nm, 30nm, 42nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, or 120nm, and may also be other values within the above range, which is not limited herein.
In some embodiments, the back passivation layer 5 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like, or any combination thereof.
For example, the back passivation layer 5 is made of silicon nitride, the silicon nitride thin film layer can function as an antireflection film, the silicon nitride thin film has good insulation, compactness and stability and can mask impurity ions, and the silicon nitride thin film layer can passivate the semiconductor substrate 1, so that the photoelectric conversion efficiency of the solar cell is obviously improved.
In some embodiments, the thickness of the back passivation layer 5 is in a range of 70nm to 120nm, specifically 70nm, 80nm, 90nm, 100nm, or 120nm, and may be other values within the above range, which is not limited herein.
In some embodiments, when the back passivation layer 5 is a stacked silicon nitride layer and silicon oxide layer or a stacked silicon nitride layer and silicon oxynitride layer, the silicon nitride layer is located on the surface of the semiconductor substrate 1, and the silicon oxide layer or the silicon oxynitride layer is located on the surface of the silicon nitride layer.
Step S204, a back gate line electrode 6 penetrating through the back passivation layer 5 and making contact with the semiconductor substrate 1, and a plurality of gate line electrode groups 4 penetrating through the surface of the front passivation layer 3 and making contact with the doped conductive layer 2.
In some embodiments, the front main gate lines and the front sub-gate lines are printed on the front surface of the semiconductor substrate 1 by using a paste, and dried to form corresponding front gate line electrode groups, the back main gate lines and the back sub-gate lines are printed on the back surface of the semiconductor substrate 1 by using a paste, and dried to form corresponding back gate line electrodes, and finally the dried cell is sintered to obtain the solar cell, wherein the structure of the solar cell is as shown in fig. 1.
In the embodiment of the present application, the specific material of the front gate line electrode group and the back gate line electrode is not limited. For example, the front gate line electrode is a silver electrode or a silver/aluminum electrode, and the back gate line electrode is a silver electrode or a silver/aluminum electrode.
In the present application, unless otherwise stated, the individual operation steps may or may not be performed in sequence. The step sequence for preparing the solar cell is not limited in the embodiment of the application, and can be adjusted according to the actual production process.
The present application also provides another method for manufacturing a solar cell, which is different from the above-mentioned method for manufacturing, the step 200 includes the following steps:
step S201, performing a diffusion process on the front surface of the semiconductor substrate 1 by using a mask method to obtain the doped conductive layer 2, and sequentially decreasing the doping concentration of the doped conductive layer 2 from the first front surface gate line electrode 41 to the symmetric central region 8 of the first front surface gate line electrode 41 and the second front surface gate line electrode 42; and/or the doping concentration of the doped conductive layer 2 decreases from the second front grid electrode 42 to the symmetrical center region 8 of the first front grid electrode 41 and the second front grid electrode 42.
Specifically, for the front surface division region of the semiconductor substrate 1, sequentially performing diffusion treatment on each region from the position where the first front surface gate line electrode 41 is preset to the direction of the symmetric center region 8 where the first front surface gate line electrode 41 and the second front surface gate line electrode 42 are preset, forming a masking layer in advance for the non-diffused region, in the diffusion process, the concentration of the doping source for diffusion process is sequentially reduced from the preset first front gate line electrode 41 to the direction of the symmetric center region 8 of the preset first front gate line electrode 41 and the preset second front gate line electrode 42, after the diffusion process is completed, the masking layer is removed to obtain the doped conductive layer 2, as shown in fig. 10, the doping concentration of the doped conductive layer 2 decreases from the predetermined first front gate line electrode 41 to the symmetric central region 8 of the predetermined first front gate line electrode 41 and the second front gate line electrode 42.
Further, in the direction from the preset second front gate line electrode 42 to the symmetrical center region 8 of the preset first front gate line electrode 41 and the preset second front gate line electrode 42, the diffusion process may be performed on each region in sequence, a masking layer is formed in advance in the non-diffused region, and in the process of the diffusion process, the doping concentration decreases in sequence from the preset second front gate line electrode 42 to the symmetrical center region 8 of the preset first front gate line electrode 41 and the preset second front gate line electrode 42, and after the diffusion process is completed, the masking layer is removed to obtain the doped conductive layer 2, as shown in fig. 10, the doping concentration of the doped conductive layer 2 decreases first from the first front gate line electrode 41 to the second front gate line 42 and then increases, that is, the transmission resistance of the symmetrical center region of the first front gate line electrode 41 to the second front gate line electrode is the smallest, thereby facilitating the transmission of the current to the first front gate line electrode 41 and the second front gate line 42, thereby improving the fill factor and further improving the battery efficiency.
Step S202, a front passivation layer 3 and a back passivation layer 5 are formed on the surface of the doped conducting layer 2.
Step S203, a back gate line electrode 6 penetrating through the back passivation layer 5 and making contact with the semiconductor substrate 1, and a plurality of gate line electrode groups 4 penetrating through the surface of the front passivation layer 3 and making contact with the doped conductive layer 2.
In a third aspect, a photovoltaic module 1000 includes a string of solar cells as described above formed by electrical connections.
Specifically, referring to fig. 11, the photovoltaic module 1000 includes a first cover plate 200, a first encapsulant layer 300, a solar cell string, a second encapsulant layer 400, and a second cover plate 500.
In some embodiments, the solar cell string includes a plurality of solar cells 100 connected by conductive tapes, and the connection manner between the solar cells 100 may be partial lamination or splicing.
In some embodiments, the first cover plate 200 and the second cover plate 500 may be transparent or opaque cover plates, such as glass cover plates and plastic cover plates.
The two sides of the first packaging adhesive layer 300 are respectively contacted and attached with the first cover plate 200 and the battery string, and the two sides of the second packaging adhesive layer 400 are respectively contacted and attached with the second cover plate 500 and the battery string. The first and second adhesive layers 300 and 400 may be ethylene-vinyl acetate (EVA) adhesive films, polyethylene octene co-elastomer (POE) adhesive films, or polyethylene terephthalate (PET) adhesive films, respectively.
The photovoltaic module 1000 may also be encapsulated in a side-edge-all-around manner, that is, the side edge of the photovoltaic module 1000 is encapsulated by an encapsulation tape, so as to prevent the photovoltaic module 1000 from generating a lamination offset phenomenon during the lamination process.
The photovoltaic module 1000 further includes an edge sealing member, which is fixedly sealed to a portion of the edge of the photovoltaic module 1000. The edge sealing member may be fixedly sealed to the edge of the photovoltaic module 1000 near the corner. The edge sealing member may be a high temperature resistant tape. The high-temperature-resistant adhesive tape has excellent high-temperature-resistant characteristic, cannot be decomposed or fall off in the laminating process, and can ensure reliable packaging of the photovoltaic module 1000. Wherein, two ends of the high temperature resistant adhesive tape are respectively fixed on the second cover plate 500 and the first cover plate 200. The two ends of the high-temperature-resistant adhesive tape can be respectively bonded with the second cover plate 500 and the first cover plate 200, and the middle part of the high-temperature-resistant adhesive tape can limit the side edge of the photovoltaic module 1000, so that the photovoltaic module 1000 is prevented from laminating and deviating in the laminating process.
In some embodiments, the photovoltaic module 1000 further includes a frame (the frame is not shown in fig. 11), the frame may be made of an aluminum alloy material or a stainless steel material, and when the frame is made of an aluminum alloy material, the strength and the corrosion resistance of the frame are very good. The frame can play the effect of supporting and protecting whole panel. The photovoltaic modules can also be connected to the outside photovoltaic support through the frame, and the photovoltaic modules can be connected with each other to jointly form a photovoltaic power station.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions, improvements, etc. within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (11)
1. A solar cell, comprising:
the semiconductor device comprises a semiconductor substrate, a first electrode and a second electrode, wherein the semiconductor substrate comprises a front surface and a back surface which are oppositely arranged;
the grid line electrode group comprises a first front grid line electrode and a second front grid line electrode which are arranged adjacently, the doping amount of the doped conducting layer is gradually reduced from the first front grid line electrode to the symmetrical central area of the first front grid line electrode and the second front grid line electrode, and/or the doping amount of the doped conducting layer is gradually reduced from the second front grid line electrode to the symmetrical central area of the first front grid line electrode and the second front grid line electrode;
and the back passivation layer and the back grid line electrode are positioned on the back of the semiconductor substrate.
2. The solar cell of claim 1, wherein the doping concentration of the doped conductive layer decreases sequentially from the first front grid line electrode to the symmetric central region of the first front grid line electrode and the second front grid line electrode, and/or the doping concentration of the doped conductive layer decreases sequentially from the second front grid line electrode to the symmetric central region of the first front grid line electrode and the second front grid line electrode.
3. The solar cell of claim 1, wherein the thickness of the doped conductive layer decreases sequentially from the first front grid line electrode to the symmetric central region of the first front grid line electrode and the second front grid line electrode, and/or the thickness of the doped conductive layer decreases sequentially from the second front grid line electrode to the symmetric central region of the first front grid line electrode and the second front grid line electrode.
4. The solar cell of claim 3, wherein the height of the front passivation layer decreases sequentially from the first front grid electrode to the symmetric central region of the first and second front grid electrodes, and/or the height of the front passivation layer decreases sequentially from the second front grid electrode to the symmetric central region of the first and second front grid electrodes.
5. The solar cell of claim 1, wherein the doping element in the doped conductive layer comprises at least one of boron, gallium, phosphorus, and arsenic.
6. The solar cell of claim 1, wherein the doped conductive layers have a doping concentration difference of 1E18cm -3 ～9E20cm -3 。
7. The solar cell of claim 1, wherein the doping concentration of the doped conductive layer at the bottom of the first front grid line electrode is 1E19cm -3 ～1E21 cm -3 (ii) a And/or the doping concentration of the doped conducting layer at the bottom of the second front grid line electrode is 1E19cm -3 ～1E21 cm -3 。
8. A method for manufacturing a solar cell, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a front surface and a back surface which are oppositely arranged;
forming a doped conducting layer and a front passivation layer on the front surface of the semiconductor substrate and forming a plurality of grid line electrode groups on the front passivation layer, wherein the grid line electrode groups comprise a first front grid line electrode and a second front grid line electrode which are arranged adjacently, the doping amount of the doped conducting layer is sequentially reduced from the first front grid line electrode to the symmetrical central regions of the first front grid line electrode and the second front grid line electrode, and/or the doping amount of the doped conducting layer is sequentially reduced from the second front grid line electrode to the symmetrical central regions of the first front grid line electrode and the second front grid line electrode;
and forming a back passivation layer and a back grid line electrode on the back of the semiconductor substrate.
9. The method according to claim 8, further comprising, after forming the doped conductive layer on the front surface of the semiconductor substrate and before forming a front passivation layer: and performing multiple laser treatments on the doped conducting layer to enable the thickness of the doped conducting layer to sequentially decrease from the first front grid line electrode to the symmetrical central regions of the first front grid line electrode and the second front grid line electrode, and/or performing multiple laser treatments on the doped conducting layer to enable the thickness of the doped conducting layer to sequentially decrease from the second front grid line electrode to the symmetrical central regions of the first front grid line electrode and the second front grid line electrode.
10. The method according to claim 8, wherein the doped conductive layer is formed by a mask process such that the doping concentration of the doped conductive layer decreases from the first front gate line electrode to the symmetric center regions of the first front gate line electrode and the second front gate line electrode, and/or the doped conductive layer is formed by a mask process such that the doping concentration of the doped conductive layer decreases from the second front gate line electrode to the symmetric center regions of the first front gate line electrode and the second front gate line electrode.
11. A photovoltaic module comprising a cover sheet, a layer of encapsulant material, a string of solar cells comprising a plurality of solar cells according to any of claims 1 to 7 or prepared according to any of the preparation methods of claims 8 to 10.
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Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030146372A1 (en) * | 2002-02-05 | 2003-08-07 | Tzu-Chiang Hsish | Camera with MOS or CMOS sensor array |
| CN102386265A (en) * | 2010-09-06 | 2012-03-21 | Lg电子株式会社 | Solar cell module |
| KR101130193B1 (en) * | 2010-12-07 | 2012-03-30 | 엘지전자 주식회사 | Solar cell |
| CN102544135A (en) * | 2010-12-27 | 2012-07-04 | Lg电子株式会社 | Solar cell and method for manufacturing the same |
| US20120184063A1 (en) * | 2011-01-14 | 2012-07-19 | Indo Chung | Method for manufacturing solar cell |
| CN102986042A (en) * | 2010-06-18 | 2013-03-20 | 弗劳恩霍弗实用研究促进协会 | Method for producing a photovoltaic solar cell |
| CN103296093A (en) * | 2012-02-23 | 2013-09-11 | Lg电子株式会社 | Solar cell and method for manufacturing the same |
| CN103378185A (en) * | 2012-04-17 | 2013-10-30 | Lg电子株式会社 | Solar cell and method for manufacturing the same |
| US20140034123A1 (en) * | 2012-08-01 | 2014-02-06 | Solarworld Innovations Gmbh | Solar cell and method of manufacturing |
| CN106133918A (en) * | 2014-03-07 | 2016-11-16 | 法国原子能及替代能源委员会 | The method manufacturing selective doping photovoltaic cell |
| DE102017102296A1 (en) * | 2017-02-07 | 2018-08-09 | Hanwha Q Cells Gmbh | Solar cell production process, solar cell semifinished product and solar cell |
| CN113838941A (en) * | 2021-11-23 | 2021-12-24 | 浙江爱旭太阳能科技有限公司 | Selective passivation contact structure of solar cell and double-sided solar cell |
| CN114068729A (en) * | 2021-11-23 | 2022-02-18 | 浙江爱旭太阳能科技有限公司 | Double-sided back contact solar cell and back structure thereof |
| CN114203850A (en) * | 2020-09-01 | 2022-03-18 | 嘉兴阿特斯技术研究院有限公司 | Heterojunction solar cell and method for manufacturing same |
-
2022
- 2022-06-28 CN CN202210751677.3A patent/CN114975648B/en active Active
- 2022-06-28 CN CN202410064739.2A patent/CN117936600A/en active Pending
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030146372A1 (en) * | 2002-02-05 | 2003-08-07 | Tzu-Chiang Hsish | Camera with MOS or CMOS sensor array |
| CN1679164A (en) * | 2002-08-27 | 2005-10-05 | 伊弗克斯公司 | Photoconductor on active pixel image sensor |
| CN102986042A (en) * | 2010-06-18 | 2013-03-20 | 弗劳恩霍弗实用研究促进协会 | Method for producing a photovoltaic solar cell |
| CN102386265A (en) * | 2010-09-06 | 2012-03-21 | Lg电子株式会社 | Solar cell module |
| KR101130193B1 (en) * | 2010-12-07 | 2012-03-30 | 엘지전자 주식회사 | Solar cell |
| CN102544135A (en) * | 2010-12-27 | 2012-07-04 | Lg电子株式会社 | Solar cell and method for manufacturing the same |
| US20120184063A1 (en) * | 2011-01-14 | 2012-07-19 | Indo Chung | Method for manufacturing solar cell |
| CN103296093A (en) * | 2012-02-23 | 2013-09-11 | Lg电子株式会社 | Solar cell and method for manufacturing the same |
| CN103378185A (en) * | 2012-04-17 | 2013-10-30 | Lg电子株式会社 | Solar cell and method for manufacturing the same |
| US20140034123A1 (en) * | 2012-08-01 | 2014-02-06 | Solarworld Innovations Gmbh | Solar cell and method of manufacturing |
| CN106133918A (en) * | 2014-03-07 | 2016-11-16 | 法国原子能及替代能源委员会 | The method manufacturing selective doping photovoltaic cell |
| DE102017102296A1 (en) * | 2017-02-07 | 2018-08-09 | Hanwha Q Cells Gmbh | Solar cell production process, solar cell semifinished product and solar cell |
| CN114203850A (en) * | 2020-09-01 | 2022-03-18 | 嘉兴阿特斯技术研究院有限公司 | Heterojunction solar cell and method for manufacturing same |
| CN113838941A (en) * | 2021-11-23 | 2021-12-24 | 浙江爱旭太阳能科技有限公司 | Selective passivation contact structure of solar cell and double-sided solar cell |
| CN114068729A (en) * | 2021-11-23 | 2022-02-18 | 浙江爱旭太阳能科技有限公司 | Double-sided back contact solar cell and back structure thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116093191A (en) * | 2023-03-01 | 2023-05-09 | 浙江晶科能源有限公司 | Solar cell and photovoltaic module |
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