CN114975410A - Double-layer stacked 3D fan-out type packaging structure and packaging method thereof - Google Patents

Double-layer stacked 3D fan-out type packaging structure and packaging method thereof Download PDF

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Publication number
CN114975410A
CN114975410A CN202110194401.5A CN202110194401A CN114975410A CN 114975410 A CN114975410 A CN 114975410A CN 202110194401 A CN202110194401 A CN 202110194401A CN 114975410 A CN114975410 A CN 114975410A
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China
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layer
metal
semiconductor chip
wiring
chip
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Inventor
陈彦亨
林正忠
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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Priority to CN202110194401.5A priority Critical patent/CN114975410A/en
Priority to US17/564,121 priority patent/US11973070B2/en
Publication of CN114975410A publication Critical patent/CN114975410A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention provides a double-layer stacked 3D fan-out type packaging structure and a preparation method thereof, wherein the structure comprises the following steps: the packaging structure comprises a first semiconductor chip, a plastic packaging material layer, a metal connecting column, a first rewiring layer, a second semiconductor chip, a solder ball bump and an underfill layer. The formed packaging structure can package two layers of fan-out type wafers in the three-dimensional direction, a single cut packaging body is provided with two layers of semiconductor chips in the three-dimensional direction, and the control of electric signals of all the semiconductor chips in the single packaging body is realized by arranging a first rewiring layer, a metal connecting column and a second rewiring layer, so that more chips are packaged in the single packaging body, the packaging integrity is improved, and the packaging volume is reduced; moreover, a plurality of chips are packaged in the same packaging body, so that the efficiency of a single chip can be effectively improved; finally, the fabrication method also provides the possibility of packaging more than three layers of fan-out wafers in a single package.

Description

Double-layer stacked 3D fan-out type packaging structure and packaging method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a double-layer stacked 3D fan-out type packaging structure and a packaging method thereof.
Background
Lower cost, more reliable, faster, and higher density circuits are sought after goals for integrated circuit packaging. In the future, integrated circuit packages will increase the integration density of various electronic components by continually reducing the minimum feature size. Currently, advanced packaging methods include: wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Packaging (Fan-Out Wafer Level Packaging, FOWLP), Flip Chip (Flip Chip), stack on Packaging (POP), and the like.
The fan-out wafer level package is an embedded chip packaging method for wafer level processing, and is one of the advanced packaging methods with more input/output ports (I/O) and better integration flexibility. Fan-out wafer level packaging has its unique advantages over conventional wafer level packaging: I/O space is flexible and does not depend on chip size; only using effective bare chip (die), the yield of product is improved; the flexible 3D packaging path is provided, namely, any array pattern can be formed on the top; fourthly, the electric performance and the thermal performance are better; high-frequency application; sixthly, it is easy to realize high-density wiring in a redistribution layer (RDL).
Currently, most of fan-out wafer level packages are single layer packages, that is, a fan-out chip wafer is packaged on a carrier, and the conventional process includes: providing a carrier, and forming an adhesive layer on the surface of the carrier; mounting the semiconductor chip on the surface of the adhesive layer with the front side facing upwards; coating a dielectric layer; photoetching and electroplating to obtain a redistribution layer (RDL); plastic packaging the semiconductor chip in the plastic packaging material layer by adopting an injection molding process; plastic packaging, grinding and opening; photoetching and electroplating to obtain a metal layer below the ball; performing ball-planting reflow to form a solder ball array; the carrier is removed. The wafer packaging body formed by adopting the packaging method only comprises one chip in a single chip packaging body formed after cutting, and under the current requirement of a higher-density circuit, the circuit interconnection among a plurality of chips needs to be packaged again by packaging a plurality of packaged chip packaging bodies, so that the integration is low, the packaging volume is large, and the efficiency of the single chip is influenced.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a dual-stacked 3D fan-out package structure and a packaging method thereof, which are used to solve the problems of low integration, large package volume, and influence on the performance of a single chip in the fan-out wafer level package in the prior art.
To achieve the above and other related objects, the present invention provides a dual-stacked 3D fan-out package structure, comprising:
a first semiconductor chip;
the plastic packaging material layer comprises a first surface and a second surface which are opposite, and is in plastic packaging on the periphery of the first semiconductor chip;
the metal connecting column is positioned in the plastic packaging material layer and vertically penetrates through the plastic packaging material layer;
the first rewiring layer is positioned on the first surface of the plastic packaging material layer and is electrically connected with the first semiconductor chip and the metal connecting column;
the second rewiring layer is positioned on the second surface of the first plastic packaging material and is electrically connected with the metal connecting column, so that the first rewiring layer is electrically connected with the second rewiring layer through the metal connecting column, and the first semiconductor chip is bonded with the second rewiring layer;
a second semiconductor chip located on a surface of the second rewiring layer away from the first semiconductor chip and electrically connected to the second rewiring layer;
the solder ball bump is positioned on the surface of the first re-wiring layer far away from the first semiconductor chip and is electrically connected with the first re-wiring layer;
and the underfill layer is positioned between the second semiconductor chip and the second re-wiring layer and in the lower area of the peripheral side of the second semiconductor chip.
Optionally, the first semiconductor chip is a bare chip or a packaged chip, and the second semiconductor chip is a bare chip or a packaged chip.
Optionally, the bare chip includes a contact pad, a dielectric layer is formed on the bare chip, a metal pillar penetrating through the dielectric layer is formed in the dielectric layer, one end of the metal pillar is connected to the contact pad, and the other end of the metal pillar is connected to the first redistribution layer or the second redistribution layer; the packaged chip comprises a contact bonding pad, a solder connecting structure is formed on the packaged chip and comprises a metal column and a solder ball, one end of the metal column is connected with the contact bonding pad, the other end of the metal column is connected with the solder ball, and the solder ball is connected with the first re-wiring layer or the second re-wiring layer.
Optionally, the first redistribution layer and the second redistribution layer include: the wiring medium layer and the metal wiring layer are positioned in the wiring medium layer; the wiring dielectric layer is made of one or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass; the material of the metal wiring layer includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium.
Optionally, the plastic packaging material layer includes one or a combination of a polyimide layer, a silica gel layer and an epoxy resin layer; the underfill layer includes an epoxy layer.
Optionally, the material of the solder ball bump is one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.
The invention also provides a preparation method of the double-layer stacked 3D fan-out type packaging structure, which comprises the following steps:
providing a first supporting substrate, and forming a separation layer on the first supporting substrate;
forming a second re-wiring layer on the separation layer;
forming a metal connecting column on the second re-wiring layer, wherein the metal connecting column is electrically connected with the second re-wiring layer;
providing a first semiconductor chip and bonding it to the second re-wiring layer;
forming a plastic packaging material layer on the surface of the second rewiring layer, wherein the plastic packaging material layer fills a gap between the first semiconductor chip and the metal connecting column and plastically packages the first semiconductor chip and the metal connecting column; the plastic packaging material layer comprises a first surface and a second surface which are opposite, the second surface of the plastic packaging material layer is in contact with the second rewiring layer, and the first surface of the plastic packaging material layer is exposed out of the metal connecting column;
forming a first rewiring layer on the first surface of the plastic packaging material layer, wherein the first rewiring layer is electrically connected with the first semiconductor chip and the metal connecting column;
forming solder ball bumps on the surface of the first re-wiring layer away from the first semiconductor chip, and electrically connecting the solder ball bumps with the first re-wiring layer;
providing a second support substrate and adhering the second support substrate to the first rewiring layer;
removing the first support substrate and the separation layer to expose the second re-wiring layer;
providing a second semiconductor chip and electrically connecting the second semiconductor chip to the second rewiring layer;
forming an underfill layer between the second semiconductor chip and the second redistribution layer and in a lower region of the periphery of the second semiconductor chip;
removing the second support substrate.
Optionally, the first support substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate, the second support substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate, and the separation layer includes a polymer layer or an adhesive layer, and the polymer layer or the adhesive layer is firstly coated on the surface of the support substrate by a spin coating process and then cured and formed by an ultraviolet curing or thermal curing process.
Optionally, the first redistribution layer and the second redistribution layer include: the wiring medium layer and the metal wiring layer are positioned in the wiring medium layer; the wiring dielectric layer is made of one or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass; the material of the metal wiring layer includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium.
Optionally, the step of forming the first redistribution layer and the second redistribution layer includes:
forming a dielectric layer by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer to form the wiring dielectric layer;
and forming a metal layer on the surface of the wiring medium layer by adopting a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process or a chemical plating process, etching the metal layer to form the metal wiring layer, and electrically connecting the metal connecting column with the metal wiring layer.
Optionally, the first semiconductor chip is a bare chip or a packaged chip, and the second semiconductor chip is a bare chip or a packaged chip.
Optionally, the bare chip includes a contact pad, a dielectric layer is formed on the bare chip, a metal pillar penetrating through the dielectric layer is formed in the dielectric layer, one end of the metal pillar is connected to the contact pad, and the other end of the metal pillar is connected to the first redistribution layer or the second redistribution layer; the packaged chip comprises a contact bonding pad, a solder connecting structure is formed on the packaged chip and comprises a metal column and a solder ball, one end of the metal column is connected with the contact bonding pad, the other end of the metal column is connected with the solder ball, and the solder ball is connected with the first re-wiring layer or the second re-wiring layer.
As described above, according to the double-layer stacked 3D fan-out package structure and the manufacturing method thereof of the present invention, the formed double-layer stacked 3D fan-out package structure can package two layers of fan-out wafers in a three-dimensional direction (i.e., thickness direction), a single package body formed after cutting has two layers of semiconductor chips along the three-dimensional direction, and control of electrical signals of all semiconductor chips in the single package body is achieved by arranging the first rewiring layer, the metal connection column, and the second rewiring layer, so that more chips are packaged in the single package body, integration of fan-out wafer level packaging is improved, and the package volume is reduced at the same time; moreover, a plurality of chips are packaged in the same packaging body, so that the efficiency of a single chip can be effectively improved; finally, the fabrication method also provides the possibility of packaging more than three layers of fan-out wafers in a single package.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a dual-layer stacked 3D fan-out package structure according to an embodiment of the invention.
Fig. 2 to 16 are schematic structural diagrams of steps in a manufacturing method of a dual-layer stacked 3D fan-out package structure according to a first embodiment of the present invention, wherein fig. 16 is a schematic structural diagram of a dual-layer stacked 3D fan-out package structure according to a second embodiment of the present invention.
Description of the element reference numerals
10 first support base
11. 22 separating layer
12 second rewiring layer
121. 161 wiring dielectric layer
122. 162 metal wiring layer
123 etch window
13 metal connecting column
14 first semiconductor chip
141. 191 contact pad
142 dielectric layer
143. 192 metal column
15 layer of plastic packaging material
16 first rewiring layer
17 solder ball bump
18 second support base
19 second semiconductor chip
193 solder ball
20 underfill layer
21 adhesive layer
S1-S12 steps
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 16. It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation can be changed according to actual needs, and the layout of the components may be more complicated.
Example one
As shown in fig. 1, the embodiment provides a method for manufacturing a dual-layer stacked 3D fan-out package structure, where the dual-layer stacked 3D fan-out package structure formed by the method can package two layers of fan-out wafers in a three-dimensional direction (i.e., a thickness direction), a single package body formed after cutting has two layers of semiconductor chips in the three-dimensional direction, and control over electrical signals of all semiconductor chips in the single package body is realized by arranging a first redistribution layer, a metal connection pillar, and a second redistribution layer, so that more chips are packaged in the single package body, the integrity of fan-out wafer level packaging is improved, and the packaging volume is reduced; moreover, a plurality of chips are packaged in the same package body, so that the efficiency of a single chip can be effectively improved; finally, the fabrication method also provides the possibility of packaging more than three layers of fan-out wafers in a single package.
Specifically, fig. 2 to fig. 16 illustrate schematic structural diagrams presented in each step of the method for manufacturing a dual-layer stacked 3D fan-out package structure in this embodiment. For convenience of understanding, only one chip is shown in each layer of wafer in the presentation process of each step, but those skilled in the art can understand that the number of chips in each layer of fan-out wafer is not more than one, and is generally several, that is, more than two.
As shown in fig. 1 to fig. 3, step S1 is first performed to provide a first support substrate 10 (as shown in fig. 2), and form a separation layer 11 (as shown in fig. 3) on the first support substrate 10.
As shown in fig. 2, the first support substrate 10 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, as an example. In this embodiment, the first support substrate 10 is a glass substrate, which has a low cost, is easy to form the separation layer 11 on the surface thereof, and can reduce the difficulty of the subsequent stripping process. The shape of the first support substrate 10 may be a wafer shape, a square shape or any other desired shape, and the present embodiment prevents the semiconductor chip from cracking, warping, breaking and the like in the subsequent manufacturing process by the first support substrate 10.
As shown in fig. 3, the separation layer 11 is preferably made of an adhesive material with a smooth surface, which is used as a separation layer between the second redistribution layer 12 formed subsequently and other structures on the second redistribution layer 12 and the first support substrate 10 in the subsequent processes, and must have a certain bonding force with the second redistribution layer 12 to ensure that the second redistribution layer 12 does not move or the like in the subsequent processes, and the bonding force with the first support substrate 10 should also be stronger, and generally, the bonding force with the first support substrate 10 needs to be greater than the bonding force with the second redistribution layer 12. As an example, the separation layer 11 includes a polymer layer or an adhesive glue layer, which is first coated on the surface of the first support substrate 10 by a spin coating process and then cured by a uv curing or thermal curing process.
In the present embodiment, the polymer layer includes a LTHC light-to-heat conversion layer, and then the LTHC light-to-heat conversion layer may be heated based on laser light when the first support substrate 10 is peeled off, so that the second rewiring layer 12 and the first support substrate 10 are separated from each other.
As shown in fig. 1 and 4, step S2 is performed to form a second redistribution layer 12 on the separation layer 11.
As shown in fig. 4, the second re-wiring layer 12 includes a wiring medium layer 121 and a metal wiring layer 122 located in the wiring medium layer 121 as an example; the wiring dielectric layer 121 is made of one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the material of the metal wiring layer 122 includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium.
As an example, forming the second re-wiring layer 12 includes the steps of: firstly, forming a dielectric layer on the surface of the separation layer 11 by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer to form the wiring dielectric layer 121; then, a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process or a chemical plating process is used to form a metal layer on the surface of the wiring medium layer 121, and the metal layer is etched to form a metal wiring layer 122. It should be noted that the materials, the number of layers, and the distribution topography of the wiring dielectric layer 121 and the metal wiring layer 122 may be set according to the specific situation of the semiconductor chip, and are not limited herein.
As shown in fig. 1 and 5, step S3 is performed to form a metal via 13 on the second redistribution layer 12, wherein the metal via 13 is electrically connected to the second redistribution layer 12.
As shown in fig. 5, as an example, when the second re-wiring layer 12 includes a wiring dielectric layer 121 and a metal wiring layer 122 located in the wiring dielectric layer 121, the metal connection stud 13 is electrically connected to the second re-wiring layer 12 by contacting the metal wiring layer 122.
By way of example, the metal connecting column 13 includes one or a combination of gold wire, silver wire, copper wire and aluminum wire; the metal connecting column 13 can also comprise one or a combination of a gold column, a silver column, a copper column and an aluminum column; the method for forming the metal connection post 13 comprises one or a combination of wire bonding, electroplating and chemical plating.
Specifically, the metal connecting column 13 may be made of a copper wire by using a wire bonding process, such as one or a combination of a thermocompression bonding process, an ultrasonic bonding process and a thermocompression ultrasonic bonding process, and the type and the making method of the metal connecting column 13 may also be selected according to the requirement, which is not limited herein.
As shown in fig. 1 and 6, step S4 is performed to provide the first semiconductor chip 14 and to adhere it to the second redistribution layer 12.
As an example, the form of the first semiconductor chip 14 is not limited, that is, the first semiconductor chip 14 may be a bare chip without package or a packaged chip, and in the fan-out wafer, the form of the first semiconductor chip 14 may be the same or different, and is specifically set according to actual needs. As shown in fig. 6, the first semiconductor chip 14 is a bare chip, the bare chip includes a contact pad 141, a dielectric layer 142 is formed on the bare chip, a metal pillar 143 penetrating through the dielectric layer 142 is formed in the dielectric layer 142, one end of the metal pillar 143 is connected to the contact pad 141, and the other end is connected to a first redistribution layer 16 formed subsequently.
As shown in fig. 6, as an example, the first semiconductor chip 14 can be adhered to the second redistribution layer 12 by an adhesive layer 21, so as to ensure that the first semiconductor chip 14 does not move in the subsequent processes and in the using process. The material of the adhesive layer 21 may be selected from a tape having both sides thereof sticky or an adhesive prepared by a spin coating process, but is not limited thereto as long as the adhesive layer 21 has desired adhesive properties.
As shown in fig. 1, fig. 7 and fig. 8, next, step S5 is performed to form a plastic package material layer 15 on the surface of the second redistribution layer 12, where the plastic package material layer 15 fills the gap between the first semiconductor chip 14 and the metal connection pillar 13, and the first semiconductor chip 14 and the metal connection pillar 13 are plastic-packaged; the plastic packaging material layer 15 comprises a first surface and a second surface which are opposite to each other, the second surface of the plastic packaging material layer 15 is in contact with the second rewiring layer 12, and the first surface of the plastic packaging material layer 15 is exposed out of the metal connecting column 13.
As an example, the molding compound layer 15 includes one or a combination of a polyimide layer, a silicone layer, and an epoxy resin layer; the method for forming the plastic packaging material layer 15 includes one of compression molding, transfer molding, liquid sealing, vacuum lamination and spin coating.
Specifically, a layer of molding compound layer 15 is formed on the surface of the second redistribution layer 12 (as shown in fig. 7), and then the upper surface of the molding compound layer 15 is subjected to a grinding or polishing method to provide a flat molding compound layer 15 (as shown in fig. 8), so as to improve the product quality.
In another example, the plastic package material layer 15 may be formed according to the height of the metal connection post 13, so that the height of the plastic package material layer 15 is just the same as the height of the metal connection post 13, that is, the first surface of the plastic package material layer 15 is flush with the surface of the metal connection post 13. This eliminates the need for grinding the layer of molding compound 15, thereby simplifying the processing steps.
As shown in fig. 1 and 9, step S6 is performed to form a first redistribution layer 16 on the first surface of the molding compound layer 15, and the first redistribution layer 16 is electrically connected to the first semiconductor chip 14 and the metal connection stud 13. After this step, the electrical signal of the first semiconductor chip 14 is controlled by the first redistribution layer 16, and the electrical signal of the second semiconductor chip 19 to be formed subsequently is controlled by the first redistribution layer 16 through the second redistribution layer 12 and the metal connection stud 13, that is, the first semiconductor chip 14 and the second semiconductor chip 19 to be formed subsequently are controlled by the first redistribution layer 16.
As shown in fig. 9, as an example, the first re-wiring layer 16 includes a wiring dielectric layer 161 and a metal wiring layer 162 located in the wiring dielectric layer 161; the wiring dielectric layer 161 is made of one or a combination of more than two of the group consisting of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass; the material of the metal wiring layer 162 includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium.
As an example, forming the first re-wiring layer 16 includes the steps of: firstly, forming a dielectric layer on the surface of the plastic packaging material layer 15 by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer to form the wiring dielectric layer 161; then, a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process or a chemical plating process is used to form a metal layer on the surface of the wiring medium layer 161, and the metal layer is etched to form a metal wiring layer 162. It should be noted that the materials, the number of layers, and the distribution shapes of the wiring dielectric layer 161 and the metal wiring layer 162 may be set according to the specific situation of the semiconductor chip, and are not limited herein.
As shown in fig. 1 and 10, step S7 is performed to form solder ball bumps 17 on the surface of the first redistribution layer 16 away from the first semiconductor chip 14, and electrically connect the first redistribution layer 16 with the solder ball bumps.
As an example, the material of the solder ball bump 17 is one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium, and the solder ball bump 17 may be formed by a ball-mounting reflow process.
As shown in fig. 1 and 11, step S8 is performed to provide a second supporting substrate 18 and adhere it to the first redistribution layer 16.
As shown in fig. 11, the second support substrate 18 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, as an example. In this embodiment, the second supporting substrate 18 is a glass substrate, which has a low cost, is easy to form the separation layer 22 on the surface thereof, and can reduce the difficulty of the subsequent stripping process. The shape of the second support substrate 18 may be a wafer shape, a square shape or any other desired shape, and the second support substrate 18 is used in this embodiment to prevent the semiconductor chip from cracking, warping, breaking and the like in the subsequent manufacturing process.
As shown in fig. 11, as an example, the adhesion of the second support substrate 18 and the first re-wiring layer 16 may be achieved by providing a separation layer 22 therebetween. By way of example, the release layer 22 comprises a polymer layer or an adhesive glue layer.
As shown in fig. 1 and 12, step S9 is performed to remove the first supporting substrate 10 and the separation layer 11 to expose the second redistribution layer 12.
As an example, when the separation layer 11 includes an adhesive glue layer, an exposure method may be employed to make the adhesive glue less sticky to achieve separation thereof from the second re-wiring layer 12; when the separation layer 11 includes the LTHC light-to-heat conversion layer, the LTHC light-to-heat conversion layer is heated based on laser light to separate the second re-wiring layer 12 and the first support substrate 10 from each other.
As shown in fig. 1, 13 and 14, step S10 is performed to provide a second semiconductor chip 19 and electrically connect it to the second redistribution layer 12. After this step, the second semiconductor chip 19 is electrically connected to the second rewiring layer 12, and the second rewiring layer 12 is electrically connected to the first rewiring layer 16 through the metal connection post 13, thereby electrically connecting the first rewiring layer 16 to the second rewiring layer 12.
As an example, the form of the second semiconductor chip 19 is not limited, i.e., the second semiconductor chip 19 may be a bare chip or a packaged chip without packaging. In the fan-out wafer, the second semiconductor chips 19 may be in the same or different forms, and are specifically arranged according to actual needs. As shown in fig. 14, the second semiconductor chip 19 is a packaged chip, the packaged chip includes a contact pad 191, a solder connection structure is formed on the packaged chip, the solder connection structure includes a metal pillar 192 and a solder ball 193, one end of the metal pillar 192 is connected to the contact pad 191, the other end is connected to the solder ball 193, and the solder ball 193 is further connected to the second redistribution layer 12. As shown in fig. 13, first, laser etching, for example, infrared laser is used to etch the wiring dielectric layer 121 in the second redistribution layer 12 to form an etching window 123, and the metal wiring layer 122 is exposed through the etching window 123; as shown in fig. 14, the electrical connection of the second semiconductor chip 19 to the second re-wiring layer 12 is then realized by the solder balls 193.
As shown in fig. 1 and 15, step S11 is performed to form an underfill layer 20 between the second semiconductor chip 19 and the second redistribution layer 12 and in the lower region of the second semiconductor chip 19 around the second semiconductor chip 19. Providing the underfill layer 20 can improve the bonding strength between the second semiconductor chip 19 and the second re-wiring layer 12 and protect the second re-wiring layer 12. Based on this, the material particles of the underfill layer 20 are smaller than those of the plastic package material layer, so that the underfill layer 20 has better bonding strength and can effectively protect the second redistribution layer 12, and only one-step underfill process is needed to implement the process, so that the process is simple, most of the packaging requirements can be met, and the cost is low.
The underfill layer is an epoxy layer, but may be other smaller particle filler materials. Methods of forming the underfill layer 20 include, but are not limited to, one or more of ink-jet, dispensing, compression molding, transfer molding, liquid encapsulation, vacuum lamination, and spin coating.
As shown in fig. 1 and 16, step S12 is finally performed to remove the second support substrate 18.
As an example, when the second support substrate 18 is bonded to the first re-wiring layer 16 through the separation layer 22; in the first case, when the separation layer 22 includes an adhesive layer, the adhesive layer may be made less adhesive by an exposure method to achieve separation from the first rewiring layer 16; when the separation layer 22 includes the LTHC light-to-heat conversion layer, the LTHC light-to-heat conversion layer is heated based on laser light to separate the first redistribution layer 16 and the second support substrate 18 from each other.
Example two
This embodiment provides a two-layer stacked 3D fan-out package structure, which can be manufactured by the manufacturing method of the first embodiment, but is not limited to the manufacturing method described in the first embodiment, as long as the two-layer stacked 3D fan-out package structure can be formed. For the beneficial effects that the dual-layer stacked 3D fan-out package structure can achieve, please refer to embodiment one, which is not described in detail below.
As shown in fig. 16, the dual-layer stacked 3D fan-out package structure includes:
a first semiconductor chip 14;
the plastic packaging material layer 15 comprises a first surface and a second surface which are opposite, and the plastic packaging material layer 15 is in plastic packaging on the periphery of the first semiconductor chip 14;
the metal connecting column 13 is positioned in the plastic packaging material layer 15 and vertically penetrates through the plastic packaging material layer 15;
a first rewiring layer 16 located on the first surface of the plastic package material layer 15 and electrically connected to the first semiconductor chip 14 and the metal connection column 13;
a second redistribution layer 12 located on the second surface of the first plastic package material 15 and electrically connected to the metal connection post 13, so that the first redistribution layer 16 is electrically connected to the second redistribution layer 12 through the metal connection post 13, and the first semiconductor chip 14 is bonded to the second redistribution layer 12;
a second semiconductor chip 19 located on a surface of the second rewiring layer 12 away from the first semiconductor chip 14 and electrically connected to the second rewiring layer 12;
a solder ball bump 17 on a surface of the first re-wiring layer 16 away from the first semiconductor chip 14 and electrically connected to the first re-wiring layer 16;
and an underfill layer 20 located between the second semiconductor chip 19 and the second redistribution layer 12 and in a lower region on the periphery of the second semiconductor chip.
As an example, the first semiconductor chip 14 is a bare chip or a packaged chip, and the second semiconductor chip 19 is a bare chip or a packaged chip. As shown in fig. 16, the first semiconductor chip 14 is a bare chip, and the second semiconductor chip 19 is a packaged chip. Further, the bare chip includes a contact pad 141, a dielectric layer 142 is formed on the bare chip, a metal pillar 143 penetrating through the dielectric layer 142 is formed in the dielectric layer 142, one end of the metal pillar 143 is connected to the contact pad 141, and the other end is connected to the first redistribution layer 16; the packaged chip comprises a contact pad 191, a solder connection structure is formed on the packaged chip, the solder connection structure comprises a metal column 192 and a solder ball 193, one end of the metal column 192 is connected with the contact pad 191, the other end of the metal column is connected with the solder ball 193, and the solder ball 193 is connected with the second redistribution layer 12.
As an example, the first re-wiring layer 16 and the second re-wiring layer 12 include: a wiring dielectric layer 121, 161 and a metal wiring layer 122, 162 positioned in the wiring dielectric layer 121, 161; the wiring dielectric layers 121 and 161 are made of one or a combination of more than two of the group consisting of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass; the material of the metal wiring layers 122, 162 includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium.
As an example, the molding compound layer 15 includes one or a combination of a polyimide layer, a silicone layer, and an epoxy resin layer; the underfill layer 20 includes an epoxy layer.
As an example, the material of the solder ball bump 17 is one of copper, aluminum, nickel, gold, silver, titanium, or a combination of two or more materials.
In summary, the invention provides a double-layer stacked 3D fan-out package structure and a manufacturing method thereof, the formed double-layer stacked 3D fan-out package structure can package two layers of fan-out wafers in a three-dimensional direction (i.e. thickness direction), a single package body formed after cutting has two layers of semiconductor chips along the three-dimensional direction, and control over electrical signals of all the semiconductor chips in the single package body is realized by arranging a first rewiring layer, a metal connecting column and a second rewiring layer, so that more chips are packaged in the single package body, integration of fan-out wafer level packaging is improved, and packaging volume is reduced; moreover, a plurality of chips are packaged in the same packaging body, so that the efficiency of a single chip can be effectively improved; finally, the fabrication method also provides the possibility of packaging more than three layers of fan-out wafers in a single package. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (12)

1. A dual-layer stacked 3D fan-out package structure, comprising:
a first semiconductor chip;
the plastic packaging material layer comprises a first surface and a second surface which are opposite, and is in plastic packaging on the periphery of the first semiconductor chip;
the metal connecting column is positioned in the plastic packaging material layer and vertically penetrates through the plastic packaging material layer;
the first rewiring layer is positioned on the first surface of the plastic packaging material layer and is electrically connected with the first semiconductor chip and the metal connecting column;
the second rewiring layer is positioned on the second surface of the first plastic packaging material and is electrically connected with the metal connecting column, so that the first rewiring layer is electrically connected with the second rewiring layer through the metal connecting column, and the first semiconductor chip is bonded with the second rewiring layer;
a second semiconductor chip located on a surface of the second rewiring layer away from the first semiconductor chip and electrically connected to the second rewiring layer;
the solder ball bump is positioned on the surface of the first re-wiring layer far away from the first semiconductor chip and is electrically connected with the first re-wiring layer;
and the underfill layer is positioned between the second semiconductor chip and the second rewiring layer and in the lower area of the periphery of the second semiconductor chip.
2. The dual-layer stacked 3D fan-out package structure of claim 1, wherein: the first semiconductor chip is a bare chip or a packaged chip, and the second semiconductor chip is a bare chip or a packaged chip.
3. The dual-layer stacked 3D fan-out package structure of claim 2, wherein: the bare chip comprises a contact pad, a dielectric layer is formed on the bare chip, a metal column penetrating through the dielectric layer is formed in the dielectric layer, one end of the metal column is connected with the contact pad, and the other end of the metal column is connected with the first rewiring layer or the second rewiring layer; the packaged chip comprises a contact bonding pad, a solder connecting structure is formed on the packaged chip and comprises a metal column and a solder ball, one end of the metal column is connected with the contact bonding pad, the other end of the metal column is connected with the solder ball, and the solder ball is connected with the first re-wiring layer or the second re-wiring layer.
4. The dual-layer stacked 3D fan-out package structure of claim 1, wherein the first and second re-routing layers comprise: the wiring medium layer and the metal wiring layer are positioned in the wiring medium layer; the wiring medium layer is made of one or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the material of the metal wiring layer includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium.
5. The dual-layer stacked 3D fan-out package structure of claim 1, wherein: the plastic packaging material layer comprises one or a combination of a polyimide layer, a silica gel layer and an epoxy resin layer; the underfill layer includes an epoxy layer.
6. The dual layer stacked 3D fan-out package structure of claim 1, in which: the solder ball bump is made of one or a combination of more than two of copper, aluminum, nickel, gold, silver and titanium.
7. A preparation method of a double-layer stacked 3D fan-out type packaging structure is characterized by comprising the following steps:
providing a first supporting substrate, and forming a separation layer on the first supporting substrate;
forming a second re-wiring layer on the separation layer;
forming a metal connecting column on the second re-wiring layer, wherein the metal connecting column is electrically connected with the second re-wiring layer;
providing a first semiconductor chip and bonding it to the second re-wiring layer;
forming a plastic packaging material layer on the surface of the second rewiring layer, wherein the plastic packaging material layer fills a gap between the first semiconductor chip and the metal connecting column and plastically packages the first semiconductor chip and the metal connecting column; the plastic packaging material layer comprises a first surface and a second surface which are opposite, the second surface of the plastic packaging material layer is in contact with the second rewiring layer, and the first surface of the plastic packaging material layer is exposed out of the metal connecting column;
forming a first rewiring layer on the first surface of the plastic packaging material layer, wherein the first rewiring layer is electrically connected with the first semiconductor chip and the metal connecting column;
forming solder ball bumps on the surface of the first re-wiring layer away from the first semiconductor chip, and electrically connecting the solder ball bumps with the first re-wiring layer;
providing a second support substrate and adhering the second support substrate to the first rewiring layer;
removing the first support substrate and the separation layer to expose the second re-wiring layer;
providing a second semiconductor chip and electrically connecting the second semiconductor chip to the second rewiring layer;
forming an underfill layer between the second semiconductor chip and the second redistribution layer and in a lower region of the periphery of the second semiconductor chip;
removing the second support substrate.
8. The method of fabricating a two-layer stacked 3D fan-out package structure of claim 7, wherein: the first supporting substrate comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate, the second supporting substrate comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate, the separation layer comprises a polymer layer or an adhesive layer, the polymer layer or the adhesive layer is firstly coated on the surface of the supporting substrate by adopting a spin coating process, and then is cured and molded by adopting an ultraviolet curing or thermosetting process.
9. The method of fabricating a two-layer stacked 3D fan-out package structure of claim 7, wherein: the first and second re-routing layers include: the wiring medium layer and the metal wiring layer are positioned in the wiring medium layer; the wiring medium layer is made of one or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the material of the metal wiring layer includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium.
10. The method of fabricating a two-layer stacked 3D fan-out package structure of claim 9, wherein the step of forming the first and second re-routing layers comprises:
forming a dielectric layer by adopting a chemical vapor deposition process or a physical vapor deposition process, and etching the dielectric layer to form the wiring dielectric layer;
and forming a metal layer on the surface of the wiring medium layer by adopting a chemical vapor deposition process, a physical vapor deposition process, a sputtering process, an electroplating process or a chemical plating process, etching the metal layer to form the metal wiring layer, and electrically connecting the metal connecting column with the metal wiring layer.
11. The method of fabricating a two-layer stacked 3D fan-out package structure of claim 7, wherein: the first semiconductor chip is a bare chip or a packaged chip, and the second semiconductor chip is a bare chip or a packaged chip.
12. The method of fabricating a two-layer stacked 3D fan-out package structure of claim 11, wherein: the bare chip comprises a contact pad, a dielectric layer is formed on the bare chip, a metal column penetrating through the dielectric layer is formed in the dielectric layer, one end of the metal column is connected with the contact pad, and the other end of the metal column is connected with the first rewiring layer or the second rewiring layer; the packaged chip comprises a contact bonding pad, a solder connecting structure is formed on the packaged chip and comprises a metal column and a solder ball, one end of the metal column is connected with the contact bonding pad, the other end of the metal column is connected with the solder ball, and the solder ball is connected with the first re-wiring layer or the second re-wiring layer.
CN202110194401.5A 2021-02-20 2021-02-20 Double-layer stacked 3D fan-out type packaging structure and packaging method thereof Pending CN114975410A (en)

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