CN114975365A - Test structure and test method - Google Patents

Test structure and test method Download PDF

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Publication number
CN114975365A
CN114975365A CN202210470164.5A CN202210470164A CN114975365A CN 114975365 A CN114975365 A CN 114975365A CN 202210470164 A CN202210470164 A CN 202210470164A CN 114975365 A CN114975365 A CN 114975365A
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China
Prior art keywords
metal layer
flash memory
memory device
test structure
region
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CN202210470164.5A
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Chinese (zh)
Inventor
杜怡行
王壮壮
王虎
顾林
姚春
杨耀华
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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Priority to CN202210470164.5A priority Critical patent/CN114975365A/en
Publication of CN114975365A publication Critical patent/CN114975365A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Non-Volatile Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Memories (AREA)

Abstract

The application discloses test structure and test method, this test structure includes: the STI structure comprises a first doped region, a second doped region and a third doped region which are formed in a substrate, wherein an STI structure is formed in the third doped region; the floating gate is formed above the substrate and is transversely positioned between the STI structures, and a gate dielectric layer is formed between the floating gate and the substrate; a control gate formed on the floating gate; the floating gates and the control gates are in a strip shape and are positioned in the third doped region; a first metal layer and a second metal layer are also formed in the third doped region, the first metal layer and the second metal layer are positioned at two sides of the region occupied by the floating gates and the control gates, and two ends of the control gates are respectively connected with the first metal layer and the second metal layer; a third metal layer and a fourth metal layer are further formed on the substrate, the third metal layer is connected with the second metal layer, and the fourth metal layer is connected with the second doped region and is not in contact with the third doped region.

Description

Test structure and test method
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a test structure and a test method.
Background
As semiconductor integrated circuit fabrication technology continues to advance, the Critical Dimension (CD) of semiconductor devices is also shrinking.
In the manufacturing process of the flash memory device, in the process of forming a Floating Gate (FG), the width of the floating gate is reduced due to the reduction of the device size, so that there is a certain probability of defects such as voids and gaps occurring in the formed floating gate.
In view of this, it is desirable to provide a testing method for monitoring the floating gate defect condition of the flash memory device.
Disclosure of Invention
The application provides a test structure and a test method, which can solve the problems of the defects of holes and gaps caused by a floating gate forming method provided in the related technology.
In one aspect, an embodiment of the present application provides a test structure, where the test structure is used to detect a floating gate defect of a flash memory device, and the test structure is formed on a substrate, and the test structure includes:
the doped region is formed in the substrate and sequentially comprises a first doped region, a second doped region and a third doped region from bottom to top, the substrate is doped with impurities of a first type, the first doped region is doped with impurities of a second type, the second doped region is doped with impurities of the first type, the third doped region is doped with impurities of the second type, and an STI structure is formed in the third doped region;
the floating gate is formed above the substrate and between the STI structure, and a gate dielectric layer is formed between the floating gate and the substrate;
a control gate formed on the floating gate;
viewed from a top view, the floating gates and the control gates are located in the third doped region, the floating gates and the control gates are strip-shaped, the floating gates and the control gates are perpendicular to each other, the distances between the floating gates are the same, and the distances between the control gates are the same;
a first metal layer and a second metal layer are further formed in the third doped region, the first metal layer and the second metal layer are located on two sides of a region occupied by the floating gates and the control gates, and two ends of the control gates are connected with the first metal layer and the second metal layer respectively;
the area of the second doping region is larger than that of the third doping region, a third metal layer and a fourth metal layer are further formed on the substrate, the third metal layer is connected with the second metal layer, and the fourth metal layer is connected with the second doping region and is not in contact with the third doping region.
In some embodiments, the first doped region is a drift region of the flash memory device, the second doped region is a well region of the flash memory device, and the third doped region is a threshold voltage adjustment region of the flash memory device.
In some embodiments, the substrate further includes a cell region for integrating the flash memory device, the floating gates of the flash memory device and the floating gate of the test structure have the same critical dimension, and the distance between the floating gates of the flash memory device and the distance between the floating gates in the test structure are the same.
In some embodiments, when a floating gate defect of the flash memory device is detected through the test structure, a high level is input through the third metal layer and a low level is input through the fourth metal layer.
In some embodiments, the flash memory device is a NOR flash memory device.
In another aspect, an embodiment of the present application provides a test method, where the method is performed by a test structure as described in any of the above, and the test method includes:
inputting a high level through a third metal layer of the test structure, and inputting a low level through a fourth metal layer of the test structure;
measuring a current of a second doped region of the test structure;
and determining whether the flash memory device has floating gate defects according to the current of the second doped region.
In some embodiments, the determining whether the flash memory device has the floating gate defect according to the current of the second doped region includes:
detecting whether the current of the second doping area is higher than a target current;
and if the current of the second doping area is higher than the target current, determining that the flash memory device has floating gate defects.
The technical scheme at least comprises the following advantages:
the method comprises the steps of forming a test structure on a substrate integrated with a flash memory device, inputting a high level into a third metal layer of the test structure, inputting a low level into a fourth metal layer of the test structure, measuring the current of a second doped region of the test structure, and determining whether the flash memory device has floating gate defects according to the current of the second doped region, so that the floating gate defects of the flash memory device can be monitored, and the reliability and yield of products are improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic cross-sectional view of a test structure provided in an exemplary embodiment of the present application;
FIG. 2 is a schematic top view of a test structure provided by an exemplary embodiment of the present application;
FIG. 3 is a flow chart of a testing method provided by an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, a fixed connection, a detachable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to FIG. 1, a schematic cross-sectional view of a test structure provided by an exemplary embodiment of the present application is shown; referring to fig. 2, which shows a schematic top view of a test structure provided in an exemplary embodiment of the present application, fig. 1 is a cross-sectional view along AA' in fig. 2.
The test structure is used for detecting floating gate defects of a flash memory device, and is formed on a substrate on which the flash memory device (not shown in fig. 1 and 2, which may be a NOR flash memory device) is integrated, as shown in fig. 1, and includes:
the doped region is formed in the substrate 110 and includes a first doped region 101, a second doped region 102 and a third doped region 103 from bottom to top, and the STI structure 140 is formed in the third doped region 103.
The substrate 110 is doped with a first type of impurity, the first doping region 101 is doped with a second type of impurity, the second doping region 102 is doped with the first type of impurity, and the third doping region 103 is doped with the second type of impurity.
In some embodiments, the first doped region 101 is a drift (drift) region, the second doped region 102 is a well (well) region, and the third doped region 103 is a threshold voltage regulation (CVT) region of the flash memory device.
In the embodiment of the application, if the first type of impurity is an n (negative) type impurity, the second type of impurity is a p (positive) type impurity; if the first type impurity is a P-type impurity, the second type impurity is an N-type impurity.
And a floating gate 131 formed over the substrate 110 and laterally between the STI structures 140, with a gate dielectric layer 120 formed between the floating gate 131 and the substrate 110.
And a control gate 132 formed on the floating gate 131.
From a top view, as shown in fig. 2, the plurality of floating gates 131 and the plurality of control gates 132 are located in the third doped region 103, and the floating gates 131 and the control gates 132 are stripe-shaped.
A first metal layer 151 and a second metal layer 152 are further formed in the third doped region 103, the first metal layer 151 and the second metal layer 152 are located at two sides of the region occupied by the plurality of floating gates 131 and the plurality of control gates 132, and two ends of the plurality of control gates 132 are respectively connected with the first metal layer 151 and the second metal layer 152.
A third metal layer 153 and a fourth metal layer 154 are further formed on the substrate 110, the third metal layer 153 is connected to the second metal layer 152, and the fourth metal layer 154 is connected to the second doped region 102 and is not in contact with the third doped region 103.
When the floating gate defect of the flash memory device is detected through the test structure, a high level is input through the third metal layer 153 and a low level is input through the fourth metal layer 154.
In the embodiment of the present application, a cell (cell) region (not shown in fig. 1 and 2) is further included on the substrate, the cell region is used for integrating the flash memory device, the critical dimensions of the floating gate of the flash memory device and the floating gate of the test structure are the same, and the distance between the floating gates of the flash memory device and the distance between the floating gates in the test structure are the same. In some embodiments, the control gates of the flash memory devices and the control gates of the test structure have the same critical dimensions, and the distance between the control gates of the flash memory devices is the same as the distance between the floating gates in the test structure.
Referring to fig. 3, which shows a flowchart of a testing method provided by an exemplary embodiment of the present application, the method is performed by the above-mentioned testing structure, and as shown in fig. 3, the testing method includes:
in step S1, a high level is input through the third metal layer of the test structure, and a low level is input through the fourth metal layer of the test structure.
In step S2, the current of the second doped region of the test structure is measured.
For example, the test structure may be connected to probes on a probe card, and a high level may be input to the third metal layer through the probes, a low level may be input to the fourth metal layer through the probes, and a current may be measured in the second doped region through the probes.
In step S3, it is determined whether the flash memory device has a floating gate defect according to the current of the second doped region.
Illustratively, step S3 includes, but is not limited to: detecting whether the current of the second doped region is higher than a target current (the target current can be determined by experience and/or simulation); and if the current of the second doping area is higher than the target current, determining that the flash memory device integrated on the substrate has floating gate defects (or, if the current of the second doping area is not higher than the target current, determining that the flash memory device integrated on the substrate does not have floating gate defects).
In summary, in the embodiment of the present application, a test structure is formed on a substrate integrated with a flash memory device, a high level is input to a third metal layer of the test structure, a low level is input to a fourth metal layer of the test structure, and after a current of a second doped region of the test structure is measured, whether the flash memory device has a floating gate defect is determined according to the current of the second doped region, so that the floating gate defect of the flash memory device can be monitored, and the reliability and yield of products are improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (7)

1. A test structure for detecting floating gate defects of a flash memory device, the test structure formed on a substrate, the test structure comprising:
the substrate comprises a substrate body, a doping region and a plurality of trenches, wherein the substrate body comprises a substrate body and a plurality of trenches arranged in the substrate body, the doping region is formed in the substrate body and sequentially comprises a first doping region, a second doping region and a third doping region from bottom to top, impurities of a first type are doped in the substrate body, impurities of a second type are doped in the first doping region, impurities of the first type are doped in the second doping region, impurities of the second type are doped in the third doping region, and an STI structure is formed in the third doping region;
the floating gate is formed between the upper part of the substrate and the STI structure, and a gate dielectric layer is formed between the floating gate and the substrate;
a control gate formed on the floating gate;
viewed from a top view, the floating gates and the control gates are located in the third doped region, the floating gates and the control gates are strip-shaped, the floating gates and the control gates are perpendicular to each other, the intervals between the floating gates are the same, and the intervals between the control gates are the same;
a first metal layer and a second metal layer are further formed in the third doped region, the first metal layer and the second metal layer are located on two sides of the region occupied by the floating gates and the control gates, and two ends of the control gates are respectively connected with the first metal layer and the second metal layer;
the area of the second doping region is larger than that of the third doping region, a third metal layer and a fourth metal layer are further formed on the substrate, the third metal layer is connected with the second metal layer, and the fourth metal layer is connected with the second doping region and is not in contact with the third doping region.
2. The test structure of claim 1, wherein the first doped region is a drift region of the flash memory device, the second doped region is a well region of the flash memory device, and the third doped region is a threshold voltage adjustment region of the flash memory device.
3. The test structure of claim 2, further comprising a cell area on the substrate, the cell area being used for integrating the flash memory device, the floating gates of the flash memory device and the floating gate of the test structure having the same critical dimensions, and the distance between the floating gates of the flash memory device being the same as the distance between the floating gates in the test structure.
4. The test structure of claim 3, wherein when a floating gate defect of a flash memory device is detected by the test structure, a high level is input through the third metal layer and a low level is input through the fourth metal layer.
5. The test structure of any of claims 1 to 4, wherein the flash memory device is a NOR flash memory device.
6. A test method, characterized in that the method is performed by a test structure according to any of claims 1 to 5, the test method comprising:
inputting a high level through a third metal layer of the test structure, and inputting a low level through a fourth metal layer of the test structure;
measuring a current of a second doped region of the test structure;
and determining whether the flash memory device has floating gate defects according to the current of the second doped region.
7. The method of claim 6, wherein determining whether a flash memory device has a floating gate defect based on the current in the second doped region comprises:
detecting whether the current of the second doping area is higher than a target current;
and if the current of the second doping area is higher than the target current, determining that the flash memory device has floating gate defects.
CN202210470164.5A 2022-04-28 2022-04-28 Test structure and test method Pending CN114975365A (en)

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CN202210470164.5A CN114975365A (en) 2022-04-28 2022-04-28 Test structure and test method

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CN202210470164.5A CN114975365A (en) 2022-04-28 2022-04-28 Test structure and test method

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CN114975365A true CN114975365A (en) 2022-08-30

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