CN114975297A - Semiconductor package device and method of manufacturing the same - Google Patents

Abstract

The present disclosure relates to a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes: the chip comprises a chip, wherein an active surface and a side surface of the chip are provided with insulating layers; and the surface of the substrate is attached to the insulating layer on the active surface of the chip, and the substrate is electrically connected with the chip. The semiconductor packaging device increases the contact area between the chip and the substrate, can effectively share the bonding force between the chip and the substrate during hybrid bonding, reduces the extrusion strength between the chip and the substrate, reduces the risk of structural fracture, and is beneficial to improving the product yield.

Description

Semiconductor package device and method of manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor packaging devices, and more particularly, to a semiconductor packaging device and a method of manufacturing the same.

Background

With the continuous improvement of the integration level, the number of device units on each chip is increased sharply, the area of the chip is increased, the increase of the connection lines between the units affects the working speed of the circuit and occupies a large area, the further improvement of the integration level and the working speed of the integrated circuit is seriously affected, and the three-dimensional stacking technology becomes a current mainstream breakthrough scheme. In the three-dimensional stacking technology, bonding is the core process technology of its manufacturing technology, and has undergone an iterative process from micro-bump (micro-bump), copper pillar bump (Cu pillar) to wafer bonding, which has now progressed from dielectric wafer bonding to hybrid bonding.

Hybrid bonding is one application of wafer-level bonding in which wafers are joined together by bond pads and dielectric layers. When the chip (especially a small-sized chip) is subjected to hybrid bonding, the problem of structural fracture is easily caused under the influence of bonding force.

Disclosure of Invention

The present disclosure provides a semiconductor package device and a method of manufacturing the same.

In a first aspect, the present disclosure provides a semiconductor package device comprising:

the chip comprises a chip, wherein an active surface and a side surface of the chip are provided with insulating layers;

the surface of the substrate is attached to the insulating layer on the active surface of the chip, and the substrate is electrically connected with the chip.

In some alternative embodiments, the chip and the substrate are electrically connected in a hybrid bond.

In some alternative embodiments, the peripheral dimension of the insulating layer decreases gradually in a direction from the passive surface of the chip to the active surface of the chip.

In some optional embodiments, an angle between an outer surface of the insulating layer disposed on the side of the chip and the active surface of the chip is greater than 60 degrees and less than 80 degrees.

In some optional embodiments, the chip includes a first chip and a second chip, and the insulating layer disposed on the first chip side and the insulating layer disposed on the second chip side are integrally connected.

In some optional embodiments, a cavity is present between the insulating layer disposed on the first chip side and the insulating layer disposed on the second chip side, and the cavity is filled with a first packaging material.

In some alternative embodiments, the material of the insulating layer is silicon dioxide.

In some alternative embodiments, the insulating layer comprises at least two silicon dioxide layers.

In some optional embodiments, a second encapsulant is disposed around the chip.

In some optional embodiments, the second encapsulant has a through hole, and a conductive pillar is disposed in the through hole, and a first end of the conductive pillar is electrically connected to the substrate.

In some alternative embodiments, the second end of the conductive post is provided with a conductive element.

In some optional embodiments, the diameter of the conductive pillars gradually decreases in a direction from the passive surface of the chip to the active surface of the chip; alternatively, the diameter of the conductive posts may remain constant in a direction from the passive surface of the chip to the active surface of the chip.

In some optional embodiments, a redistribution layer is disposed on a surface of the second encapsulant, and the second end of the conductive pillar is electrically connected to the redistribution layer.

In some optional embodiments, the substrate includes a substrate body and an electrical connection layer on the substrate body, the chip being electrically connected to the electrical connection layer.

In some alternative embodiments, the thickness of the electrical connection layer is less than 10 microns.

In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, comprising:

forming an insulating layer on the active surface and the side surface of the chip;

leveling an insulating layer of an active surface of the chip;

electrically connecting the chip and a substrate, wherein the surface of the substrate is attached to the insulating layer of the active surface of the chip;

in some optional embodiments, the method further comprises:

arranging a second packaging material around the chip;

and arranging an external connecting structure on the surface of the second packaging material, wherein the external connecting structure is electrically connected with the substrate.

In some optional embodiments, the forming of the insulating layer on the active surface and the side surface of the chip includes:

placing the chip on a carrier;

arranging photoresist surrounding the chip around the chip;

depositing silicon dioxide on the active surface and the side face of the chip through physical vapor deposition to form the insulating layer;

and stripping the photoresist.

In some optional embodiments, the electrically connecting the chip and the substrate includes:

and mixing and bonding the chip and the substrate.

In some optional embodiments, the disposing an external connection structure on the surface of the second encapsulant comprises:

forming a through hole in the second packaging material;

forming a conductive pillar in the through hole, wherein a first end of the conductive pillar is electrically connected with the conductive pad on the substrate;

disposing a conductive element at a second end of the conductive post; or, a redistribution layer is arranged on the surface of the second packaging material, and the second end of the conductive pillar is electrically connected with the redistribution layer.

According to the semiconductor packaging device and the manufacturing method thereof provided by the embodiment of the disclosure, the insulating layers are arranged on the active surface and the side surface of the chip, so that the contact area between the chip and the substrate is increased, the bonding force between the chip and the substrate during Hybrid bonding (Hybrid bonding) can be effectively shared, the extrusion strength between the chip and the substrate is reduced, the risk of structural fracture is reduced, and the product yield is favorably improved.

Drawings

Other features, objects and advantages of the present disclosure will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

FIG. 1 is a schematic diagram of a prior art semiconductor package device;

fig. 2-12 are first through eleventh schematic views of a semiconductor package device according to an embodiment of the present invention;

fig. 13-18 are schematic diagrams of a manufacturing process of a semiconductor package device according to an embodiment of the present invention.

Description of the symbols:

11 chip 12 insulating layer

13 substrate 100 substrate

101 substrate body 102 electrical connection layer

103 conductive pad 200 chip

201 first insulating layer 202 second insulating layer

200a first chip 201a first insulating layer on a first chip surface

202a second insulating layer 200b on the first chip surface of the second chip

201b first insulating layer on second chip surface 202b second insulating layer on second chip surface

201c first insulating layer on photoresist surface 202c second insulating layer on photoresist surface

301 first encapsulant 302 second encapsulant

303 conductive post 400 conductive element

400a irregular conductive bump 400b stud conductive bump

21 carrier 22 photoresist

304 seed layer 104 additional layers

303' additional conductive pillars 105 first conductive vias

105' second conductive via 106 first conductive pad

106' second conductive pad 107 third conductive via

108 line layer

Detailed Description

The following description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples, and the technical problems and effects solved by the present invention will be readily apparent to those skilled in the art from the description of the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.

It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined by the claims and the appended claims, and therefore, they are not technically essential, and any structural modification, proportion change, or size adjustment should be within the scope of the present disclosure without affecting the function and achievement of the present disclosure. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship thereof may be regarded as the scope of the present invention without substantial technical changes.

It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.

In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 is a schematic view of a semiconductor package device in the prior art. As shown in fig. 1, in the conventional semiconductor package device, an insulating layer 12 is provided on the lower surface of a chip 11. When the chip 11 and the substrate 13 are hybrid bonded, the lower surface of the insulating layer 12 is in direct contact with the upper surface of the substrate 13. When the size of the chip 11 is small, the lower surface area of the insulating layer 12 is correspondingly small, resulting in a small contact area between the insulating layer 12 and the substrate 13. Therefore, during the hybrid bonding process, the bonding force generated by the bonding head (not shown in fig. 1) generates a large pressure on the insulating layer 12 and the substrate 13, which easily causes structural fracture.

Fig. 2 is a first schematic diagram of a semiconductor package device according to an embodiment of the present invention, which corresponds to a longitudinal cross-section of the semiconductor package device. As shown in fig. 2, the semiconductor package device includes a substrate 100 and a chip 200.

In the present embodiment, the active surface and the side surface of the chip 200 are provided with insulating layers, and the insulating layers include a first insulating layer 201 and a second insulating layer 202. The first insulating layer 201 and the second insulating layer 202 are stacked on the active surface and the side surface of the chip 200. Here, the active surface of the chip 200 refers to a surface of the chip 200 for making external connection, for example, a lower surface of the chip 200 in fig. 2.

In one example, the material of the insulating layer on the surface of the chip 200 (including the insulating layer on the active surface and the insulating layer on the side surface) may be silicon dioxide. The silicon dioxide may be formed by deposition. Since the thickness of the silicon dioxide layer formed at each deposition is limited, an insulating layer including a plurality of silicon dioxide layers may be formed by a plurality of depositions. In the example shown in fig. 2, the first insulating layer 201 and the second insulating layer 202 may correspond to silicon dioxide layers formed by two deposition processes.

In the present embodiment, the surface of the substrate 100 is attached to the insulating layer of the active surface of the chip 200, and the substrate 100 is electrically connected to the chip 200. Compared with the semiconductor package device in fig. 1, the contact area between the substrate 100 and the chip 200 in this embodiment includes an increased portion caused by the insulating layer on the side of the chip 200 in addition to the portion facing the active surface of the chip 200 (i.e., the lower surface of the chip 200), so that the contact area between the substrate 100 and the chip 200 is significantly increased in the semiconductor package device in this embodiment compared with the prior art.

In the present embodiment, the substrate 100 and the chip 200 may be electrically connected by hybrid bonding. In the hybrid bonding method, the conductive element of the chip 200 is bonded to the conductive element of the substrate 100, and the insulating layer of the chip 200 is bonded to the insulating portion of the substrate 100. In the semiconductor package device of the present embodiment, the substrate 100 and the chip 200 have a large contact area therebetween, so that the bonding force generated by the bond head can be effectively shared in the hybrid bonding process, thereby reducing the pressing strength of the substrate 100 and the chip 200.

In one example, the substrate 100 may include a substrate body 101 and an electrical connection layer 102. As shown in fig. 2, the electrical connection layer 102 is located on the substrate main body 101, and the chip 200 is electrically connected to the electrical connection layer 102. In one example, the thickness of the electrical connection layer 102 may be less than 10 microns. Thus, the overall thickness of the semiconductor package device is advantageously reduced.

In one example, the outer perimeter dimension of the insulating layer of the chip 200 surface may gradually decrease in a direction from the passive surface of the chip 200 to the active surface of the chip. Here, the passive surface of the chip 200 refers to a surface of the chip 200 opposite to the active surface, for example, an upper surface of the chip 200 in fig. 2. Here, the outer circumference of the insulating layer on the surface of the chip 200 may be the outer circumference of the insulating layer on the surface of the chip 200. As shown in fig. 2, the width of the insulating layer of the surface of the chip 200 is gradually reduced in a direction from the passive surface of the chip 200 to the active surface of the chip (i.e., in a direction from top to bottom), and accordingly, the outer circumference of the insulating layer of the surface of the chip 200 is gradually reduced. The insulating layer on the surface of the chip 200 in this embodiment may be obtained by deposition, so as to form variations in the peripheral dimensions of the insulating layer at different heights.

In one example, the outer surface of the insulating layer disposed on the side of the chip 200 may be at an angle greater than 60 degrees and less than 80 degrees with respect to the active surface of the chip 200. As shown in fig. 4, the dotted line is an extension of the active surface of the chip 200, and therefore the angle θ in the drawing is an included angle between the outer surface of the insulating layer disposed on the side surface of the chip 200 and the active surface of the chip 200. The angle theta may have a value greater than 60 and less than 80 to form a suitable grade.

In one example, the number of chips may be plural. As shown in fig. 2, the chip 200 includes a first chip 200a and a second chip 200 b. A first insulating layer 201a and a second insulating layer 202a are disposed on a surface of the first chip 200a, and a first insulating layer 201b and a second insulating layer 202b are disposed on a surface of the second chip 200 b. In the hybrid bonding process, the plurality of chips can share the bonding force together, which is beneficial to further reducing the extrusion strength between each chip and the substrate 100.

In one example, a cavity may be formed between the insulating layer disposed on the side of the first chip 200a and the insulating layer disposed on the side of the second chip 200b, and the cavity may be filled with the first encapsulant 301. In the manufacturing process, the cavity may be used as a channel for mold Flow (Molding Flow).

In one example, the insulating layers of the plurality of chip surfaces may be formed at one time. For example, deposition may be performed simultaneously on the surfaces of a plurality of chips, thereby forming an insulating layer on the surfaces of the plurality of chips at one time.

In one example, as shown in fig. 2, a second encapsulant 302 may be disposed around the chip 200. The second encapsulant 302 may protect the chip 200.

In one example, as shown in fig. 2, the second encapsulant 302 may have a via hole, and the conductive pillar 303 may be disposed in the via hole, wherein a sidewall of the via hole has a seed layer 304, and the seed layer 304 may be used to form the conductive pillar 303 by electroplating in the manufacturing process. A first end (i.e., a lower end in fig. 2) of the conductive post 303 may be electrically connected to the substrate 100, and a second end (i.e., an upper end in fig. 2) of the conductive post 303 may be provided with the conductive element 400. The second ends of the conductive pillars 303 may extend to the upper surface of the encapsulant 302, so as to form conductive pads or conductive traces on the upper surface of the encapsulant 302. The conductive elements 400 may be solder balls. By the mode, the external connection of the semiconductor packaging device is favorably realized.

In one example, as shown in fig. 8, a redistribution layer 500 is disposed on a surface of the second encapsulant 302, and the second end (i.e., the upper end in fig. 8) of the conductive pillar 303 is electrically connected to the redistribution layer 500. By the mode, diversified external connection of the semiconductor packaging device is facilitated.

In one example, as shown in fig. 2, the diameter of the conductive posts 303 may gradually decrease in a direction from the passive surface of the chip to the active surface of the chip (i.e., in a direction from top to bottom in fig. 3). In this example, the encapsulant 302 may be provided first, then the via holes are formed in the encapsulant 302 by laser drilling, and finally the conductive posts 303 are formed by electroplating in the via holes. Since the laser-drilled via hole is tapered in diameter in the drilling direction, the diameter of the conductive post 303 is accordingly tapered. In another example, as shown in fig. 5, the diameter of the conductive posts 303 may be constant in a direction from the passive surface of the chip to the active surface of the chip (i.e., in a direction from top to bottom in fig. 5). In this example, a photoresist may be disposed on the surface of the substrate 100, then a through hole is formed in the photoresist by exposure, then a conductive pillar 303 is formed in the through hole by electroplating, and finally the photoresist is removed and the package material 302 is disposed. Since the via holes having a uniform diameter can be formed by photolithography, the conductive posts 303 have a uniform diameter accordingly.

In one example, as shown in fig. 3, the insulating layer of the side of the first chip 200a and the insulating layer of the side of the second chip 200b may be integrally connected. In another example, as shown in fig. 6, the insulating layer of the side of the first chip 200a and the insulating layer of the side of the second chip 200b may be separated from each other.

In one example, the conductive elements disposed at the second end of the conductive pillar 303 may be conductive balls as shown in fig. 2, or irregular conductive bumps 400a or pillar conductive bumps 400b as shown in fig. 7.

In the semiconductor packaging device provided by the embodiment of the disclosure, the insulating layers are arranged on the active surface and the side surface of the chip, so that the contact area between the chip and the substrate is increased, the bonding force between the chip and the substrate during hybrid bonding can be effectively shared, the extrusion strength between the chip and the substrate is reduced, the risk of structural fracture is reduced, and the product yield is favorably improved.

In one example, as shown in fig. 9, the semiconductor package device may include the additional layer 104, the additional conductive pillar 303 'is disposed on the additional layer 104, the conductive element 400 is disposed on the additional layer 104, and two ends of the additional conductive pillar 303' are electrically connected to the conductive pillar 303 and the conductive element 400, respectively. In the example shown in fig. 2, the thickness of the package material 302 is relatively thick, and the reliability of the conductive pillars 303 formed by electroplating is relatively poor, whereas in the example shown in fig. 9, the upper surfaces of the first chip 200a and the second chip 200b may be exposed by a thinning process (e.g., a grinding process) after the package material 302 is formed, then the through holes and the conductive pillars 303 are formed in the package material 302, then the additional layer 104 is disposed on the package material 302, and then the additional conductive pillars 303' are formed on the additional layer 104. By forming more than two conductive posts connected with each other, the height of each conductive post can be reduced, thereby improving the reliability of the conductive posts.

In the example shown in fig. 9, the additional layer 104 is a dielectric material. The additional layer 104 may be an organic material such as PA (Polyamide), PI (Polyimide), Epoxy (Epoxy), PBO (Poly-p-phenylene benzoxazole), etc., which is formed by coating, laminating, printing, etc. The additional layer 104 may also be an inorganic material, such as Si (silicon), glass, ceramic, oxide (silicon oxide, tantalum oxide), etc., formed by Physical Vapor Deposition (PVD), Plasma processes (Plasma fabrics), etc. The additional layer 104 can serve as an electrical isolation function to prevent the first chip 200a and the second chip 200b from being directly electrically connected to the conductive pads or conductive traces on the upper surface of the semiconductor package device, thereby avoiding unnecessary electrical generation.

In one example, as shown in fig. 10, in the semiconductor package device, the encapsulation material 302 may expose the passive surface of the first chip 200a, the passive surface of the second chip 200b, the first insulating layer 201a of the first chip surface, and the first insulating layer 201b of the second chip surface to the outside. Therefore, the thickness of the packaging structure is reduced, and the heat dissipation performance of the packaging structure is improved.

In one example, as shown in fig. 11, two semiconductor packages as described above may be vertically stacked. Wherein the upper semiconductor package has a substrate body 101 on which a first conductive via 105 and a first conductive pad 106 connected thereto are formed, and the lower semiconductor package has a second conductive via 105 'and a second conductive pad 106' connected thereto. The first conductive pad 106 and the second conductive pad 106' may be directly connected, thereby achieving electrical connection of the two semiconductor packages.

In one example, as shown in fig. 12, a third conductive via 107 may be formed on the substrate main body 101, and a line layer 108 may be formed on a surface of the substrate main body 101 facing away from the electrical connection layer 102, wherein two ends of the third conductive via 107 are electrically connected to the electrical connection layer 102 and the line layer 108, respectively.

The present disclosure also provides a method of manufacturing a semiconductor package device. As shown in fig. 13-18, the method includes the steps of:

in the first step, an insulating layer is formed on the active surface and the side surface of the chip.

In one example, the first step may further include the steps of: first, the chip is placed on a carrier. As shown in fig. 14, a first chip 200a and a second chip 200b are placed on a carrier 21. Next, a photoresist is disposed around the chip. As shown in fig. 14, a photoresist 22 may be disposed on the carrier 21 and around the first chip 200a and the second chip 200 b. And finally, depositing silicon dioxide on the active surface and the side surface of the chip through physical vapor deposition to form an insulating layer. As shown in fig. 15, a first insulating layer 201a and a second insulating layer 202a may be formed on the active surface and the side of the first chip 200a, while a first insulating layer 201b and a second insulating layer 202b may be formed on the active surface and the side of the second chip 200b, by multiple physical vapor deposition. Note that the first insulating layer 201c and the second insulating layer 202c are also formed on the surface of the photoresist 22. Finally, the photoresist is stripped. For example, the photoresist may be modified in its properties by immersion in a chemical agent to separate it from the carrier 21. In the method, the photoresist can play a role in stripping, and under the scene that a plurality of semiconductor packaging devices are manufactured on the same carrier, the photoresist can naturally separate the insulating layers of chips in different packaging devices, so that the subsequent cutting of the insulating layers is not needed, and the efficiency and the quality of product manufacturing are improved.

And secondly, flattening the insulating layer on the active surface of the chip.

As shown in fig. 16, the insulating layer on the active surface of the chip may be polished to ensure that the surface is flat and the level is the same, so as to perform subsequent hybrid bonding.

And thirdly, electrically connecting the chip and the substrate, wherein the surface of the substrate is attached to the insulating layer on the active surface of the chip.

The substrate 100 as shown in fig. 13 may be formed by repeating the processes of depositing a seed layer, coating a photoresist, etching, and removing the photoresist. The substrate 100 includes a substrate main body 101 and an electrical connection layer 102, and a conductive pad 103 is disposed on the electrical connection layer 102.

As shown in fig. 17, the chip with the insulating layer and the substrate may be hybrid bonded so that the conductive portion and the insulating portion of the two are joined, respectively. In addition, the carrier 21 may be removed.

In one example, after the third step, the manufacturing method may further include the steps of:

and fifthly, arranging a second packaging material around the chip. As shown in fig. 18, the second encapsulant 302 may be disposed around the first chip 200a and the second chip 200b in a Molding (Molding) manner.

And sixthly, arranging an external connection structure on the surface of the second packaging material, wherein the external connection structure is electrically connected with the substrate.

In one example, the sixth step may further include the steps of: first, a through hole is formed in the second sealing material. As shown in fig. 3, through holes corresponding to the conductive pillars 303 may be formed in the second encapsulant 302. And secondly, forming a conductive column in the through hole, wherein the first end of the conductive column is electrically connected with the conductive pad on the substrate. As shown in fig. 3, a conductive post 303 may be formed in the through hole by electroplating. The lower ends of the conductive posts may be electrically connected to conductive pads 103 on the substrate 100. Finally, as shown in fig. 3, a conductive element 400 may be disposed at the second end of the conductive post 303. As shown in fig. 8, a redistribution layer 500 may be disposed on the surface of the second encapsulant 302, and the second end of the conductive pillar 303 may be electrically connected to the redistribution layer 500.

The method for manufacturing a semiconductor package device in this embodiment can achieve similar technical effects to those of the semiconductor package device described above, and will not be described herein again.

While the disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration is not intended to limit the disclosure. It will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted in the embodiments without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (10)

1. A semiconductor package device, comprising:

the chip comprises a chip, wherein an active surface and a side surface of the chip are provided with insulating layers;

the surface of the substrate is attached to the insulating layer on the active surface of the chip, and the substrate is electrically connected with the chip.

2. The semiconductor package device of claim 1, wherein the chip and the substrate are electrically connected in a hybrid bond.

3. The semiconductor package device of claim 1, wherein a peripheral dimension of the insulating layer gradually decreases in a direction from the passive surface of the chip to the active surface of the chip.

4. The semiconductor package device according to claim 3, wherein an angle between an outer surface of the insulating layer provided on the side surface of the chip and the active surface of the chip is greater than 60 degrees and less than 80 degrees.

5. The semiconductor package device of claim 1, wherein the chip comprises a first chip and a second chip, and the insulating layer disposed on the side of the first chip and the insulating layer disposed on the side of the second chip are integrally connected.

6. The semiconductor package device according to any one of claims 1 to 5, wherein a second packaging material is provided around the chip.

7. A method of manufacturing a semiconductor package device, comprising:

forming an insulating layer on the active surface and the side surface of the chip;

leveling an insulating layer of an active surface of the chip;

and electrically connecting the chip and the substrate, wherein the surface of the substrate is attached to the insulating layer on the active surface of the chip.

8. The method of claim 7, wherein the method further comprises:

arranging a second packaging material around the chip;

and arranging an external connection structure on the surface of the second packaging material, wherein the external connection structure is electrically connected with the substrate.

9. The method of claim 7, wherein the forming of the insulating layer on the active surface and the side surface of the chip comprises:

placing the chip on a carrier;

arranging photoresist surrounding the chip around the chip;

depositing silicon dioxide on the active surface and the side surface of the chip through physical vapor deposition to form the insulating layer;

and stripping the photoresist.

10. The method of claim 8, wherein the providing an external connection structure on the surface of the second packaging material comprises:

forming a through hole in the second packaging material;

forming a conductive pillar in the through hole, wherein a first end of the conductive pillar is electrically connected with the conductive pad on the substrate;

disposing a conductive element at a second end of the conductive post; or, a redistribution layer is arranged on the surface of the second packaging material, and the second end of the conductive pillar is electrically connected with the redistribution layer.

Images