CN114975235A - Semiconductor packaging structure and preparation method of conductive TIV through hole - Google Patents

Semiconductor packaging structure and preparation method of conductive TIV through hole Download PDF

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Publication number
CN114975235A
CN114975235A CN202111306041.XA CN202111306041A CN114975235A CN 114975235 A CN114975235 A CN 114975235A CN 202111306041 A CN202111306041 A CN 202111306041A CN 114975235 A CN114975235 A CN 114975235A
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Prior art keywords
tiv
layer
metal
conductive
packaging
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Inventor
尹佳山
周祖源
林正忠
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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Priority to CN202111306041.XA priority Critical patent/CN114975235A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor packaging structure and a preparation method of a conductive TIV through hole, wherein the preparation method of the conductive TIV through hole comprises the following steps: and providing a semiconductor structure, and forming a first metal column, a first packaging layer, a dielectric layer, a second metal column and a second packaging layer until a metal column with a preset height is formed. Preparing metal columns with different heights by a method of vertically stacking conductive TIV through holes; a dielectric layer is added between every two packaging layers, so that the binding force between the packaging layers is improved, the packaging layers are prevented from falling off in the subsequent process, and the requirement of mutually communicating a plurality of chips under the condition of high-density circuit is met; compared with the high metal column manufactured by WB technology in the prior art, the high metal column with the vertically stacked conductive TIV through holes can reduce position deviation, improve the reliability of the metal column, reduce gold plating process and reduce cost.

Description

Semiconductor packaging structure and preparation method of conductive TIV through hole
Technical Field
The invention relates to the technical field of advanced semiconductor packaging, in particular to a semiconductor packaging structure and a preparation method of a conductive TIV through hole.
Background
With the development of packaging technology, more and more chips are packaged together under the current demand of higher density circuits, the interconnection between the chips is generally performed through high metal columns, and copper metal is widely used as a raw material of the high metal columns due to the good conductivity and low cost of the copper metal. The conventional method has difficulty to make the length of the copper pillar more than 200 μm, and some special packages require the height of the copper pillar to be very high, for example, more than 1000 μm, so that the fabrication of the high copper pillar is a new packaging challenge.
An Antenna In Package (AiP) is a technology for integrating an Antenna and a chip in a Package based on a Package material and a process to realize a system-level wireless function. At present, AiP a Wire Bonding (WB) method is often used to fabricate a high metal pillar, a gold layer is usually plated on the upper surface of a semiconductor structure, a metal Wire is led on the upper surface of the gold layer as the metal pillar, then a packaging layer is covered, and an antenna layer is formed on the upper surface of the packaging layer after molding and grinding.
In view of the above, there is a need to provide a semiconductor package structure and a method for fabricating conductive tiv (through Interposer via) vias, so as to achieve interconnection of multiple chips through high metal pillars, so as to solve the problems of high cost, poor reliability, low yield, etc. in the conventional technology for fabricating high metal pillars by WB.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a semiconductor package structure and a method for manufacturing a conductive TIV through hole, which are used to solve the problems of high cost of gold plating, poor reliability, and low yield in WB manufacturing process in the prior art.
To achieve the above and other related objects, the present invention provides a semiconductor package structure and a method for fabricating a conductive TIV via, the method comprising:
s1: providing a semiconductor structure;
s2: forming a photoresist layer with a first TIV on the semiconductor structure, then filling metal in the first TIV to form a first metal column, and then removing the photoresist layer;
s3: forming a first packaging layer on the semiconductor structure so as to plastically package the first metal column and expose the top surface of the first metal column;
s4: forming a dielectric layer with a second TIV on the first packaging layer, then filling metal in the second TIV, and enabling the height of the metal to be larger than the depth of the second TIV to form a second metal column;
s5: forming a second packaging layer on the dielectric layer so as to plastically package the second metal column and expose the top surface of the second metal column;
s6: repeating the steps S4 to S5 at least once when the sum of the heights of the first metal pillar and the second metal pillar is less than a preset height until the metal pillar with the preset height is formed.
Optionally, the first metal pillar, the second metal pillar, and the metal pillar are copper pillars.
Optionally, the method of forming the first metal pillar, the second metal pillar, and the metal pillar is an electroless plating method or an electroplating method.
Optionally, the first metal pillar, the second metal pillar and the metal pillar have a radial dimension between 50 μm and 200 μm and a height less than 200 μm.
Optionally, the photoresist layer is removed by a wet etching process, and the wet etching solution is a degumming solution containing dimethyl sulfoxide, ethylene glycol, N-methyl-2-pyrrolidone and tetramethylammonium hydroxide.
Optionally, the second TIV has the same vertical position and radial dimension as the first TIV.
Optionally, the dielectric layer is made of one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass.
Optionally, the method for forming the dielectric layer includes one of plastic package process, compression molding, transfer molding, liquid seal molding, vacuum lamination molding, and spin coating molding.
Optionally, the first encapsulation layer includes a lamination of one or more than two of a polyimide layer, a silicone layer, and an epoxy layer; the second packaging layer comprises one or more than two laminated layers of a polyimide layer, a silica gel layer and an epoxy resin layer.
Optionally, the method for forming the first package layer includes one of a plastic package process, compression molding, transfer molding, liquid package molding, vacuum lamination molding, and spin coating molding; the method for forming the second packaging layer comprises one of plastic packaging technology, compression molding, transfer molding, liquid sealing molding, vacuum lamination molding and spin coating molding.
The invention also provides a preparation method of the semiconductor packaging structure, which comprises the preparation method of the conductive TIV through hole.
Optionally, the semiconductor package structure is a package antenna; the method also comprises the step of forming an antenna layer on the metal post after the metal post is formed.
As described above, the semiconductor package structure and the method for manufacturing the conductive TIV via according to the present invention have the following advantages: the metal columns with different heights can be vertically stacked through the conductive TIV through hole technology, and the dielectric layer is added between every two packaging layers, so that the binding force between the packaging layers is improved, the packaging layers are prevented from falling off in the subsequent process, and the requirement of mutually communicating a plurality of chips under the condition of high-density circuit is met; compared with the high metal columns manufactured by WB technology in the prior art, the high metal columns with the vertically stacked conductive TIV through holes can reduce offset, improve the reliability of the metal columns, reduce gold plating process and reduce cost.
Drawings
FIG. 1 is a schematic flow chart of a method for fabricating a conductive TIV via according to the present invention.
Fig. 2 to 5 are schematic structural views showing steps of a method for manufacturing a metal pillar using WB in the prior art.
Fig. 6 to 11 are schematic structural views showing steps of the method for fabricating a conductive TIV via according to the present invention.
Fig. 12 is a schematic structural diagram of a semiconductor package structure formed by the method for manufacturing a semiconductor package structure according to the present invention, wherein the semiconductor package structure is a package antenna.
Description of the element reference numerals
10 semiconductor structure
101 supporting a substrate
102 separating layers
103 first dielectric layer
104 metal seed layer
1041 Ti Metal seed layer
1042 Cu metal seed layer
105 metal wire layer
106 Au metal layer
20 a photoresist layer
301 first TIV
302 second TIV
40 metal column
401 first metal pillar
402 second metal pillar
403 third metal column
501 first encapsulation layer
502 second encapsulation layer
503 third encapsulation layer
60 dielectric layer
70 antenna layer
701 antenna metal layer
702 antenna connecting wire
S1-S6
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 12. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 2 to 5, a schematic flow chart of a process for manufacturing a conductive TIV via by using a WB process in the prior art is shown, and the manufacturing process is as follows:
as shown in fig. 2, first, a semiconductor structure 10 is provided, wherein an inner portion of an upper surface of the semiconductor structure 10 includes an Au metal layer 106;
as shown in fig. 3, metal wires are then led on the Au metal layer 106 as metal pillars 40;
as shown in fig. 4, a first package layer 501 is formed on the semiconductor structure 10 to mold the metal pillar 40 and expose the top surface of the metal pillar 40;
as shown in fig. 5, an antenna layer 70 is formed on the upper surface of the metal pillar 40.
As shown by research, the inventor finds that if WB technology is used to lead metal wires to make high metal pillars, there are some inevitable problems, and the lead wire is generally required to be performed on the Au metal layer 106, because the gold plating process results in increased cost; the manufacture of high metal columns generally meets some special packaging requirements, the height of the high metal columns is often more than 1000 μm and the requirement on the height is very high, and the radial size of a metal wire led by a WB technology is small, so that the problem of position offset can occur, the open circuit of a device is caused, the reliability is poor, and the yield is low; in addition, flux residue or oxide layer generated in the soldering process of the WB technology can reduce the bonding quality and long-term reliability, and such a dirt layer can directly cause the weakening of the tensile force and the shearing force, and if the bonding energy is not enough, the lead connecting force is not enough, so that the soldered portion is peeled off.
Based on the above findings and through research and analysis, the inventors propose a method for fabricating a conductive TIV via, as shown in fig. 1, to solve the problems of high gold plating cost, poor reliability, low yield, etc. in the WB technology. The method for fabricating the conductive TIV via of the present embodiment is described in detail below with reference to the accompanying drawings.
As shown in fig. 1 and 6, step S1 is performed to provide the semiconductor structure 10.
As shown in fig. 6, the semiconductor structure 10 includes, as an example, a supporting substrate 101, a separation layer 102, and a first dielectric layer 103 in sequence from bottom to top, where the first dielectric layer includes a metal seed layer 104 and a metal wire layer 105.
It should be noted that the supporting substrate 101 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, in this embodiment, a glass layer is preferably used, the glass layer has a low cost, the separation layer 102 is easily formed on the surface of the glass layer, and the difficulty of the subsequent peeling process can be reduced.
The separation layer 102 includes a polymer layer or an adhesive layer, the polymer layer or the adhesive layer is firstly coated on the surface of the supporting substrate 101 by a spin coating process, and then is cured and molded by an ultraviolet curing or thermal curing process, in this embodiment, the polymer layer includes an LTHC light-to-heat conversion layer, and subsequently, when the supporting substrate 101 is peeled off, the LTHC light-to-heat conversion layer may be heated based on laser light, so that the supporting substrate 101 is separated from the LTHC light-to-heat conversion layer, thereby improving the convenience of operation.
The first dielectric layer 103 is made of one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and PI is preferably used in this embodiment, so as to further reduce the process difficulty and the process cost. The method of the first dielectric layer 103 includes one of plastic package process, compression molding, transfer molding, liquid seal molding, vacuum lamination molding and spin coating molding, in this embodiment, spin coating molding is preferably adopted, and the specific thickness of the first dielectric layer 103 is set according to actual needs, which is not limited herein.
The method for forming the metal seed layer 104 and the metal line layer 105 includes one or a combination of a sputtering method, an electroplating method, and a transition method, in this embodiment, the metal seed layer 104 and the metal line layer 105 are selected from the sputtering method, wherein the metal seed layer 104 sequentially includes a Ti metal seed layer 1041 and a Cu metal seed layer 1042 from bottom to top, and the thicknesses of the Ti metal seed layer 1041 and the Cu metal seed layer 1042 may be set according to actual needs, which is not limited herein. In this embodiment, the material of the metal wire layer 105 is electroplated copper, and the thickness of the metal wire layer 105 can be set according to actual needs, which is not limited herein.
As shown in fig. 1, 7(a) and 7(b), step S2 is performed to form a photoresist layer 20 having a first TIV on the semiconductor structure 10 (as shown in fig. 7 (a)), fill the first TIV 301 with metal to form a first metal pillar 401, and remove the photoresist layer 20 (as shown in fig. 7 (b)).
As shown in fig. 7(a) and 7(b), the method for forming the photoresist layer 20 includes one of plastic molding, compression molding, transfer molding, liquid sealing, vacuum lamination molding and spin coating molding, spin coating molding is preferably used in the present embodiment, and the specific thickness of the photoresist layer 20 is set according to actual needs, and is not limited herein.
The photoresist layer 20 is patterned by exposure and development processes to form a photoresist layer having a first TIV 301, and the radial dimension and height of the first TIV 301 are set according to the requirement of an actual metal pillar, which is not limited herein.
As an example, the first metal pillar 401 is a copper pillar, the first metal pillar 401 is electrically connected to the metal line layer 105, and the radial dimension and height of the first metal pillar 401 correspond to the radial dimension and height of the first TIV 301 one to one. The method of forming the first metal posts 401 is electroless plating or electroplating, and electroplating is preferably used in this embodiment.
As an example, the photoresist layer 20 is removed by a wet etching process, and the wet etching solution is a deglued solution containing dimethyl sulfoxide, ethylene glycol, N-methyl-2-pyrrolidone and tetramethylammonium hydroxide.
As shown in fig. 1 and 8, step S3 is performed to form a first package layer 501 on the semiconductor structure 10, so as to mold the first metal pillar 401 and expose the top surface of the first metal pillar 401.
As shown in fig. 8, the first encapsulation layer 501 includes a laminate of one or more of a polyimide layer, a silicone layer, and an epoxy layer, and a method for forming the first encapsulation layer 501 includes one of a plastic molding process, a compression molding process, a transfer molding process, a liquid sealing process, a vacuum lamination process, and a spin coating process. The first package layer 501 is formed by processes of material scattering, heating and melting, mold clamping and cooling, and the like, so that gaps between the first metal columns 401 can be filled, and the first metal columns 401 are plastically packaged.
As an example, if the first package layer 501 completely encapsulates the first metal pillar 401, the first package layer 501 needs to be ground, and the top surface of the first metal pillar 401 is exposed, the method for grinding the first package layer 501 includes one of a chemical mechanical grinding method and a mechanical grinding method, which provides a flat first package layer 501, which is beneficial to reducing the process difficulty of subsequent processing and further improving the quality of subsequent processes.
In another example, the first encapsulation layer 501 may also be formed according to the height of the first metal pillar 401, so that the height of the formed first encapsulation layer 501 is just the same as the height of the first metal pillar 401, i.e., the first encapsulation layer 501 is flush with the surface of the first metal pillar 401. This eliminates the need for grinding the first encapsulation layer 501, thereby simplifying the process steps.
As shown in fig. 1 and 9, step S4 is performed to form a dielectric layer 60 having a second TIV302 on the first package layer 501, and then the second TIV302 is filled with a metal whose height is greater than the depth of the second TIV to form a second metal pillar 402.
As shown in fig. 9, as an example, the material of the dielectric layer 60 is one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and PI is preferably used in this embodiment to further reduce the process difficulty and the process cost. The method of the dielectric layer 60 includes one of plastic package process, compression molding, transfer molding, liquid seal molding, vacuum lamination molding and spin coating molding, in this embodiment, spin coating molding is preferably adopted, and the specific thickness of the dielectric layer 60 is set according to actual needs, which is not limited herein.
The second TIV302 and the second metal post 402 are formed by the same method as the first TIV 301 and the first metal post 401, the second TIV302 is formed by exposure and development processes, the second metal post 402 is formed by electroless plating or electroplating, and electroplating is preferably used in this embodiment; the specific heights of the second TIV302 and the second metal pillar 402 are set according to actual needs, and are not limited herein. The second metal pillar 402 is also a copper pillar.
It should be noted here that the height of the second metal pillar 402 is greater than the depth of the second TIV302, the dielectric layer 60 is only a thin layer, and the dielectric layer 60 is added between two encapsulation layers, so that the bonding force between the encapsulation layers can be improved, and the encapsulation layers can be prevented from falling off in the subsequent process due to the fact that the high metal pillar is too high. The vertical position and radial dimension of the second TIV302 are the same as those of the first TIV 301, and the second TIV302 is used for positioning the formed metal pillars and ensuring that the vertical position and radial dimension of the interconnected metal pillars are the same, so as to manufacture high-reliability and high-yield metal pillars. The first metal column 401 and the second metal column 402 are in the same vertical direction, and the connection mode is electrical connection.
The radial dimensions of the first metal pillar 401 and the second metal pillar 402 are completely the same, and are between 50 μm and 200 μm, including the end point value, in this embodiment, preferably 100 μm and 150 μm are adopted, and compared with the radial dimension of the wire of WB technology, the radial dimension is about 50 μm, a metal pillar with a large radial dimension can be obtained, the structural strength is improved, the device open circuit caused by position offset is avoided, and the process deviation is reduced. The height of each metal pillar formed is less than 200 μm, and 180 μm is preferably used in this embodiment.
As shown in fig. 1 and 10, step S5 is performed to form a second encapsulation layer 502 on the dielectric layer 60, so as to mold the second metal pillar 402 and expose the top surface of the second metal pillar 402.
As shown in fig. 10, the second encapsulation layer 502 is the same as the first encapsulation layer 501, and includes one or more of a polyimide layer, a silicone layer, and an epoxy resin layer, and the second encapsulation layer 502 is formed by the same method as the first encapsulation layer 501, including one of a plastic molding process, a compression molding process, a transfer molding process, a liquid encapsulation molding process, a vacuum lamination molding process, and a spin coating process. The second package layer 502 is formed by processes of material spreading, heating and melting, mold clamping and cooling, and the like, so that the gap between the second metal posts 402 can be filled, and the second metal posts 402 can be plastically packaged.
As an example, if the second package layer 501 completely encapsulates the second metal pillar 402, the second package layer 502 needs to be ground, and the top surface of the second metal pillar 402 is exposed, the method for grinding the second package layer 502 is the same as the method for grinding the first package layer 501, and includes one of a chemical mechanical grinding method and a mechanical grinding method, so as to provide the second package layer 502 with a flat surface, which is beneficial to reducing the process difficulty of subsequent processing and further improving the quality of subsequent processing.
In another example, the second encapsulation layer 5021 can also be formed according to the height of the second metal pillar 402, so that the height of the second encapsulation layer 502 and the height of the dielectric layer 60 are formed to be just the same as the height of the second metal pillar 402, i.e., the second encapsulation layer 502 is flush with the surface of the second metal pillar 402. This eliminates the need for grinding the second encapsulant layer 502, thereby simplifying processing steps.
As shown in fig. 1 and 11, step S6 is finally performed, and when the sum of the heights of the first metal pillar 401 and the second metal pillar 402 is less than a predetermined height, steps S4 to S5 are repeated at least once until the metal pillar with the predetermined height is formed.
As shown in fig. 11, as an example, steps S4 to S5 are repeated once, a metal pillar is formed by a vertical stacking method, and 3 layers of metal pillars are stacked to reach a predetermined height.
Based on the above method for preparing the conductive TIV via, this embodiment also provides a method for preparing a semiconductor package structure, where the method for preparing the conductive TIV via includes the above method for preparing the conductive TIV via.
In this embodiment, the semiconductor package structure is a package antenna; the method also comprises the step of forming an antenna layer on the metal post after the metal post is formed.
As shown in fig. 12, the semiconductor package structure is a package antenna, and an antenna layer 70 is further formed on the metal pillar after the metal pillar is formed. Preferably, the antenna layer 70 includes a metal antenna layer 701 and an antenna connection line 702, and in this embodiment, the metal antenna layer 701 is preferably a Ni metal antenna layer.
In summary, the invention provides a semiconductor package structure and a method for manufacturing a conductive TIV through hole, which can vertically stack metal pillars with different heights as required by using a conductive TIV through hole technology, and add a dielectric layer between every two package layers to improve the bonding force between the package layers, thereby preventing the package layers from falling off in subsequent processes and satisfying the requirement of interconnecting a plurality of chips under the condition of high-density circuit; compared with the high metal column manufactured by WB technology in the prior art, the high metal column stacked by the conductive TIV through holes can reduce position deviation, improve the reliability of the metal column, reduce gold plating process and reduce cost. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (12)

1. A method for preparing a conductive TIV via, comprising the steps of:
s1: providing a semiconductor structure;
s2: forming a photoresist layer with a first TIV on the semiconductor structure, then filling metal in the first TIV to form a first metal column, and then removing the photoresist layer;
s3: forming a first packaging layer on the semiconductor structure so as to plastically package the first metal column and expose the top surface of the first metal column;
s4: forming a dielectric layer with a second TIV on the first packaging layer, then filling metal in the second TIV, and enabling the height of the metal to be larger than the depth of the second TIV to form a second metal column;
s5: forming a second packaging layer on the dielectric layer so as to plastically package the second metal column and expose the top surface of the second metal column;
s6: when the sum of the heights of the first metal pillar and the second metal pillar is less than a preset height, repeating the steps S4 to S5 at least once until the metal pillar with the preset height is formed.
2. The method of making a conductive TIV via of claim 1, wherein: the first metal column, the second metal column and the metal column are all copper columns.
3. The method of making a conductive TIV via of claim 1, wherein: the method of forming the first metal pillar, the second metal pillar, and the metal pillar is an electroless plating method or an electroplating method.
4. The method of making a conductive TIV via of claim 1, wherein: the first metal column, the second metal column and the metal column have radial sizes between 50 μm and 200 μm and heights less than 200 μm.
5. The method of making a conductive TIV via of claim 1, wherein: and removing the photoresist layer by adopting a wet etching process, wherein a wet etching solution is a degumming solution containing dimethyl sulfoxide, ethylene glycol, N-methyl-2-pyrrolidone and tetramethyl ammonium hydroxide.
6. The method of making a conductive TIV via of claim 1, wherein: the second TIV has the same vertical position and radial dimensions as the first TIV.
7. The method of making a conductive TIV via of claim 1, wherein: the dielectric layer is made of one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass.
8. The method of making a conductive TIV via of claim 1, wherein: the method for forming the dielectric layer comprises one of plastic package technology, compression molding, transfer molding, liquid seal molding, vacuum lamination molding and spin coating molding.
9. The method of making a conductive TIV via of claim 1, wherein: the first packaging layer comprises one or more than two laminated layers of a polyimide layer, a silica gel layer and an epoxy resin layer; the second packaging layer comprises one or more than two laminated layers of a polyimide layer, a silica gel layer and an epoxy resin layer.
10. The method of making a conductive TIV via of claim 1, wherein: the method for forming the first packaging layer comprises one of plastic packaging technology, compression molding, transfer molding, liquid sealing molding, vacuum lamination molding and spin coating molding; the method for forming the second packaging layer comprises one of plastic packaging technology, compression molding, transfer molding, liquid sealing molding, vacuum lamination molding and spin coating molding.
11. A preparation method of a semiconductor packaging structure is characterized by comprising the following steps: a method of making a conductive TIV via comprising any of claims 1-10.
12. The method of manufacturing a semiconductor package structure according to claim 11, wherein: the semiconductor packaging structure is a packaging antenna; the method also comprises the step of forming an antenna layer on the metal post after the metal post is formed.
CN202111306041.XA 2021-11-05 2021-11-05 Semiconductor packaging structure and preparation method of conductive TIV through hole Pending CN114975235A (en)

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