CN114974157A - Display panel and display device - Google Patents
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- CN114974157A CN114974157A CN202210362460.3A CN202210362460A CN114974157A CN 114974157 A CN114974157 A CN 114974157A CN 202210362460 A CN202210362460 A CN 202210362460A CN 114974157 A CN114974157 A CN 114974157A
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- 239000003990 capacitor Substances 0.000 claims description 42
- 239000010409 thin film Substances 0.000 claims description 30
- 239000000126 substance Substances 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 description 18
- 239000000758 substrate Substances 0.000 description 17
- 239000004973 liquid crystal related substance Substances 0.000 description 13
- 101150037603 cst-1 gene Proteins 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 9
- 239000010410 layer Substances 0.000 description 9
- 238000002161 passivation Methods 0.000 description 6
- 239000002346 layers by function Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application discloses display panel and display device, this display panel includes: the pixel structure comprises a data line, a scanning line, a first pixel unit and a second pixel unit, wherein the scanning line and the data line are arranged in an intersecting manner, and the scanning line comprises a first scanning line and a second scanning line which are arranged along a first direction; the first pixel unit is electrically connected with the data line and the first scanning line, the first pixel unit comprises a first pixel electrode and a first common electrode, the second pixel unit is adjacently arranged with the first pixel unit along a second direction, the second pixel unit is electrically connected with the data line and the second scanning line, and the second pixel unit comprises a second pixel electrode and a second common electrode; the overlapping area of the first common electrode and the first pixel electrode is smaller than the overlapping area of the second common electrode and the second pixel electrode. The display panel can solve the problem of uneven display brightness caused by different feed-through voltages.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
The related art liquid crystal display panel driving circuit includes: scanning line, data line, thin film transistor, liquid crystal capacitor and storage capacitor. The liquid crystal capacitor is composed of a pixel electrode arranged on the first substrate and a common electrode arranged on the second substrate; the storage capacitor is composed of a pixel electrode and a common electrode arranged on the first substrate. The gate electrode of the thin film transistor is electrically connected to the scan line, the source electrode is electrically connected to the data line, and the drain electrode is electrically connected to the pixel electrode.
Since a parasitic capacitance is formed between the scan line and the drain electrode, the parasitic capacitance introduces the scan signal to the pixel electrode at the moment when the thin film transistor is turned off, thereby reducing the voltage applied to the pixel electrode, and the reduced voltage is referred to as a feedthrough voltage. The pixel unit far away from the data line in the two pixel units sharing the data line and arranged along the row direction has more lateral electric fields to the pixel unit than the pixel unit near the data line, so that parasitic capacitance formed between the scanning line and the drain electrode of the pixel unit far away from the data line is larger, feed-through voltage of the pixel unit far away from the data line is larger than that of the pixel unit near the data line, and further, the defect of uneven brightness exists in a low-gray-level picture, and the display quality is influenced.
Disclosure of Invention
The application provides a display panel and display device, through the different influence to feed-through voltage of adjustment storage capacitor with balanced parasitic capacitance, can solve the uneven problem of demonstration luminance that the feed-through voltage difference leads to.
In a first aspect, an embodiment of the present application provides a display panel, including: the pixel structure comprises a data line, a scanning line, a first pixel unit and a second pixel unit, wherein the scanning line and the data line are arranged in an intersecting manner, and the scanning line comprises a first scanning line and a second scanning line which are arranged along a first direction; the first pixel unit is electrically connected with the data line and the first scanning line, and comprises a first pixel electrode and a first common electrode; the second pixel unit and the first pixel unit are adjacently arranged along a second direction, the second pixel unit is electrically connected with the data line and the second scanning line, and the second pixel unit comprises a second pixel electrode and a second common electrode; wherein an overlapping area of the first common electrode and the first pixel electrode is smaller than an overlapping area of the second common electrode and the second pixel electrode.
Optionally, in some embodiments of the present application, the first pixel unit further includes a first thin film transistor including a first gate electrode, a first source electrode, and a first drain electrode, the first gate electrode is electrically connected to the first scan line, one of the first source electrode and the first drain electrode is electrically connected to the data line, and the other of the first source electrode and the first drain electrode is electrically connected to the first pixel electrode; the first common electrode and the first pixel electrode are overlapped to form a first storage capacitor; the second pixel unit further comprises a second thin film transistor, the second thin film transistor comprises a second gate, a second source and a second drain, the second gate is electrically connected with the second scanning line, one of the second source and the second drain is electrically connected with the data line, the other of the second source and the second drain is electrically connected with the second pixel electrode, and the second common electrode and the second pixel electrode are overlapped to form a second storage capacitor.
Optionally, in some embodiments of the present application, an area of the first pixel electrode is smaller than an area of the second pixel electrode.
Optionally, in some embodiments of the present application, an overlapping portion of the first common electrode and the first pixel electrode is a hollow structure.
Optionally, in some embodiments of the present application, the first pixel electrode includes a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode and the second sub-pixel electrode are disposed at an interval, and the first sub-pixel electrode partially overlaps the first common electrode and the second sub-pixel electrode partially overlaps the first common electrode.
Optionally, in some embodiments of the present application, an area of the hollow structure is smaller than an area of the first sub-pixel electrode, and/or an area of the hollow structure is smaller than an area of the second sub-pixel electrode.
Optionally, in some embodiments of the present application, an area of the first pixel electrode is equal to an area of the second pixel electrode.
Optionally, in some embodiments of the present application, a distance between the first common electrode and the first pixel electrode is greater than a distance between the second common electrode and the second pixel electrode.
Optionally, in some embodiments of the present application, the first common electrode and the second common electrode are arranged in a staggered manner.
In another aspect, the present application provides a display device, including the display panel and a backlight module, where the backlight module is configured to provide a light source to the display panel.
The application provides a display panel and a display device, wherein the display panel comprises data lines, scanning lines, a first pixel unit and a second pixel unit, the scanning lines and the data lines are arranged in an intersecting manner, and the scanning lines comprise first scanning lines and second scanning lines which are distributed along a first direction; the first pixel unit is electrically connected with the data line and the first scanning line, and comprises a first pixel electrode and a first common electrode; the second pixel unit and the first pixel unit are adjacently arranged along a second direction, the second pixel unit is electrically connected with the data line and the second scanning line, and the second pixel unit comprises a second pixel electrode and a second common electrode; wherein an overlapping area of the first common electrode and the first pixel electrode is smaller than an overlapping area of the second common electrode and the second pixel electrode. The display panel of this application can solve the uneven problem of demonstration luminance that feedthrough voltage difference leads to through the different influence to feedthrough voltage of storage capacitor with the balance parasitic capacitance difference through the adjustment, promotes the display effect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic diagram of a first pixel structure of a display panel according to an embodiment of the present disclosure;
fig. 2 is a circuit diagram of a display panel provided in an embodiment of the present application;
fig. 3 is a cross-sectional view of a display panel provided in an embodiment of the present application;
fig. 4 is a schematic diagram of a second pixel structure of a display panel according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a third pixel structure of a display panel according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating a fourth pixel structure of a display panel according to an embodiment of the present disclosure;
FIG. 7 is a cross-sectional view of the display panel shown in FIG. 6 taken along the direction A-A';
fig. 8 is a cross-sectional view of a display device provided in an embodiment of the present application.
Wherein the content of the first and second substances,
100/200/300/400/500, a display panel, 10, a first pixel unit, 11, a first pixel electrode, 111, a first sub-pixel electrode, 112, a second sub-pixel electrode, 12, a first common electrode, 13, a first thin film transistor, 20, a second pixel unit, 21, a second pixel electrode, 22, a second common electrode, 23, a second thin film transistor, 30, a hollow, 40, an array substrate, 41, a substrate, 42, a functional layer, 43, a passivation layer, 50, a color film substrate, 60, a liquid crystal, 70, a backlight module, 600, and a display device.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides a display panel and display device, through adjusting storage capacitor with the influence of balanced parasitic capacitance difference to feed-through voltage, can solve the uneven problem of display brightness that feed-through voltage difference leads to. The following are detailed below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments. In addition, in the description of the present application, the term "including" means "including but not limited to". The terms "first," "second," "third," and the like are used merely as labels to distinguish between different objects and not to describe a particular order.
Referring to fig. 1 to 3, fig. 1 is a schematic view illustrating a first pixel structure of a display panel according to an embodiment of the present disclosure; fig. 2 is a circuit diagram of a display panel provided in an embodiment of the present application; fig. 3 is a cross-sectional view of a display panel provided in an embodiment of the present application. As shown in fig. 1 and 2, an embodiment of the present application provides a display panel 100, including: DATA lines DATA, scan lines GATE, the first pixel unit 10, and the second pixel unit 20, the scan lines GATE intersecting the DATA lines DATA, the scan lines GATE including a first scan line GATE1 and a second scan line GATE2 arranged in a first direction; the first pixel unit 10 is electrically connected to the DATA line DATA and the first scan line GATE1, the first pixel unit 10 includes the first pixel electrode 11 and the first common electrode 12, the second pixel unit 20 is disposed adjacent to the first pixel unit 10 along the second direction, the second pixel unit 20 is electrically connected to the DATA line DATA and the second scan line GATE2, and the second pixel unit 20 includes the second pixel electrode 21 and the second common electrode 22; the overlapping area of the first common electrode 12 and the first pixel electrode 11 is smaller than the overlapping area of the second common electrode 22 and the second pixel electrode 21.
The application provides a display panel 100 is through the influence of adjustment storage capacitor with the difference of balanced parasitic capacitance to feed-through voltage, and then solves the uneven problem of demonstration luminance that the feed-through voltage difference leads to, promotes display effect.
In the embodiment of the present application, the first pixel unit 10 includes a first thin film transistor 13, a first pixel electrode 11 and a first common electrode 12, the first thin film transistor 13 includes a first GATE g1, a first source s1 and a first drain d1, the first GATE g1 is electrically connected to the first scan line GATE1, one of the first source s1 and the first drain d1 is electrically connected to the DATA line DATA, and the other of the first source s1 and the first drain d1 is electrically connected to the first pixel electrode 11; the first common electrode 12 overlaps the first pixel electrode 11 to form a first storage capacitor Cst 1; the second pixel unit 20 includes a second thin film transistor 23, a second pixel electrode 21 and a second common electrode 22, the second thin film transistor 23 includes a second GATE g2, a second source s2 and a second drain d2, the second GATE g2 is electrically connected to the second scan line GATE2, one of the second source s2 and the second drain d2 is electrically connected to the DATA line DATA, the other of the second source s2 and the second drain d2 is electrically connected to the second pixel electrode 21, and the second common electrode 22 overlaps the second pixel electrode 21 to form a second storage capacitor Cst 2.
In the embodiment of the present application, the area of the first pixel electrode 11 is smaller than that of the second pixel electrode 21, so that the capacitance value of the first storage capacitor Cst1 is smaller than that of the second storage capacitor Cst 2. Preferably, the area of the first common electrode 12 is equal to the area of the first pixel electrode 11, and the area of the second common electrode 22 is equal to the area of the second pixel electrode 21.
As shown in fig. 3, the display panel 100 includes an array substrate 40 and a color filter substrate 50 which are oppositely disposed at an interval, and a liquid crystal 60 sandwiched between the array substrate 40 and the color filter substrate 50, wherein the liquid crystal 60 is located in a liquid crystal 60 box formed by overlapping and combining the array substrate 40 and the color filter substrate 50.
Note that, a common electrode (not shown) is disposed on the color filter substrate 50, wherein the liquid crystal 60 capacitor is formed by the first pixel electrode 11/the second pixel electrode 21 disposed on the array substrate 40 and the common electrode disposed on the color filter substrate 50.
In the driving process of the display panel 100, a scan signal is applied to the GATE of the thin film transistor through the scan line GATE to turn on the thin film transistor, and a DATA signal is applied to the source of the thin film transistor through the DATA line DATA. When the thin film transistor is in an on state by a scan signal, a data signal is applied to the pixel electrode of the liquid crystal 60 capacitor through the drain electrode of the thin film transistor. When the voltage applied across the capacitance of the liquid crystal 60 changes, the direction of deflection of the liquid crystal 60 molecules in the layer of liquid crystal 60 also changes, thereby controlling the light transmittance through the pixel cell and thus the display brightness of each pixel cell.
Due to the existence of the parasitic capacitor, at the moment when the thin film transistor is turned off, the parasitic capacitor introduces a scanning signal to the pixel electrode, so that the voltage loaded on the pixel electrode is reduced, the reduced voltage is called feed-through voltage, the pixel voltage is coupled downwards due to the existence of the feed-through voltage, the voltage of the originally balanced common electrode is deviated, and if the adjustment is not carried out in time, the display screen flickers. The larger the pixel voltage variation, the greater the likelihood of the panel developing frame sticking and reliability problems. The equation for the feedthrough voltage is:
where Δ Vp is a change in pixel voltage due to a change in scanning voltage via the coupling capacitor, Vgh is a turn-on voltage of the TFT transistor to which the scanning voltage is input, Vgl is a turn-off voltage of the TFT transistor to which the scanning voltage is input, Cgs is a parasitic capacitor, Clc is a liquid crystal 60 capacitor, and Cst is a storage capacitor.
In the embodiment of the present application, the first pixel unit 10 and the second pixel unit 20 share the DATA line DATA and are arranged along the second direction, and the second pixel unit 20 has a larger lateral electric field to the scan line GATE than the first pixel unit 10, which results in a larger parasitic capacitance formed between the scan line GATE and the drain of the second pixel unit 20, and the feed-through voltage of the second pixel unit 20 is larger than the feed-through voltage of the first pixel unit 10, so that the overlapping area of the first common electrode 12 and the first pixel electrode 11 needs to be adjusted to adjust the capacitance value of the first storage capacitor Cst1, so that the capacitance value of the first storage capacitor Cst1 is smaller than the capacitance value of the second storage capacitor Cst2, and further, the difference of the feed-through voltage between the first pixel unit 10 and the second pixel unit 20 is balanced, and the brightness of the display panel is uniform, thereby improving the display effect.
The display panel 100 provided by the present application sets the area of the first pixel electrode 11 to be smaller than the area of the second pixel electrode 21, so that the overlapping area between the first common electrode 12 and the first pixel electrode 11 is smaller than the overlapping area between the second common electrode 22 and the second pixel electrode 21, and further the first storage capacitor Cst1 is smaller than the second storage capacitor Cst2, so as to balance that the parasitic capacitor Cgs1 between the first pixel unit 10 and the first scan line GATE1 is smaller than the parasitic capacitor Cgs2 between the second pixel unit 20 and the second scan line GATE2, so that the feed-through voltage difference between the first pixel unit 10 and the second pixel unit 20 is solved, and the display luminance feed-through problem caused by the difference in voltage is solved, thereby improving the display effect.
As an embodiment of the present application, please refer to fig. 4, where fig. 4 is a schematic diagram of a second pixel structure of a display panel according to an embodiment of the present application. As shown in fig. 4, the present application provides a display panel 200, and the difference between the display panel 200 and the display panel 100 is: the overlapping portion of the first common electrode 12 and the first pixel electrode 11 is a hollow 30 structure. The hollow-out 30 regions are disposed on the first common electrode 12 at intervals.
In the embodiment of the present application, the first pixel electrode 11 partially overlaps the first common electrode 12, an overlapping portion of the first common electrode 12 corresponding to the first pixel electrode 11 is a hollow 30 structure, and an area of the hollow 30 structure is smaller than an area of the first pixel electrode 11.
In the embodiment of the present application, the first pixel unit 10 includes a first thin film transistor 13, a first pixel electrode 11 and a first common electrode 12, the first thin film transistor 13 includes a first GATE g1, a first source s1 and a first drain d1, the first GATE g1 is electrically connected to the first scan line GATE1, one of the first source s1 and the first drain d1 is electrically connected to the DATA line DATA, and the other of the first source s1 and the first drain d1 is electrically connected to the first pixel electrode 11.
The application provides a display panel 200 is through setting up fretwork 30 structure on first common electrode 12 to reduce the area of overlap between first common electrode 12 and the first pixel electrode 11, and then reduce first storage capacitor Cst1 with the different influence to feed through voltage of the difference of parasitic capacitance between the balanced adjacent pixel cell, and then solve the uneven problem of display brightness that feed through voltage difference leads to, promote display effect.
As an embodiment of the present application, please refer to fig. 5, in which fig. 5 is a schematic diagram of a third pixel structure of a display panel according to an embodiment of the present application. As shown in fig. 5, the present application provides a display panel 300, and the difference between the display panel 300 and the display panel 200 is: the first pixel electrode 11 includes a first sub-pixel electrode 111 and a second sub-pixel electrode 112, the first sub-pixel electrode 111 and the second sub-pixel electrode 112 are disposed at intervals, and the first sub-pixel electrode 111 and the first common electrode 12 partially overlap with each other and the second sub-pixel electrode 112 and the first common electrode 12 partially overlap with each other.
In the embodiment of the present disclosure, the first sub-pixel electrode 111 partially overlaps the first common electrode 12, and/or the second sub-pixel electrode 112 partially overlaps the first common electrode 12, an overlapping portion of the first common electrode 12 corresponding to the first sub-pixel electrode 111/the second sub-pixel electrode 112 is a hollow 30 structure, and an area of the hollow 30 structure is smaller than an area of the first sub-pixel electrode 111, and/or an area of the hollow 30 structure is smaller than an area of the second sub-pixel electrode 112.
In the embodiment of the present application, the first pixel unit 10 includes a first thin film transistor 13, a first pixel electrode 11 and a first common electrode 12, the first thin film transistor 13 includes a first GATE g1, a first source s1 and a first drain d1, the first GATE g1 is electrically connected to the first scan line GATE1, one of the first source s1 and the first drain d1 is electrically connected to the DATA line DATA, and the other of the first source s1 and the first drain d1 is electrically connected to the first pixel electrode 11.
The display panel 300 provided by the present application sets the hollow 30 structure on the first common electrode 12, and sets the first pixel electrode 11 as the first sub-pixel electrode 111 and the second sub-pixel electrode 112, the overlapping portion of the first common electrode 12 corresponding to the first sub-pixel electrode 111/the second sub-pixel electrode 112 is the hollow 30 structure, so as to reduce the overlapping area between the first common electrode 12 and the first pixel electrode 11, and further reduce the influence of the difference of the parasitic capacitance between the first storage capacitor Cst1 and the adjacent pixel units on the feed-through voltage, and further solve the problem of the uneven display brightness caused by the difference of the feed-through voltage, and improve the display effect.
As an embodiment of the present application, please refer to fig. 6, where fig. 6 is a schematic diagram of a fourth pixel structure of a display panel according to an embodiment of the present application. As shown in fig. 6, the present application provides a display panel 400, and the display panel 400 is different from the display panel 200 in that: the area of the first pixel electrode 11 is equal to the area of the second pixel electrode 21.
In the embodiment of the present application, the overlapping portion of the first common electrode 12 and the first pixel electrode 11 is a hollow 30 structure. The hollow-out 30 regions are disposed on the first common electrode 12 at intervals.
In the embodiment of the present application, the first pixel electrode 11 partially overlaps the first common electrode 12, an overlapping portion of the first common electrode 12 corresponding to the first pixel electrode 11 is a hollow 30 structure, and an area of the hollow 30 structure is smaller than an area of the first pixel electrode 11.
In the embodiment of the present application, the first pixel unit 10 includes a first thin film transistor 13, a first pixel electrode 11 and a first common electrode 12, the first thin film transistor 13 includes a first GATE g1, a first source s1 and a first drain d1, the first GATE g1 is electrically connected to the first scan line GATE1, one of the first source s1 and the first drain d1 is electrically connected to the DATA line DATA, and the other of the first source s1 and the first drain d1 is electrically connected to the first pixel electrode 11; the first common electrode 12 overlaps the first pixel electrode 11 to form a first storage capacitor Cst 1; the second pixel unit 20 includes a second thin film transistor 23, a second pixel electrode 21 and a second common electrode 22, the second thin film transistor 23 includes a second GATE g2, a second source s2 and a second drain d2, the second GATE g2 is electrically connected to the second scan line GATE2, one of the second source s2 and the second drain d2 is electrically connected to the DATA line DATA, the other of the second source s2 and the second drain d2 is electrically connected to the second pixel electrode 21, and the second common electrode 22 overlaps the second pixel electrode 21 to form a second storage capacitor Cst 2.
The application provides a display panel 400 is through setting up fretwork 30 structure on first common electrode 12 to reduce the area of overlap between first common electrode 12 and the first pixel electrode 11, and then reduce first storage capacitor Cst1 with the different influence to feed through voltage of the difference of parasitic capacitance between the balanced adjacent pixel cell, and then solve the uneven problem of display brightness that feed through voltage difference leads to, promote display effect.
Referring to fig. 7 as an embodiment of the present application, fig. 7 is a cross-sectional view of the display panel shown in fig. 6 along a direction a-a'. As shown in fig. 7, the present application provides a display panel 500, and the difference between the display panel 500 and the display panel 100 is: the distance between the first common electrode 12 and the first pixel electrode 11 is greater than the distance between the second common electrode 22 and the second pixel electrode 21.
In the embodiment of the present application, the first common electrodes 12 are arranged to be different layers from the second common electrodes 22.
In the embodiment of the present application, the pixel structure of the display panel includes a substrate 41, a first common electrode 12, a functional layer 42 (including an insulating layer for insulation and a thin film transistor), a second common electrode 22, a passivation layer 43, a first pixel electrode 11, and a second pixel electrode 21. The first common electrode 12 is located above the substrate 41, the first common electrode 12 has a hollow 30 structure disposed at an interval, the functional layer 42 covers the first common electrode 12, the second common electrode 22 is disposed on the functional layer 42 and staggered with the first common electrode 12, the passivation layer 43 covers the second common electrode 22, the first pixel electrode 11 and the second pixel electrode 21 are disposed on the passivation layer 43 at an interval, the first pixel electrode 11 and the first common electrode 12 are partially overlapped, the overlapping portion of the first common electrode 12 corresponding to the first pixel electrode 11 is a hollow 30 structure, and the area of the hollow 30 structure is smaller than that of the pixel electrode.
It should be noted that the specific implementation manner (not shown in the figure) of the present embodiment includes: the thickness of the first pixel electrode 11 is the same as that of the second pixel electrode 21, and the thickness of the first common electrode 12 is smaller than that of the second common electrode 22.
The specific implementation manner (not shown in the figure) of this embodiment further includes: the thickness of the first common electrode 12 is the same as that of the second common electrode 22, and the thickness of the first pixel electrode 11 is smaller than that of the second pixel electrode 21.
The specific implementation manner (not shown in the figure) of this embodiment further includes: the thickness of the passivation layer 43 at the position corresponding to the first pixel electrode 11 is greater than the thickness of the passivation layer 43 at the position corresponding to the second pixel electrode 21.
In the embodiment of the present application, the distance between the first common electrode 12 and the first pixel electrode 11 is greater than the distance between the second common electrode 22 and the second pixel electrode 21, so as to reduce the first storage capacitor Cst1 to balance the influence of the difference in parasitic capacitance between adjacent pixel units on the feed-through voltage, thereby solving the problem of uneven display brightness caused by the difference in feed-through voltage, and improving the display effect.
Referring to fig. 8, fig. 8 is a cross-sectional view of a display device according to an embodiment of the present disclosure. The present application further provides a display device 600, and the display device 600 includes the above display panel and the backlight module 70 providing a light source for the display panel.
The application provides a display panel and a display device, the display panel includes DATA lines DATA, scanning lines GATE, a first pixel unit 10 and a second pixel unit 20, the scanning lines GATE and the DATA lines DATA are arranged in an intersecting manner, the scanning lines GATE includes a first scanning line GATE1 and a second scanning line GATE2 arranged along a first direction; the first pixel unit 10 is electrically connected to the DATA line DATA and the first scan line GATE1, and the first pixel unit 10 includes a first storage capacitor Cst 1; the second pixel unit 20 is disposed adjacent to the first pixel unit 10 along the second direction, the second pixel unit 20 is electrically connected to the DATA line DATA and the second scan line GATE2, and the second pixel unit 20 includes a second storage capacitor Cst 2; the capacitance value of the first storage capacitor Cst1 is smaller than that of the second storage capacitor Cst 2. The display panel of this application can solve the uneven problem of demonstration luminance that feedthrough voltage difference leads to through the different influence to feedthrough voltage of storage capacitor with the balance parasitic capacitance difference through the adjustment, promotes the display effect.
The display panel and the display device provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein by applying specific examples, and the description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display panel, comprising:
a data line;
the scanning lines are intersected with the data lines and comprise first scanning lines and second scanning lines which are arranged along a first direction;
a first pixel unit electrically connected to the data line and the first scan line, the first pixel unit including a first pixel electrode and a first common electrode;
the second pixel unit and the first pixel unit are adjacently arranged along a second direction, the second pixel unit is electrically connected with the data line and the second scanning line, and the second pixel unit comprises a second pixel electrode and a second common electrode; wherein the content of the first and second substances,
the overlapping area of the first common electrode and the first pixel electrode is smaller than the overlapping area of the second common electrode and the second pixel electrode.
2. The display panel according to claim 1, wherein the first pixel unit further comprises a first thin film transistor including a first gate electrode, a first source electrode, and a first drain electrode, wherein the first gate electrode is electrically connected to the first scan line, wherein one of the first source electrode and the first drain electrode is electrically connected to the data line, and wherein the other of the first source electrode and the first drain electrode is electrically connected to the first pixel electrode; the first common electrode and the first pixel electrode are overlapped to form a first storage capacitor;
the second pixel unit further comprises a second thin film transistor, the second thin film transistor comprises a second gate, a second source and a second drain, the second gate is electrically connected with the second scanning line, one of the second source and the second drain is electrically connected with the data line, the other of the second source and the second drain is electrically connected with the second pixel electrode, and the second common electrode and the second pixel electrode are overlapped to form a second storage capacitor.
3. The display panel according to claim 2, wherein an area of the first pixel electrode is smaller than an area of the second pixel electrode.
4. The display panel according to claim 2, wherein an overlapping portion of the first common electrode and the first pixel electrode is a hollow structure.
5. The display panel according to claim 4, wherein the first pixel electrode comprises a first sub-pixel electrode and a second sub-pixel electrode, the first sub-pixel electrode and the second sub-pixel electrode are arranged at intervals, and the first sub-pixel electrode and the first common electrode and the second sub-pixel electrode partially overlap with the first common electrode.
6. The display panel according to claim 4 or 5, wherein the area of the hollow structure is smaller than the area of the first sub-pixel electrode, and/or the area of the hollow structure is smaller than the area of the second sub-pixel electrode.
7. The display panel according to claim 6, wherein an area of the first pixel electrode is equal to an area of the second pixel electrode.
8. The display panel according to claim 2, wherein a distance between the first common electrode and the first pixel electrode is larger than a distance between the second common electrode and the second pixel electrode.
9. The display panel according to claim 8, wherein the first common electrode and the second common electrode are arranged in a different layer.
10. A display device comprising the display panel of any one of claims 1-9 and a backlight module for providing a light source to the display panel.
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