CN114974124A - Display driving circuit, display device, and method of operating display driving circuit - Google Patents

Abstract

A display driving circuit, a display device, and an operation method of the display driving circuit may be provided. The display drive circuit includes: a reference voltage generator configured to generate a plurality of reference voltages; a buffer circuit configured to generate an output voltage based on a reference voltage applied to an input node of the buffer circuit among the reference voltages; and a precharge circuit configured to precharge the input node based on a first control signal in a transition period, the transition period being a period between a first time point at which a first reference voltage is applied to the input node and a second time point at which a second reference voltage is applied to the input node.

Description

Display driving circuit, display device, and method of operating display driving circuit

Cross Reference to Related Applications

This application is based on and claimed at the priority of korean patent application No.10-2021-0022031, which was filed at the korean intellectual property office at 18.2.2021, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present inventive concept relates to a semiconductor device, and more particularly, to a display driving circuit in which crosstalk is reduced when Adaptive Fast Voltage Tracking (AFVT) is applied to a display apparatus, a display apparatus including the same, and/or an operation method of the display driving circuit.

Background

Display devices are widely used in smart phones, notebook computers, and monitors, and include a display panel that displays images. A plurality of pixels are provided in the display panel. When a plurality of pixels are driven by data signals supplied from a display driver Integrated Circuit (IC), the display panel implements an image.

As the resolution increases due to the enlargement of the screen size of the display device, defective image quality such as crosstalk may occur when the reference voltage generator supplies the reference voltage to the display panel through the buffer circuit. An electrical interference phenomenon in which an undesired pixel is adversely affected when driving an adjacent pixel in a display panel is referred to as crosstalk.

Disclosure of Invention

The present inventive concept provides a display driving circuit, a display device including the same, and/or an operation method of the display driving circuit that reduces noise such as crosstalk by precharging with a reference voltage in supplying the reference voltage to a display panel using a push-pull circuit and a voltage selection circuit.

According to an aspect of the inventive concept, a display driving circuit may include: a reference voltage generator configured to generate a plurality of reference voltages; a buffer circuit configured to generate an output voltage based on a reference voltage applied to an input node of the buffer circuit among the reference voltages; and a precharge circuit configured to precharge the input node based on a first control signal in a transition period, the transition period being a period between a first time point at which a first reference voltage is applied to the input node and a second time point at which a second reference voltage is applied to the input node.

According to another aspect of the inventive concept, an operating method of a display driving circuit may include: generating a first control signal precharging an input node in a transition period, the transition period being a period between a first time point of applying a first reference voltage to the input node and a second time point of applying a second reference voltage to the input node; precharging the input node based on the first control signal; applying the second reference voltage to the input node; and generating an output voltage based on the second reference voltage.

According to still another aspect of the inventive concept, a display apparatus may include: a display panel; and a display driving circuit configured to drive the display panel so that the display panel displays an image. The display driving circuit may include: a reference voltage generator configured to generate a plurality of reference voltages; a buffer circuit configured to generate an output voltage with a reference voltage applied to an input node of the buffer circuit among the reference voltages; the circuit includes a precharge circuit configured to precharge the input node based on a first control signal, and a controller configured to generate the first control signal precharging the input node in a transition period, the transition period being a period between a first time point at which a first reference voltage is applied to the input node and a second time point at which a second reference voltage is applied to the input node.

Drawings

Some example embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a block diagram illustrating a display apparatus and a display system including the display apparatus according to an example embodiment;

fig. 2 is a block diagram illustrating a display driving circuit and a display panel according to an example embodiment;

fig. 3 is a block diagram schematically illustrating a display driving circuit according to an example embodiment;

FIG. 4 is a block diagram schematically illustrating a voltage tracking circuit according to an example embodiment;

FIG. 5 is a circuit diagram illustrating a reference voltage generator according to an example embodiment;

FIG. 6 is a block diagram schematically illustrating a voltage tracking circuit according to an example embodiment;

fig. 7A is a circuit diagram showing a voltage tracking circuit according to an example embodiment, and fig. 7B is a graph for describing an operation signal of fig. 7A;

fig. 8A is a circuit diagram illustrating a reference voltage generator and a buffer circuit according to an example embodiment, and fig. 8B is a graph for describing an operation signal of fig. 8A;

FIG. 9 is a circuit diagram illustrating a voltage selection circuit according to an example embodiment;

fig. 10 is a flowchart illustrating an operation method of a display driving circuit according to an example embodiment;

fig. 11 shows an implementation example of a display device according to an example embodiment; and

fig. 12 shows an implementation example of a display device according to an example embodiment.

Detailed Description

Fig. 1 is a block diagram illustrating a display apparatus and a display system 10 including the display apparatus according to an example embodiment.

The display system 10 according to an example embodiment may be mounted in an electronic device having an image display function. For example, the electronic devices may include smart phones, tablet Personal Computers (PCs), Portable Multimedia Players (PMPs), cameras, wearable devices, Televisions (TVs), Digital Video Disc (DVD) players, refrigerators, air conditioners, set-top boxes, robots, unmanned planes, various medical devices, navigation devices, Global Positioning System (GPS) receivers, in-vehicle devices, furniture, and various measuring instruments.

Referring to fig. 1, a display system 10 may include a display device 100 and a host processor 200, and the display device 100 may include a display driving circuit 110 (or referred to as a display driving Integrated Circuit (IC)) and a display panel 120.

The host processor 200 may generate image data IDT to be displayed by the display panel 120 and may transmit the image data IDT and a control command CMD to the display driving circuit 110. For example, the control command CMD may include setting information regarding, for example, brightness, gamma (gamma), frame, frequency, and/or operation mode of the display driving circuit 110. Although not shown, the host processor 200 may transmit a clock signal or a synchronization signal to the display driving circuit 110.

Host processor 200 may include a graphics processor. However, the inventive concept is not limited thereto, and the host processor 200 may be implemented as various kinds of processors such as a Central Processing Unit (CPU), a microprocessor, a multimedia processor, and an application processor. In an example embodiment, host processor 200 may be implemented with an IC or a system on a chip (SoC).

The display device 100 may display the image data IDT received from the host processor 200. In example embodiments, the display device 100 may be a device in which the display driving circuit 110 and the display panel 120 are implemented as one module. For example, the display driving circuit 110 may be mounted on a substrate of the display panel 120, or the display driving circuit 110 may be electrically connected to the display panel 120 through a connection member such as a Flexible Printed Circuit Board (FPCB).

The display panel 120 may be a display unit displaying a real image, and may include one of display devices such as an Organic Light Emitting Diode (OLED) display, a thin film transistor-liquid crystal display (TFT-LCD), a field emission display, and a Plasma Display Panel (PDP), which receives an electrically transmitted image signal to display a two-dimensional (2D) image. Hereinafter, in the inventive concept, it may be assumed that the display panel 120 is an OLED display panel in which a plurality of pixels each include an OLED. However, the inventive concept is not limited thereto, and the display panel 120 may be implemented as a different kind of flat display panel or flexible display panel.

The display driving circuit 110 may convert the image data IDT received from the host processor 200 into a plurality of analog signals (e.g., a plurality of data voltages) for driving the display panel 120 and may supply the plurality of analog signals to the display panel 120. Accordingly, the display panel 120 can display an image corresponding to the image data IDT.

The display driving circuit 110 according to example embodiments may include a voltage tracking circuit 300. The voltage tracking circuit 300 can perform pre-charging with a reference voltage in a transition period in which the reference voltage supplied to the display panel 120 varies by using a push-pull circuit and a voltage selection circuit, and thus can remove noise including crosstalk occurring at the time of display driving. In an example embodiment, the voltage tracking circuit 300 may generate a first control signal for precharging the input node, precharge the input node based on the first control signal, apply a second reference voltage to the input node, and generate the output voltage based on the second reference voltage in a transition period before the input node is applied with the second reference voltage after the first reference voltage is applied to the input node.

The display driving circuit 110 may include a reference voltage generator (115 of fig. 2) that converts a pixel value into a reference voltage (or a gray scale voltage) corresponding to a gray scale represented by the pixel value, and may apply the reference voltage corresponding to the pixel value to the pixels of the display panel 120. Accordingly, the pixel may output an optical signal based on the luminance corresponding to the pixel value. The reference voltage generator may generate a plurality of reference voltages.

The display driving circuit 110 according to the above example embodiment may reduce noise such as crosstalk by precharging with a reference voltage in the course of supplying the reference voltage to the display panel 120 using a push-pull circuit and a voltage selection circuit.

Fig. 2 is a block diagram illustrating the display driving circuit 110 and the display panel according to example embodiments.

Referring to fig. 2, the display driving circuit 110 may include an Interface (IF) circuit 111, a controller 112, a memory 113, a data driver 114 (or referred to as a source driver), a reference voltage generator 115, a scan driver 116 (or referred to as a gate driver), and a voltage tracking circuit 300. The display driver circuit 110 may also include other general-purpose elements (e.g., a voltage generator and a clock generator).

In an example embodiment, the interface circuit 111, the controller 112, the memory 113, the data driver 114, the reference voltage generator 115, the scan driver 116, and the voltage tracking circuit 300 may be integrated into one semiconductor chip. In some example embodiments, the interface circuit 111, the controller 112, the memory 113, the data driver 114, the reference voltage generator 115, and the voltage tracking circuit 300 may be provided in one semiconductor chip, and the scan driver 116 may be provided in the display panel (120 of fig. 1).

The interface circuit 111 may transmit signals or data to the host processor 200 or receive signals or data from the host processor 200. The interface circuit 111 may be implemented, for example, as a Mobile Industry Processor Interface (MIPI)

One of a serial interface of a Mobile Display Digital Interface (MDDI), a displayport, and an embedded displayport (eDP).

The memory 113 may store image data received from the host processor 200 in units of frames. The memory 113 may be referred to as a graphics Random Access Memory (RAM) or a frame buffer. The memory 113 may include volatile memory (e.g., Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM)) or non-volatile memory (e.g., Read Only Memory (ROM), flash memory, resistive random access memory (ReRAM), or Magnetic Random Access Memory (MRAM)). The image data received from the host processor 200 may be stored in the memory 113 before or after the controller 112 performs image processing on the image data. In an example embodiment, the display driving circuit 110 may not include the memory 113, and in this case, after the controller 112 performs image processing on the image data, the image data received from the host processor 200 may be transferred to the data driver 114.

The controller 112 may control the overall operation of the display driving circuit 110, and may control elements (e.g., the interface circuit 111, the memory 113, the data driver 114, the reference voltage generator 115, the scan driver 116, and the voltage tracking circuit 300) of the display driving circuit 110 so that image data received from the host 100 is displayed by the display panel 120.

In addition, the controller 112 may perform image processing for brightness change, size change, and format change on the received image data, or may generate new image data to be displayed by the display panel 120 based on the received image data. To this end, the controller 112 may include a plurality of intellectual property rights (IPs) for image processing.

The reference voltage generator 115 may generate a plurality of reference voltages (VG < n-1:0>) (referred to as gray scale voltages or gamma voltages) based on a desired (or predetermined) gamma curve, where n is an integer of 2 or more, and may supply the reference voltages (VG < n-1:0>) to the voltage tracking circuit 300. The reference voltage generator 115 may adjust the highest reference voltage and/or the lowest reference voltage based on the gamma setting value, and may adjust the gamma curve. In this case, the gamma curve may be a graph of the luminance of the light signal output from the pixels PX of the display panel 120 with respect to a plurality of gray levels. The voltage levels of the plurality of reference voltages (VG < n-1:0>) may be adjusted such that the light signal corresponding to the luminance based on a desired (or predetermined) gamma curve, or the gamma curve, may be adjusted by adjusting the voltage levels of the plurality of reference voltages (VG < n-1:0 >).

The voltage tracking circuit 300 may include a voltage selection circuit 310 and a precharge circuit 320 having a push-pull circuit structure. The voltage tracking circuit 300 may perform a precharge operation in a transition period in which the reference voltages supplied to the plurality of lines are varied based on the plurality of reference voltages (VG _ O < n-1:0>), and may supply the plurality of reference voltages (VG _ O < n-1:0>) to the data driver 114, thereby reducing crosstalk. The transition period may point to a period between a first time point at which the first reference voltage is applied to the input node and a second time point at which the second reference voltage is applied to the input node. The precharge operation will be described in detail with reference to fig. 7A and 7B.

The voltage tracking circuit 300 may be implemented in hardware or a combination of software (or firmware) and hardware. For example, the voltage tracking circuit 300 may be implemented in hardware logic, in various hardware logic such as an application specific ic (asic), a Field Programmable Gate Array (FPGA), or a Complex Programmable Logic Device (CPLD), or in firmware, software, or a combination of hardware and software driven in a processor such as a microcontroller unit (MCU) or a CPU.

The data driver 114 may convert the compensated image data CIDT received from the controller 112 into a plurality of image signals (e.g., a plurality of data voltages VD1 to VDm (where m is an integer of 2 or more), and may output the plurality of data voltages VD1 to VDm to the display panel 120 through the plurality of data lines DL.

The data driver 114 may receive the compensated image data CIDT in units of row data (e.g., in units of data corresponding to a plurality of pixels included in one horizontal row of the display panel 120). The data driver 114 may convert the line data received from the controller 112 into a plurality of data voltages VD1 to VDm based on a plurality of reference voltages (VG _ O < n-1:0>) received from the voltage tracking circuit 300.

The scan driver 116 may be connected to the plurality of scan lines SL of the display panel 120, and may sequentially drive the plurality of scan lines SL of the display panel 120. The scan driver 116 may provide a plurality of scan signals S1 through Sn (where n is a positive integer of 2 or more) having an active level (e.g., a logic high level) to the plurality of scan lines SL based on the control of the controller 112. Accordingly, a plurality of scan lines SL may be sequentially selected, and a plurality of data voltages VD1 to VDm may be applied to a plurality of pixels PX connected to the selected scan lines SL.

The display panel 120 may include a plurality of data lines DL, a plurality of scan lines SL, and a plurality of pixels PX disposed between lines (at intersections of the plurality of data lines DL and the plurality of scan lines SL). The plurality of pixels PX may be each connected to a corresponding scan line SL and a corresponding data line DL.

The plurality of pixels PX may each output light having a desired (or, predetermined) color, and may be disposed adjacent to the same or adjacent lines. In addition, two or more pixels PX (e.g., a red (R) pixel, a blue (B) pixel, and a green (G) pixel) for outputting a plurality of lights of different colors may configure one unit pixel. In this case, two or more pixels PX configuring a unit pixel may be referred to as sub-pixels. The display panel 120 may have an RGB structure in which a red pixel, a blue pixel, and a green pixel configure one unit pixel. However, the inventive concept is not limited thereto, and the display panel 120 may have an RGBW structure in which the unit pixel further includes a white (W) pixel for enhancing luminance. In some example embodiments, the unit pixels of the display panel 120 may be configured by a combination of different color pixels other than red, blue, and green pixels.

The display panel 120 may include an OLED display panel in which a plurality of pixels PX each include an OLED. However, the inventive concept is not limited thereto, and the display panel 120 may be implemented as a different kind of flat display panel or flexible display panel.

Fig. 3 is a block diagram schematically illustrating the display driving circuit 110 according to an example embodiment.

Referring to fig. 3, the display driving circuit 110 may include a controller 112, a data driver 114, a display panel 350, a reference voltage generator 115, and a voltage tracking circuit 300.

The reference voltage generator 115 may generate a plurality of reference voltages (VG < n-1:0>) (where n is an integer of 2 or more) based on a desired (or predetermined) gamma curve, and may provide the reference voltages (VG < n-1:0>) to the voltage tracking circuit 300.

The voltage tracking circuit 300 may perform a precharge operation in a transition period of a reference voltage variation in order to reduce crosstalk in supplying the reference voltage (VG < n-1:0 >).

The controller 112 may perform a preprocessing process on the input pixel data to generate pixel data PD (e.g., CIDT), and may provide the pixel data PD to the data driver 114.

The data driver 114 may include a digital-to-analog converter (DAC)41 and an output buffer 42. In fig. 3, the data driver 114 is shown to include a driving circuit of one channel having the DAC 41 and the output buffer 42, but this is for convenience of description, and the data driver 114 may include a driving circuit of a plurality of channels.

Fig. 4 is a block diagram schematically illustrating a voltage tracking circuit 300 according to an example embodiment.

The voltage tracking circuit 300 may include a voltage selection circuit 310 and a precharge circuit 320. The voltage selection circuit 310 may generate a control signal for performing a precharge operation on the input nodes of the output buffers (e.g., the first output buffer CH1 and the second output buffer CH2 in fig. 7A) in a transition period in which the reference voltage applied to the output buffers varies. Voltage selection circuit 310 may generate a control voltage that is very close to the target reference voltage and may precharge the input nodes, thereby further enhancing performance associated with crosstalk.

The precharge circuit 320 may precharge the input node with a target reference voltage to be supplied to the output node through the push-pull circuit structure, and may limit the precharge to a certain range. The push-pull circuit may stop operating when a gate-source voltage of the push-pull circuit is less than a threshold voltage. For example, when a voltage level higher than the sum of the first control signal and the threshold voltage is supplied to the first node of the precharge circuit 320, the second transistor may be turned on. The first transistor may be turned on when a voltage level lower than a difference between the first control signal and the threshold voltage is supplied to the first node of the precharge circuit 320. Accordingly, the precharge circuit 320 may limit the voltage of the first node to a range from a difference between the first control signal and the threshold voltage to a sum of the first control signal and the threshold voltage. In this case, the first transistor may include an NMOS transistor, and the second transistor may include a PMOS transistor.

Fig. 5 is a circuit diagram illustrating the reference voltage generator 115 according to an example embodiment.

It can be assumed that reference voltage generator 115 generates 256 reference voltages GV <255:0 >.

Referring to fig. 5, the reference voltage generator 115 may include a gamma tap voltage generating unit (gamma tap voltage generating unit)51 and a reference voltage output unit 52. The gamma tap voltage generating unit 51 may generate a plurality of gamma tap voltages Vgmt0 to Vgmt5 corresponding to a plurality of gamma taps used to determine a gamma curve, and may generate a plurality of reference voltages (e.g., zeroth to 255 th reference voltages) VG <0> to VG <255> corresponding to a plurality of gray levels based on the plurality of gamma tap voltages Vgmt0 to Vgmt 5. In this case, the plurality of gamma taps may represent a specific gray level (e.g., a plurality of reference gray levels) for determining a gamma curve among the plurality of gray levels, and the plurality of gamma tap voltages Vgmt0 to Vgmt5 may correspond to some of a plurality of reference voltages (e.g., zeroth to 255 th reference voltages) VG <0> to VG <255 >.

The gamma tab voltage generating unit 51 may include a plurality of resistor strings RS1 to RS5 and a plurality of selectors SLT1 to SLT 6. The number of resistor strings and the number of selectors may vary. Although not shown, the gamma tap voltage generating unit 51 may further include a plurality of buffers (not shown) (e.g., current buffers) for stably maintaining voltage levels of the plurality of gamma tap voltages Vgmt0 to Vgmt5 output from the plurality of selectors (e.g., first to sixth selectors) SLT1 to SLT 6.

The plurality of resistor strings (e.g., first to fifth resistor strings) RS1 to RS5 may each generate a plurality of voltages by dividing a voltage applied to both ends thereof using a resistor included therein, and may output the plurality of voltages. Each of the plurality of selectors SLT1 to SLT6 may select one voltage from among voltages output from the resistor string based on a corresponding selection signal among a plurality of selection signals (e.g., the first to sixth selection signals CS1 to CS6), and may output the selected voltage. Accordingly, a plurality of gamma tap voltages (e.g., the zeroth to fifth gamma tap voltages) Vgmt0 to Vgmt5 may be generated.

For example, the first resistor string RS1 may divide the reference high voltage VSH and the reference low voltage VSL to generate a plurality of voltages, and in response to the first selection signal CS1, the first selector SLT1 may select one voltage from among the plurality of voltages received from the first resistor string RS1, and may output the selected voltage as the zeroth gamma tap voltage Vgmt 0. The zeroth gamma tap voltage Vgmt0 may be the lowest reference voltage (e.g., the zeroth reference gamma voltage VG <0 >). In response to the second selection signal CS2, the second selector SLT2 may select one voltage from among a plurality of voltages received from the first resistor string RS1, and may output the selected voltage as the fifth gamma tap voltage Vgmt 5. The fifth gamma tap voltage Vgmt5 may be the highest reference voltage (e.g., the zeroth reference gamma voltage VG <0 >).

The third to sixth resistor strings RS3 to RS6 may divide the fifth gamma tap voltage Vgmt5 and a different gamma tap voltage (e.g., one of the zero to third gamma tap voltages Vgmt0 to Vgmt 3) by using resistors included therein, select one voltage from among a plurality of voltages generated based on the divided voltages in response to corresponding selection signals (e.g., the third to sixth selection signals CS3 to CS6), and output the selected voltage as one of the first to fourth gamma tap voltages Vgmt1 to Vgmt 4. The first to fourth gamma terminal voltages Vgmt1 to Vgmt4 may be one of the intermediate reference voltages. For example, the first gamma tap voltage Vgmt1 may be output as the seventh reference voltage VG <7>, the second gamma tap voltage Vgmt2 may be output as the 75 th reference voltage VG <75>, the third gamma tap voltage Vgmt3 may be output as the 151 th reference voltage VG <151>, and the fourth gamma tap voltage Vgmt4 may be output as the 203 th reference voltage VG <203 >.

Accordingly, the gamma tap voltage generating unit 51 may generate a plurality of gamma tap voltages Vgmt0 to Vgmt5 corresponding to a plurality of gamma taps (e.g., a plurality of reference gray levels). At this time, the first to sixth selection signals CS1 to CS6 may vary, and the voltage level of each of the plurality of gamma tap voltages Vgmt0 to Vgmt5 may be adjusted. Accordingly, the highest reference voltage and the lowest reference voltage may be adjusted based on the first selection signal CS1 and the second selection signal CS2, and a plurality of intermediate reference voltages used to determine gamma curves may be adjusted based on the third selection signal CS3 to the sixth selection signal CS 6.

The reference voltage output unit 52 may include a resistor string (e.g., a sixth resistor string) RS6, and a plurality of gamma tap voltages (e.g., a zero gamma tap voltage to a fifth gamma tap voltage) Vgmt0 to Vgmt5 are applied to the resistor string RS 6. The sixth resistor string RS6 may divide a plurality of gamma tap voltages (e.g., a zeroth to fifth gamma tap voltage) Vgmt0 to Vgmt5 respectively applied to the plurality of nodes ND1 to ND6 to generate a plurality of reference voltages (e.g., a zeroth to 255 th reference voltage) VG <0> to VG <255 >.

In this case, the resistance values of the resistors provided between two adjacent nodes among the plurality of nodes ND1 to ND6 may be the same, or all the resistance values of the resistors included in the sixth resistor string RS6 may be the same. Therefore, the voltage difference between the reference voltages between two adjacent gamma tap voltages may be the same. For example, a voltage difference between pairs of adjacent reference voltages among the zeroth through seventh reference voltages VG <0> through VG <7> may be the same as a voltage difference between the pairs of adjacent reference voltages. In addition, a voltage difference between pairs of adjacent reference voltages among the seventh to 75 th reference voltages VG <7> to VG <75> may be the same as a voltage difference between the pairs of adjacent reference voltages. As described above, the voltage increase amount between the reference voltages may be the same for the adjacent gamma terminal voltages.

FIG. 6 is a block diagram schematically illustrating a voltage tracking circuit according to an example embodiment.

Referring to fig. 2 and 6, the reference voltage generator 115 may generate a plurality of reference voltages (VG < n-1:0) (e.g., n reference voltages, where n is an integer of 2 or more) and may provide the reference voltages (VG < n-1:0>) to the voltage tracking circuit 300. The generated plurality of reference voltages may be provided to a plurality of channels (e.g., a plurality of output buffers).

For convenience of description, it may be assumed that the reference voltage generator 115 generates two reference voltages (e.g., a first reference voltage vref1 and a second reference voltage vref2) and supplies the two reference voltages to two channels (e.g., a first output buffer CH1 and a second output buffer CH2) included in the display panel.

For example, referring to fig. 6, the reference voltage generator 115 may supply a first reference voltage vref1 and a second reference voltage vref2 to a first output buffer CH1 and a second output buffer CH2, both of which are included in the display panel. The first switch S1 may select a reference voltage to be supplied to the first output buffer CH1, and the fourth switch S4 may select a reference voltage to be supplied to the second output buffer CH 2.

The precharge circuit 320 may include a first push-pull structure connected to the first node a and a second push-pull structure connected to the second node B.

The first push-pull structure may include a first transistor M1 performing a pull-up operation and a second transistor M2 performing a pull-down operation. The first reference voltage vref1 or the second reference voltage vref2 may be applied to a gate terminal of each of the first transistor M1 and the second transistor M2. The precharge circuit 320 may perform precharge on the first node a connected to the source terminal of each of the first and second transistors M1 and M2. The first output buffer CH1 may generate an output voltage Y _ OUT1 supplied to the display panel based on the reference voltage supplied to the first node a.

The second push-pull structure may include a third transistor M3 performing a pull-up operation and a fourth transistor M4 performing a pull-down operation. The first reference voltage vref1 or the second reference voltage vref2 may be applied to a gate terminal of each of the third transistor M3 and the fourth transistor M4. The precharge circuit 320 may perform a precharge on the second node B connected to the source terminal of each of the third transistor M3 and the fourth transistor M4. The second output buffer CH2 may generate an output voltage Y _ OUT2 supplied to the display panel based on the reference voltage supplied to the second node B.

The precharge circuit 320 may precharge the first node a or the second node B with a target reference voltage to be supplied to the output node through the push-pull circuit structure. The push-pull circuit may stop operating when a gate-source voltage of the push-pull circuit is less than a threshold voltage. For example, when a voltage level higher than the sum of the first reference voltage vref1 and the threshold voltage vth2 of the second transistor M2 is supplied to the first node a, the second transistor M2 may be turned on. When a voltage level lower than a difference between the first reference voltage vref1 and the threshold voltage vth1 of the first transistor M1 is supplied to the first node a, the first transistor M1 may be turned on. In the following description, it may be assumed that the threshold voltage vth1 of the first transistor M1 is the same as the threshold voltage vth2 of the second transistor M2, but example embodiments are not limited thereto. Accordingly, the precharge circuit 320 may limit the voltage of the first node a to a range from the difference between the first reference voltage vref1 and the threshold voltage to the sum of the first reference signal vref1 and the threshold voltage.

When a voltage level higher than the sum of the first reference voltage vref1 and the threshold voltage is supplied to the second node B, the fourth transistor M4 may be turned on. When a voltage level lower than the difference between the first reference voltage vref1 and the threshold voltage is supplied to the second node B, the third transistor M3 may be turned on. Accordingly, the precharge circuit 320 can limit the voltage of the second node B to a range from the difference between the first reference voltage vref1 and the threshold voltage to the sum of the first reference signal vref1 and the threshold voltage.

Fig. 7A is a circuit diagram illustrating a voltage tracking circuit according to an example embodiment, and fig. 7B is a graph for describing an operation signal of fig. 7A.

Referring to fig. 2 and 7A, the reference voltage generator 115 may generate a plurality of reference voltages (VG < n-1:0) (e.g., n reference voltages, where n is an integer of 2 or more) and may supply the reference voltages (VG < n-1:0>) to a plurality of channels through a plurality of output buffers.

For convenience of description, it may be assumed that the reference voltage generator 115 generates two reference voltages (e.g., a first reference voltage vref1 and a second reference voltage vref2) and supplies the first reference voltage vref1 and the second reference voltage vref2 to two channels (e.g., a first output buffer CH1 and a second output buffer CH2) included in the display panel.

For example, referring to fig. 7A, the reference voltage generator 115 may supply a first reference voltage vref1 and a second reference voltage vref2 to a first output buffer CH1 and a second output buffer CH2, both of which are included in the display panel. The first switch S1 may select a reference voltage to be supplied to the first output buffer CH1, and the fourth switch S4 may select a reference voltage to be supplied to the second output buffer CH 2. The reference voltage generator 115 may supply the voltage selection circuit 310 with the reference voltage vref [2:1] and the control signal ctrl, both generated by the precharge operation.

The voltage selection circuit 310 may generate a first control signal vctrl1 for a precharge operation before supplying the reference voltage to the first output buffer CH1 based on the reference voltage Vref [2:1] and the control signal ctrl, both of which are received accordingly. The precharge circuit 320 may apply the first control signal vctrl1 to the gate terminal of each of the first transistor M1 and the second transistor M2. The precharge circuit 320 may perform precharge on the first node a connected to the source terminal of each of the first and second transistors M1 and M2. The first output buffer CH1 may generate an output voltage Y _ OUT1 supplied to the display panel based on the reference voltage supplied to the first node a.

The voltage selection circuit 310 may generate the second control signal vctrl2 for the precharge operation before supplying the reference voltage to the second output buffer CH2 based on the reference voltage Vref [2:1] and the control signal ctrl, both of which are received accordingly. The precharge circuit 320 may apply the second control signal vctrl2 to the gate terminal of each of the third transistor M3 and the fourth transistor M4. The precharge circuit 320 may perform precharge on the second node B connected to the source terminal of each of the third transistor M3 and the fourth transistor M4. The second output buffer CH2 may generate an output voltage Y _ OUT2 supplied to the display panel based on the reference voltage supplied to the second node B.

Voltage selection circuit 310 may generate a control voltage that is very close to the target reference voltage and may apply the control voltage to perform a precharge operation, thereby further enhancing performance associated with crosstalk. The precharge circuit 320 may precharge the input nodes of the output buffers (e.g., the first output buffer CH1 and the second output buffer CH2 in fig. 7A) with a target reference voltage to be supplied to the output nodes through the push-pull circuit structure, and may limit the precharge to a certain range. The push-pull circuit may stop operating when the gate-source voltage of the push-pull circuit is less than the threshold voltage. For example, when a voltage level higher than the sum of the first control signal vctrl1 and the threshold voltage is supplied to the first node a of the precharge circuit 320, the second transistor M2 may be turned on. The first transistor M1 may be turned on when a voltage level lower than a difference between the first control signal vctrl1 and the threshold voltage is supplied to the first node a of the precharge circuit 320. Therefore, the precharge circuit 320 may limit the voltage of the first node a to a range from a difference between the first control signal vctrl1 and the threshold voltage to a sum of the first control signal vctrl1 and the threshold voltage.

When a voltage level higher than the sum of the second control signal vctrl2 and the threshold voltage is supplied to the second node B of the precharge circuit 320, the fourth transistor M4 may be turned on. The third transistor M3 may be turned on when a voltage level lower than a difference between the second control signal vctrl2 and the threshold voltage is supplied to the second node B of the precharge circuit 320. Accordingly, the precharge circuit 320 may limit the voltage of the second node B to a range from a difference between the second control signal vctrl2 and the threshold voltage to a sum of the second control signal vctrl2 and the threshold voltage.

Fig. 7B illustrates signals and control signals applied to the switch when the same reference voltage is supplied to the first output buffer CH1 and a changed reference voltage is applied to the second output buffer CH 2.

The display driving circuit 110 may connect the first switch S1 to the first reference voltage vref1 to supply the first reference voltage vref1 to the first node a in the first period P1. At this time, the display driving circuit 110 may maintain the second switch S2 in an on state and may maintain the third switch S3 in an off state. The voltage selection circuit 310 may generate a first control signal vctrl1 based on a first reference voltage vref1, and may provide the first control signal vctrl1 to the precharge circuit 320 to precharge the first node a.

The display driving circuit 110 may connect the fourth switch S4 to the first reference voltage vref1 to supply the first reference voltage vref1 to the second node B in the first period P1. At this time, the display driving circuit 110 may maintain the fifth switch S5 in an on state, and may maintain the sixth switch S6 in an off state. The voltage selection circuit 310 may generate the second control signal vctrl2 based on the second reference voltage vref2, and may provide the second control signal vctrl2 to the precharge circuit 320 so as to precharge the second node B.

The display driving circuit 110 may change the first node a and the second node B to a high impedance (high Z) state in which the connection with the first output buffer CH1 and the second output buffer CH2 is blocked in the second period P2, which is a transition period for changing the reference voltage. That is, when the second switch S2 and the fifth switch S5 are all turned off, the first switch S1 and the fourth switch S4 may float and may change to a high impedance (high Z) state. The display driving circuit 110 may change the first switch S1 and the fourth switch S4 to a high impedance state or a floating state in the second period P2.

The display driving circuit 110 may change the second switch S2 to an off state and may change the third switch S3 to an on state. The display driving circuit 110 may equally hold the first control signal vctrl1 generated based on the first reference voltage vref1 in the second period P2.

The display driving circuit 110 may change the fifth switch S5 to an off state and may change the sixth switch S6 to an on state. The display drive circuit 110 may change the second control signal vctrl2 generated based on the first reference voltage vref1 to a signal generated based on the second reference voltage vref2 in the second period P2. In this case, even when noise occurs due to the change of the second control signal vctrl2 in the display drive circuit 110, the first switch S1, the second switch S2, the fourth switch S4, and the fifth switch S5 can be in an off state, and thus the noise does not adversely affect other channels, thereby reducing crosstalk.

Accordingly, the display driving circuit 110 may supply the changed reference voltage to the display panel in the third period P3 without noise.

Fig. 8A is a circuit diagram illustrating the reference voltage generator 115 and the buffer circuit according to an example embodiment, and fig. 8B is a graph for describing an operation signal of fig. 8A.

Referring to fig. 2 and 8A, the reference voltage generator 115 may generate a plurality of reference voltages (VG < n-1:0) (e.g., n reference voltages, where n is an integer of 2 or more) and may provide the reference voltages (VG < n-1:0 >). The generated plurality of reference voltages (VG < n-1:0) may be provided to a buffer circuit including a plurality of channels CH1 and CH 2.

For convenience of description, it may be assumed that the reference voltage generator 115 generates two reference voltages (e.g., a first reference voltage vref1 and a second reference voltage vref2) and supplies the first reference voltage vref1 and the second reference voltage vref2 to two channels (e.g., a first output buffer CH1 and a second output buffer CH2) included in the display panel.

For example, referring to fig. 8A, the display driving circuit 110 may supply the first and second reference voltages vref1 and vref2 generated by the reference voltage generator 115 to the first and second output buffers CH1 and CH2, which are both included in the display panel. The display driving circuit 110 may select a reference voltage to be supplied to the first output buffer CH1 through the first switch S1, and may select a reference voltage to be supplied to the second output buffer CH2 through the fourth switch S4.

Fig. 8B illustrates signals and control signals applied to the switch when the same reference voltage is supplied to the first output buffer CH1 and a changed reference voltage is applied to the second output buffer CH 2.

The display driving circuit 110 may connect the first switch S1 to the first reference voltage vref1 to supply the first reference voltage vref1 to the first node a in the first period P1. At this time, the display driving circuit 110 may maintain the second switch S2 in an on state and may maintain the third switch S3 in an off state.

The display driving circuit 110 may connect the fourth switch S4 to the second reference voltage vref2 to supply the second reference voltage vref2 to the second node B in the first period P1. At this time, the display driving circuit 110 may maintain the fifth switch S5 in an on state and may maintain the sixth switch S6 in an off state.

In the second period P2, which is a transition period for changing the reference voltage, the display driving circuit 110 may maintain the first switch S1 in the current state, and may change the fourth switch S4 from the second reference voltage vref2 to the first reference voltage vref 1.

In the second period P2, the display driving circuit 110 may change the second switch S2 to an off state and may change the third switch S3 to an on state. In the second period P2, the display driving circuit 110 may change the fifth switch S5 to an off state and may change the sixth switch S6 to an on state.

At this time, when noise occurs in the second node B due to the change of the fourth switch S4 in the display driving circuit 110, the first switch S1 may be connected to the fourth switch S4, and accordingly, the noise may adversely affect the first node a, thereby causing crosstalk. Accordingly, in the third period P3, the display driving circuit 110 may supply the reference voltage, in which noise occurs, to the display panel.

Fig. 9 is a circuit diagram illustrating a voltage selection circuit 310 according to an example embodiment.

The voltage selection circuit 310 may generate a control signal for a precharge operation before supplying the reference voltage to the output buffer based on the reference voltage Vref and the control signal ctrl, both of which are received thus. The voltage selection circuit 310 may generate a control voltage that is very close to the target reference voltage and may apply the control voltage to perform a precharge operation, thereby further enhancing performance associated with crosstalk.

For example, the voltage selection circuit 310 may select the high gray code circuit HGC by using a multiplexer when the received reference voltage vref changes from a high voltage level to a low voltage level, and the voltage selection circuit 310 may select the low gray code circuit LGC when the received reference voltage vref changes from a low voltage level to a high voltage level.

When the received reference voltage vref changes from a high voltage level to a low voltage level, the voltage selection circuit 310 may output a control signal vctrl that is higher than the received reference voltage vref by a threshold voltage level. When the received reference voltage vref changes from a low voltage level to a high voltage level, the voltage selection circuit 310 may output a control signal vctrl that is lower than the received reference voltage vref by a threshold voltage level. Accordingly, the voltage selection circuit 310 may output the control signal vctrl within the threshold voltage range based on the target reference voltage vref to precharge the voltage node.

Fig. 10 is a flowchart illustrating an operation method of the display driving circuit 110 according to an example embodiment.

Referring to fig. 2, 7A and 10, in operation S110, the display driving circuit 110 may generate a first control signal for precharging the input node of a buffer circuit (e.g., the first output buffer CH1 and/or the second output buffer CH2 in fig. 7A) in a transition period after the input node is applied with a first reference voltage and before the input node is applied with a second reference voltage. The display driving circuit 110 may further include a voltage selection circuit 310, and the voltage selection circuit 310 generates a first control signal corresponding to the reference voltage. When the first reference voltage is higher than the second reference voltage, the voltage selection circuit 310 may generate the first control signal by adding a desired (or predetermined) threshold voltage to the second reference voltage, and when the first reference voltage is lower than the second reference voltage, the voltage selection circuit 310 may generate the first control signal by subtracting the desired (or predetermined) threshold voltage from the second reference voltage. In this case, the second reference voltage may be different from the first reference voltage.

In operation S120, the precharge circuit 320 included in the display driving circuit 110 may precharge the input node based on the first control signal. The display driving circuit 110 may further include a switching circuit configured to provide one of the plurality of reference voltages to the input node based on the second control signal. The controller may generate the second control signal such that the input node floats in the transition period.

The precharge circuit 320 may apply a first control signal to a gate terminal of each of the first NMOS transistor and the first PMOS transistor to precharge the input node through a source terminal of the first NMOS transistor and a source terminal of the first PMOS transistor. The precharge circuit 320 may precharge the input node within a desired (or, predetermined) range of the second reference voltage.

The display driving circuit 110 may use a signal generated by the voltage selection circuit 310 as the first control signal or the second control signal, and may use a reference voltage generated by the reference voltage generator 115 as the first control signal or the second control signal.

In operation S130, the display driving circuit 110 may apply a second reference voltage to the input node. The input node may be in a state of being precharged based on the first control signal, and thus, a difference from the second reference voltage may be less than or equal to a threshold voltage, thereby improving performance related to noise because a variation in voltage is not large.

In operation S140, the display driving circuit 110 may generate an output voltage based on the second reference voltage. The display driving circuit 110 may include a data driver that receives a plurality of reference voltages from the reference voltage generator 115 and outputs a data voltage corresponding to a reference voltage selected by the controller from among the plurality of reference voltages to the display panel.

Fig. 11 shows an implementation example of a display device 1000 according to an example embodiment. The display apparatus 1000 of fig. 1 may be an apparatus including a small display panel 1200, and may be applied to, for example, mobile devices such as a smartphone and a tablet Personal Computer (PC).

Referring to fig. 11, the display apparatus 1000 may include a display driving circuit 1100 and a display panel 1200. The display driver circuit 1100 may be configured with one or more ICs, and may be mounted on a circuit film such as a Tape Carrier Package (TCP), a Chip On Film (COF), or a Flexible Printed Circuit (FPC), attached to the display panel 1200 in a Tape Automated Bonding (TAB) type, or provided in a non-display area (e.g., an area where an image is not displayed) of the display panel 1200 in a Chip On Glass (COG) type.

The display driving circuit 1100 may include a data driver 1110 and a control logic 1120, and may further include a gate driver. In example embodiments, the gate driver may be provided in the display panel 1200.

Fig. 12 shows an implementation example of a display device 2000 according to an example embodiment. The display device 2000 of fig. 12 may be a device including a moderately large display panel 2200, and may be applied to, for example, a Television (TV), a monitor, or the like.

Referring to fig. 12, the display device 2000 may include a data driver 2110, a timing controller (e.g., TCON IC)2120, a gate driver 2130, and a display panel 2200.

The timing controller 2120 may be configured with one or more ICs or modules. The timing controller 2120 may communicate with the plurality of data driving ICs DDIC and the plurality of gate driving ICs GDIC through a desired (or predetermined) interface.

The timing controller 2120 may generate a control signal controlling a driving timing of each of the plurality of data driving IC DDICs and the plurality of gate driving IC GDICs, and may supply the control signal to the plurality of data driving IC DDICs and the plurality of gate driving IC GDICs.

The data driver 2110 may include a plurality of data driving IC DDICs, and the plurality of data driving IC DDICs may be mounted on a circuit film such as TCP, COF, or FPC, attached to the display panel 2200 in a TAB type, or provided in a non-display region of the display panel 2200 in a COG type.

The gate driver 2130 may include a plurality of gate driver ICs GDICs, and the plurality of gate driver ICs GDICs may be mounted on a circuit film or an FPC, attached to the display panel 2200 in a TAB type, or mounted in a non-display region of the display panel 2200 in a COG type. In some example embodiments, the gate driver 2130 may be disposed directly on the lower substrate of the display panel 2200 in a gate driver in panel (GIP) type. The gate driver 2130 may be disposed in a non-display region of the display panel 2200 other than the pixel array in which the plurality of subpixels PX are disposed, and may be formed through the same Thin Film Transistor (TFT) process as the subpixels PX.

Any of the functional blocks shown in the figures and described above may be implemented in processing circuitry, such as hardware including logic circuitry, a hardware/software combination, such as a processor executing software, or a combination thereof. For example, the processing circuitry may more particularly include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and so forth. While the present inventive concept has been particularly shown and described with reference to certain exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims (20)

1. A display driver circuit, the display driver circuit comprising:

a reference voltage generator configured to generate a plurality of reference voltages;

a buffer circuit configured to generate an output voltage based on a reference voltage applied to an input node of the buffer circuit among the reference voltages; and

a precharge circuit configured to precharge the input node based on a first control signal in a transition period, the transition period being a period between a first time point at which a first reference voltage is applied to the input node and a second time point at which a second reference voltage is applied to the input node.

2. The display drive circuit according to claim 1, further comprising:

a switching circuit configured to provide one of the plurality of reference voltages to the input node based on a second control signal and to float the input node in the transition period.

3. The display drive circuit according to claim 1, wherein the second reference voltage is different from the first reference voltage.

4. The display driver circuit of claim 1, wherein the pre-charge circuit is further configured to apply the first control signal to a gate terminal of each of a first NMOS transistor and a first PMOS transistor to pre-charge the input node through a source terminal of the first NMOS transistor and a source terminal of the first PMOS transistor.

5. The display driving circuit according to claim 1, wherein the precharge circuit is further configured to precharge the input node within a certain range determined based on the second reference voltage.

6. The display drive circuit according to claim 1, further comprising:

a voltage selection circuit configured to generate the first control signal based on the reference voltage applied to an input node of the buffer circuit.

7. The display driver circuit of claim 6, wherein the voltage selection circuit is further configured to:

generating the first control signal having a first voltage level obtained by adding a threshold voltage to the second reference voltage when the first reference voltage is higher than the second reference voltage, an

Generating the first control signal having a second voltage level obtained by subtracting the threshold voltage from the second reference voltage when the first reference voltage is lower than the second reference voltage.

8. The display drive circuit according to claim 1, further comprising:

a data driver configured to receive the plurality of reference voltages from the reference voltage generator and output a data voltage corresponding to a specific reference voltage selected by the controller of the display driving circuit from among the plurality of reference voltages to a display panel.

9. A method of operating a display driver circuit, the method of operation comprising:

generating a first control signal precharging an input node in a transition period, the transition period being a period between a first time point of applying a first reference voltage to the input node and a second time point of applying a second reference voltage to the input node;

precharging the input node based on the first control signal;

applying the second reference voltage to the input node; and

an output voltage is generated based on the second reference voltage.

10. The method of operation of claim 9, further comprising:

floating the input node by a switching circuit during the pre-charging,

wherein the switching circuit is configured to provide one of a plurality of reference voltages to the input node based on a second control signal.

11. The operating method of claim 9, wherein the second reference voltage is different from the first reference voltage.

12. The operating method of claim 9, wherein the precharging comprises applying the first control signal to a gate terminal of each of a first NMOS transistor and a first PMOS transistor to precharge the input node through a source terminal of the first NMOS transistor and a source terminal of the first PMOS transistor.

13. The operating method of claim 9, wherein the precharging includes precharging the input node within a range determined based on the second reference voltage.

14. The method of operation of claim 9, wherein the generating the first control signal comprises:

generating the first control signal by adding a threshold voltage to the second reference voltage when the first reference voltage is higher than the second reference voltage; and

generating the first control signal by subtracting the threshold voltage from the second reference voltage when the first reference voltage is lower than the second reference voltage.

15. The method of operation of claim 9, further comprising:

outputting a data voltage corresponding to the generated output voltage to a display panel.

16. A display device, the display device comprising:

a display panel; and

a display driving circuit configured to drive the display panel such that the display panel displays an image, wherein,

the display driving circuit includes a display driver circuit including,

a reference voltage generator configured to generate a plurality of reference voltages,

a buffer circuit configured to generate an output voltage with a reference voltage applied to an input node of the buffer circuit among the reference voltages,

a precharge circuit configured to precharge the input node based on a first control signal, an

A controller configured to generate the first control signal for precharging the input node in a transition period, which is a period between a first time point of applying a first reference voltage to the input node and a second time point of applying a second reference voltage to the input node.

17. The display device according to claim 16, further comprising:

a switching circuit configured to provide one of the plurality of reference voltages to the input node based on a second control signal,

wherein the controller is further configured to generate the second control signal for floating the input node in the transition period.

18. The display device according to claim 16, wherein the second reference voltage is different from the first reference voltage.

19. The display device of claim 16, wherein the precharge circuit is further configured to apply the first control signal to a gate terminal of each of a first NMOS transistor and a first PMOS transistor to precharge the input node within a range by a source terminal of the first NMOS transistor and a source terminal of the first PMOS transistor.

20. The display device according to claim 16, further comprising:

a voltage selection circuit configured to generate the first control signal corresponding to the reference voltage applied to the input node of the buffer circuit, wherein the voltage selection circuit is configured to,

generating the first control signal by adding a threshold voltage to the second reference voltage when the first reference voltage is higher than the second reference voltage, an

Generating the first control signal by subtracting the threshold voltage from the second reference voltage when the first reference voltage is lower than the second reference voltage.

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