KR101023722B1 - Driving Circuit of Shift Registers - Google Patents

Abstract

The present invention detects an output voltage of a predetermined output terminal of a shift register built in a liquid crystal panel, and when a plurality of output voltages are generated in one frame, the system automatically feeds back the supplied supply voltage to the shift register again. A drive circuit for a resistor, comprising: a power supply for supplying a reference voltage, a timing controller for outputting various control signals for driving a shift register, and a voltage signal output from a predetermined output terminal of the shift register; A voltage automatic compensator for determining the number of gate on voltages generated therein and a number of the reference voltage and the gate on voltage in response to the control signal and adjusting the gate on voltage according to the number of gate on voltages To apply a predetermined driving voltage and a clock signal to the shift register. It characterized by yirueojim a controller.

Shift Registers, Voltage Auto Compensation, Level Shifter, Drive Voltage

Description

Driving Circuit of Shift Registers

1 is a view illustrating a connection relationship between a liquid crystal panel and a driving unit of a general liquid crystal display;

2 is a view showing a liquid crystal display device with a built-in gate driver;

3 is a block diagram illustrating a driving circuit of a general liquid crystal display.

4 is a block diagram showing a driving unit of the liquid crystal display including the driving circuit of the shift register of the present invention;

5 is a block diagram showing a shift register applied to the driving circuit of the shift register of the present invention;

6 is a timing diagram illustrating a gate voltage signal generated at each output terminal of FIG. 5.

7 is a block diagram illustrating an automatic voltage compensator of a shift register.

8 is a block diagram illustrating a driving unit of a liquid crystal display including a driving circuit of a shift register according to another exemplary embodiment of the present invention.

Description of the Related Art [0002]

100: liquid crystal panel 110: active area

120: shift register 130: drive unit

131: power supply unit 132: gamma reference voltage unit                 

133: timing controller 134: data driver

135: voltage control unit 136: first level shifter

137: second level shifter 151: error detection

152: Up-Counter 200: Automatic voltage compensation unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and in particular, detects an output voltage of a predetermined output terminal of a shift register built in a liquid crystal panel, and automatically feeds back an upwardly supplied supply voltage when a plurality of output voltages are generated in one frame. The driving circuit of the shift register is supplied to the shift register again.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed a variety of monitors such as television and computer to receive and display broadcast signals.

In order to use such a liquid crystal display as a general screen display device in various parts, it is a matter of how high quality images such as high definition, high brightness and large area can be realized while maintaining the characteristics of light weight, thinness and low power consumption. Can be.

A general liquid crystal display device may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates bonded to each other with a predetermined space; It consists of a liquid crystal layer injected between the said 1st, 2nd glass substrate.

Here, the first glass substrate (TFT array substrate) has a plurality of gate lines arranged in one direction at regular intervals, a plurality of data lines arranged at regular intervals in a direction perpendicular to the gate lines, A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing a gate line and a data line, and a plurality of thin film transistors switched by signals of the gate line to transfer the signal of the data line to each pixel electrode. Is formed.

In the second glass substrate (color filter substrate), a black matrix layer for blocking light in portions other than the pixel region, an R, G, B color filter layer for expressing color colors, and a common image for implementing an image An electrode is formed.

The driving principle of the general liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal by optical anisotropy, thereby representing image information.

Currently, an active matrix LCD, in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner, is attracting the most attention due to its excellent resolution and ability to implement video.

Hereinafter, a driving circuit and a driving circuit thereof of a conventional liquid crystal display will be described with reference to the accompanying drawings.

1 is a diagram illustrating a connection relationship between a liquid crystal panel and a driver of a general liquid crystal display.

As shown in FIG. 1, a liquid crystal panel 10 of a general liquid crystal display device includes a lower substrate 1 having a TFT array including a plurality of gate lines and data lines, and an upper substrate 2 having a color filter array opposite thereto. It includes a liquid crystal layer (not shown) filled between the substrate (1, 2).

The liquid crystal panel 100 includes a gate drive IC 5 for applying a driving signal to the gate line, a gate printed circuit board 3 for controlling the gate drive IC 5, and a data line. A source drive IC 6 for applying a drive signal, a source PCB 4 for controlling the source drive IC 6, the gate drive IC 5, and a source drive IC 6 are respectively connected to a gate PCB ( 3), The drive part which consists of Tape Carrier Package (TCP) films 18a and 18b which connects to the source PCB 4 is connected.

The timing controller for applying various control signals to the gate PCB 3 and the source PCB 4 is not shown in the driver.

In recent years, efforts have been made to embed drive ICs in liquid crystal panels to reduce costs and simplify device configuration.

2 is a view showing a liquid crystal display device with a built-in gate driver.

As shown in FIG. 2, the gate driver embedded liquid crystal display includes a gate PCB and a gate drive IC formed in the liquid crystal panel.

The gate driver is a simple structure in which a shift register and an input / output buffer are provided at both sides of the shift register. The gate driver is easily integrated into a panel by a circuit that can be decorated with a simple element. On the other hand, the source driver side has many control signals and data signals received from a system (not shown) or a timing controller, and its internal circuit is complicated and is not generally incorporated in the liquid crystal panel 10. Accordingly, a source drive IC 16 for applying a drive signal to a data line, a source PCB 14 for controlling the source drive IC 16, and a source drive IC 16 and a source PCB 14 for connecting the source drive IC 16 to the data line are connected. A source driver is formed of a TCP film 17 and externally connected to the liquid crystal panel 10.

In some cases, when the semiconductor layer of the thin film transistor included in the lower substrate 1 is formed of polysilicon, the source driver may be embedded in the liquid crystal panel. This is because polysilicon has high electron mobility, and therefore, it is possible to expect rapid operation of a source driver configured in a liquid crystal panel.

However, most of the liquid crystal display devices that are currently mass-produced comprise a semiconductor layer made of amorphous silicon, and amorphous silicon is a material having low mobility, and as shown in FIG. 2, when a gate driver is embedded in a liquid crystal panel, As a result, compared to the external gate driver structure of FIG. 1, a delay of an output value or a change of a threshold voltage value of an element included in an internal circuit may be caused, and thus reliability may be degraded.

Hereinafter, the driving circuit of the liquid crystal display of FIG. 1 or 2 described above with reference to the drawings. The driving circuit of the liquid crystal display of FIGS. 1 and 2 has the same function as the gate driver is built in the liquid crystal panel.

3 is a block diagram illustrating a driving circuit of a general liquid crystal display.

As shown in FIG. 3, a general liquid crystal display device includes a liquid crystal panel 21 having a plurality of gate lines G and data lines D arranged in a direction perpendicular to each other, and having a pixel region in a matrix form. The driving circuit unit 22 supplies a driving signal and a data signal to the 21 and a backlight 28 providing a constant light source to the liquid crystal panel 21.

Here, the driving circuit unit 22 applies a gate driving pulse to the data driver 21b for inputting a data signal to each data line of the liquid crystal panel 21 and the gate lines G of the liquid crystal panel 21. Display data (R, G, B) input from the gate driver 21a to be applied, the drive system 27 of the liquid crystal module (LCM), and the vertical and horizontal synchronization signals Vsync and Hsync and the clock signal DCLK. A timing controller that receives a control signal and formats and outputs each display data, a clock, and a control signal at a timing suitable for each data driver 21b and the gate driver 21a of the liquid crystal panel 21 to reproduce a screen. 23, a power supply unit 24 for supplying a voltage required for the liquid crystal panel 21 and each part, and a digital data input from the data driver 21b by receiving power from the power supply unit 24; A gamma reference voltage unit 25 for supplying a reference voltage necessary for converting the data into analog data, and a constant voltage VDD and a gate used in the liquid crystal panel 21 by using the voltage output from the power supply unit 24. A DC / DC converter 26 for outputting a high voltage VGH, a gate low voltage VGL, a reference voltage Vref, a common voltage Vcom, and an inverter 29 for driving the backlight 28. It is provided.

The operation of the driving circuit of the general liquid crystal display device configured as described above is as follows.

That is, the timing controller 23 inputs control signals such as display data (R, G, B) and vertical and horizontal synchronization signals (Vsync, Hsync) and a clock signal (DCLK) input from the driving system 27 of the liquid crystal panel. Since the data driver 21b and the gate driver 21a of the liquid crystal panel 21 provide each display data, a clock, and a control signal at a timing suitable for reproducing the screen, the gate driver 21a provides the liquid crystal. An image input by applying a gate driving pulse to each gate line G of the panel 21 and in synchronization with the data driver 21b by inputting a data signal to each data line D of the liquid crystal panel 21. Display the signal.

At this time, the backlight 28 provides a backlight having a constant brightness regardless of the brightness of the input video signal.

The driving circuit of the conventional liquid crystal display device as described above has the following problems.

Most liquid crystal display devices that are currently mass-produced have a semiconductor layer made of amorphous silicon, which is a material having low mobility, and may have a problem in that the speed of the driver may be delayed when the driver is embedded in a panel. In addition, there is a voltage drop phenomenon of the device provided in the driver along with the speed delay, which has a weakness in reliability compared to the model in which all of the drivers are configured as an external type of the liquid crystal panel.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and detects the output voltage of a predetermined output terminal of a shift register embedded in a liquid crystal panel, and automatically supplies upwards when the number of output voltages in one frame is plural. It is an object of the present invention to provide a driving circuit of a shift register that feeds back a voltage and supplies the voltage to a shift register.

The driving circuit of the shift register of the present invention for achieving the above object is a power supply for supplying a reference voltage, a timing controller for outputting various control signals for driving the shift register, and at a predetermined output terminal of the shift register A voltage automatic compensator for monitoring the output voltage signal and determining the number of gate on voltages generated in one frame and receiving the reference voltage and the number of gate on voltages in response to the control signal, And a voltage controller configured to apply a driving voltage and a clock signal adjusted to the number of gate-on voltages to the shift register.

The shift register has a plurality of output stages.

The shift register is built in the liquid crystal panel.

The voltage automatic compensator is configured inside the timing controller.

The automatic voltage compensator includes a detector configured to determine that the voltage signal output from the predetermined output terminal of the shift register is a gate on signal, and an up counter for counting the number of times the gate on signal occurs within one frame.

The sensing unit and the up counter operate in response to the vertical sync signal (Vsync) signal.

When the number of times the gate-on signal occurs in one frame is two or more times, the voltage controller outputs an automatically raised voltage value.

A first level shifter for converting a voltage level of a control signal applied from the timing controller to the shift register to a shift register application level, and a voltage level generated at a predetermined output terminal of the shift register to an application level to the timing controller It further comprises a second level shifter.                     

In addition, the shift register driving circuit of the present invention for achieving the same object is a shift register driving circuit for controlling a shift register having a plurality of output terminals in the liquid crystal panel, the power supply for supplying various reference voltages to the liquid crystal panel A timing controller for outputting various control signals for driving the shift register, a first level shifter for level shifting a control signal generated from the timing controller to a voltage level applied to the shift register, and A second level shifter for level shifting a voltage signal output from a predetermined output terminal to a voltage level applied to the timing controller, and a sensing unit and the gate determining that the voltage signal output from the predetermined output terminal of the shift register is a gate-on signal. ON signal An up counter for counting the number of times occurring in one frame, and a driving voltage signal that is automatically supplied in response to the number of counts in the up counter in response to a reference voltage from the power supply in response to a control signal applied from the timing controller; And a voltage controller for feeding back a clock signal to the shift register.

The sensing unit and the up counter are configured inside the timing controller.

Hereinafter, the shift register driving circuit of the liquid crystal display of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram illustrating a driving unit of a liquid crystal display including a driving circuit of a shift register of the present invention.

As shown in FIG. 4, the liquid crystal display including the drive circuit of the shift register of the present invention incorporates a shift register 120 having a plurality of output terminals into the liquid crystal panel 100. Here, the liquid crystal panel 100 is defined by being divided into an active region 110 in which an actual thin film transistor array is formed to display and a non-display region around the liquid crystal panel 100. The shift register 120 is built in one side of the non-display area. The shift register 120 functions as a gate driver and may further include a buffer unit in each of the internal input / output terminals.

The driving circuit unit for driving the liquid crystal panel includes a power supply unit 131 for supplying various reference voltages required, a data driver 134 for driving data lines in the liquid crystal panel 100, and a gamma reference voltage for the data driver. A gamma reference voltage unit 132 providing a timing controller, a timing controller 133 for outputting various control signals for driving the shift register 120 and the data driver 134, and the shift from the timing controller 133. The voltage automatic compensator 200 monitors a voltage signal output from a predetermined output terminal of the register 120 and determines the number of gate on voltages generated within one frame, and the reference in response to the control signal. Receives a voltage and the number of the gate-on voltage, and applies a driving voltage adjusted to the number of the gate-on voltage to the shift register It comprises a voltage control unit 135 to.

Here, between the timing controller 133 and the shift register 120, a voltage level (TTL level: 0 V to 3.3 V or 0 to 5 V) of a control signal applied from the timing controller 133 to the shift register 120. A first level shifter 136 is formed to convert the shift register 120 into an application level of the shift register 120, that is, the clock signals CK and / CK of about 0 to 20V and the start signal, and the voltage automatic compensation is performed. Between the unit 200 and the timing controller 133, a high voltage level (0 to 20 V or 0 to 25 V) generated at a predetermined output terminal of the shift register 120 is applied to the timing controller 133 to a TTL level. A second level shifter 137 for converting is further formed.

In this case, when the number of times the gate on signal generated by the voltage automatic compensator 200 is generated in one frame is two or more times, the voltage is displayed as an error state and the voltage controller automatically outputs the voltage value. At this time, the reference for counting the number of times the gate-on signal occurs in one frame is applied because the vertical synchronization signal (Vsync) is applied every frame (frame), so that it is applied as a signal to operate.

The number of gate lines included in the liquid crystal panel is provided based on the vertical resolution of the display device.

Although a predetermined output terminal of the shift register is illustrated as a portion corresponding to the last gate line in the drawing, an output terminal corresponding to an arbitrary gate line may be selected without being limited thereto.

5 is a block diagram illustrating a shift register applied to a driving circuit of a shift register according to the present invention, and FIG. 6 is a timing diagram illustrating gate voltage signals generated at each output terminal of FIG. 5.

As shown in FIG. 5, the shift register of the present invention is composed of n stages SR1 to SRN connected to the front end and each output terminal g1 to gN, respectively. ), And are driven using the driving voltage signals VDD and VSS and the clock signals CK and / CK.

A start signal start is input to the first stage SR1, and the second to nth stages SR2 to SRN are output signals G1 to Gn-1 of the previous stage and two clock signals CK, / CK) sequentially selects the gate lines connected to each stage.

As shown in FIG. 6, each stage of the shift register is sequentially outputted with a square output voltage signal and applied to corresponding gate lines.

When the shift register of the present invention is normally driven, the gate-on voltage is output once per frame by delaying the start signal start by one clock (1H), but when an error occurs, one frame Two or more gate-on voltages may be output within.

There may be various causes of an error, but it is mainly caused by a change in the threshold voltage Vth of a device configured in a shift register. In particular, a start signal (start) supplied to the shift register and a stress situation in which the driving voltage signal (VDD) is applied at a high voltage are a major factor causing the change of the threshold voltage.

When the clock signals CK and / CK and the driving voltage VDD are set as low as possible, the stress decreases and the speed at which the threshold voltage Vth changes can be reduced, but in this case, the voltage margin is small, There is a problem in that the shift register cannot be extended and driven as a whole. Therefore, in order to extend the lifetime, the clock signals CK and / CK and the driving voltage VDD are conventionally applied with a larger margin than the voltage values required for driving the panel.

The shift register driving circuit of the present invention reduces the stress situation by applying only the minimum voltage required for driving in an initial state, detects the output voltage at a predetermined output terminal of the shift register, and then automatically applies an upwardly adjusted voltage to the required voltage. Having a margin and applying only the minimum voltage required for driving, it is possible to reduce the stress that may occur in the shift resistor.

The driving circuit of the shift register of the present invention initially sets the clock signal CK, / CK and driving voltage VDD signal levels to a minimum voltage at which the panel operates, and then detects a predetermined output terminal of the shift register. The output voltage value is monitored every frame, and when a plurality of gate-on signals of the output stage are generated, the driving voltage and the clock signal level applied to the shift register are increased by a predetermined step corresponding to the number of output voltage values. It is applied to the shift register again.

7 is a block diagram illustrating an automatic voltage compensator of a shift register.

As shown in FIG. 7, the automatic voltage compensator 200 determines that the voltage signal output from the predetermined output terminal of the shift register is a gate on signal and the number of times that the gate on signal occurs within one frame. It includes an up counter 152 to count. Here, the detector 151 and the up counter 152 operate in response to the vertical sync signal Vsync signal.                     

The detector 151 converts a signal of a predetermined output terminal of the shift register to a logic level through the converter 150 to determine the number of gate-on signals generated at the predetermined output terminal.

The converter 150 includes a resistor R and a transistor in series between a constant voltage VCC terminal, a ground terminal, and the transistor supplies a gate signal to a predetermined output terminal (n-th gate line Gn). The output terminal) is applied to the gate terminal, the source terminal is grounded, and the drain terminal is connected to the sensing unit 151.

The converter 150 outputs a low voltage level when a gate-on voltage is generated at a predetermined output terminal of the shift register, and outputs a high level when the gate-on voltage is not generated.

The detector 151 detects when a low voltage level is output from the converter 150, and performs up counting on the up counter 152 in synchronization with the low voltage level.

When the low voltage level occurs once in one frame, it is determined that the operation is normal. When the low voltage level occurs twice or more times, an error is fed back to the voltage controller 135 as an error.

In the normal operation, the voltage controller 135 applies the normal clock signals CK and / CK to the first level shifter 136, and applies the normal driving voltage signal VDD to the shift register 120. When an error occurs, the clock signal and the driving voltage which are automatically adjusted, respectively, are applied to the first level shifter 136 and the shift register.

In the drawing, the sensing unit 151 and the up counter 152 blocked by one box 160 may be built in the timing controller 133.

Hereinafter, another embodiment in which the sensing unit and the up counter are configured in the timing controller will be described with reference to the accompanying drawings.

8 is a block diagram illustrating a driving unit of a liquid crystal display including a driving circuit of a shift register according to another exemplary embodiment of the present invention.

As shown in FIG. 8, the driving circuit of the shift register according to another exemplary embodiment has the same function as the configuration except that the voltage automatic compensator 200 is embedded in the timing controller 133. Give the same sign.

The driving circuit of the shift register according to another exemplary embodiment of the present invention includes a power supply unit 131 for supplying various reference voltages to the liquid crystal panel 100, and a data driver 134 for driving data lines in the liquid crystal panel 100. ), A gamma reference voltage unit 132 for providing a gamma reference voltage to the data driver, a timing controller 133 for outputting various control signals for driving the shift register 120 and the data driver 134; And a first level shifter 136 for level shifting a control signal generated from the timing controller 133 to a voltage level applied to the shift register 120 and a predetermined output terminal of the shift register 120. A second level shifter 137 for level shifting a voltage signal to a voltage level applied to the timing controller 133, and embedded in the timing controller 133; A voltage automatic compensator 200 which determines that the voltage signal output from the predetermined output terminal of the shift register 120 is a gate-on signal, and counts the number of times the gate-on signal occurs in one frame, and the timing controller ( The shift register 120 receives a reference voltage from the power supply unit 131 in response to a control signal applied from 133 and automatically increases a driving voltage signal corresponding to the number of times of counting by the voltage automatic compensation unit 200. It includes a voltage control unit 135 to feed back to apply.

Here, the voltage automatic compensator 200 counts the detection unit 151 for determining that the voltage signal output from the predetermined output terminal of the shift register is a gate on signal and the number of times the gate on signal occurs within one frame. An up counter 152 is included and configured. Here, the detector 151 and the up counter 152 operate in response to the vertical sync signal Vsync signal.

Here, the driving voltage VDD and the clock signals CK and / CK applied to the shift register 120 for the first time are the minimum voltages required for driving the panel, and the voltage automatic compensator 200 performs the gate-on signal two or more times. Is detected, and when the up counting number is generated two or more times, the voltage controller 135 determines that the error state is an error state, and automatically increases the clock signals CK and / CK and the driving voltage VDD, respectively, which are automatically increased. Applied to the level shifter 136 and the shift register 120.

The power supply unit 131, the gamma reference voltage unit 132, the timing controller 133, the source driver 134, the voltage controller 135, and the first and second level shifters 136 and 137 are all one. By configuring the IC, the liquid crystal display device can be further simplified.

 The driving circuit of the shift register of the liquid crystal display of the present invention as described above has the following effects.

Conventionally, when a shift register is built in a liquid crystal panel, a DC voltage having a fixed value is simply applied as a driving voltage and a clock signal. However, the present invention provides a gate-on voltage generated at a predetermined output terminal of the shift register within one frame. It detects a signal and outputs a normal voltage or an adjusted voltage corresponding to the number. Therefore, by applying a minimum voltage at which the panel operates normally in a range that the reference power supply allows the supply voltage applied to the shift register, it is possible to maximize the life by minimizing the stress of the internal shift resistor.

In addition, the driving voltage and the like are not set to a fixed DC voltage value, and when an error occurs, an upward value is applied to compensate for this, so that an error situation can be appropriately dealt with, thereby improving reliability.

Claims (10)

A power supply unit supplying a reference voltage; A timing controller for outputting various control signals for driving the shift register; A voltage automatic compensator for monitoring a voltage signal output from a predetermined output terminal of the shift register and determining a number of gate on voltages generated in one frame; And A shift register configured to receive a number of the reference voltage and the gate on voltage in response to the control signal, and apply a driving voltage and a clock signal adjusted to the number of gate on voltages to the shift register; In the driving circuit of The voltage automatic compensation unit A detector configured to determine that a voltage signal output from a predetermined output terminal of the shift register is a gate on signal; And And an up counter that counts the number of times the gate-on signal occurs within one frame. The method of claim 1, And the shift register has a plurality of output stages. The method of claim 1, And the shift register is built in a liquid crystal panel. The method of claim 1, And the voltage automatic compensator is configured inside the timing controller. delete The method of claim 1, And the sensing unit and the up counter operate in response to a vertical synchronization signal (Vsync) signal. The method of claim 1, And outputting a voltage value automatically raised by the voltage controller when the number of times the gate-on signal occurs in one frame is two or more times. The method of claim 1, A first level shifter for converting a voltage level of a control signal applied from the timing controller to the shift register to a shift register application level, and a voltage level generated at a predetermined output terminal of the shift register to an application level to the timing controller The shift register driving circuit further comprises a second level shifter. A shift register driving circuit for controlling a shift register having a plurality of output terminals in a liquid crystal panel, A power supply unit supplying various reference voltages to the liquid crystal panel; A timing controller configured to output various control signals for driving the shift register; A first level shifter for level shifting a control signal generated from the timing controller to a voltage level applied to the shift register; A second level shifter for level shifting a voltage signal output from a predetermined output terminal of the shift register to a voltage level applied to a timing controller; A detector configured to determine that a voltage signal output from a predetermined output terminal of the shift register is a gate on signal; And An up counter that counts the number of times the gate on signal occurs within one frame; A voltage that receives a reference voltage from the power supply in response to a control signal applied from the timing controller and feeds back a driving voltage signal and a clock signal that are automatically raised in response to the number of counts in the up counter to the shift register. A shift register driving circuit comprising a control unit. The method of claim 9, And the sensing unit and the up counter are configured inside the timing controller.

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