CN114974105B - Low-power-consumption pixel scanning circuit and method applied to micro display chip - Google Patents
Low-power-consumption pixel scanning circuit and method applied to micro display chip Download PDFInfo
- Publication number
- CN114974105B CN114974105B CN202210901960.XA CN202210901960A CN114974105B CN 114974105 B CN114974105 B CN 114974105B CN 202210901960 A CN202210901960 A CN 202210901960A CN 114974105 B CN114974105 B CN 114974105B
- Authority
- CN
- China
- Prior art keywords
- clock
- clock control
- shift register
- control units
- units
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a low-power-consumption pixel scanning circuit and a method applied to a micro-display chip, comprising a plurality of shift register units, wherein the output of each shift register unit is connected to a scanning link in an active matrix panel; the system also comprises a plurality of groups of clock control units, wherein each group of clock control units comprises a clock gate and an enabling circuit; the multiple groups of clock control units are sequentially arranged along the data transmission direction of the scanning link; the clock gating is sequentially connected to the clock input ends of the plurality of shift register units in the data transmission direction of the scanning link; the enabling circuit generates an enabling signal for controlling the clock gating to be turned on or off according to the first control signal and the plurality of second control signals; inputting the pixel clock to all clock gates; the pixel clock is input to the shift register while the enable circuit controls the clock gating to be on.
Description
Technical Field
The invention relates to the technical field of LED display, in particular to a low-power-consumption pixel scanning circuit and method applied to a micro display chip.
Background
The Micro-LED display technology is a display technology which takes self-luminous micrometer-scale LEDs as light-emitting pixel units and assembles the light-emitting pixel units on a driving panel to form a high-density LED array. Due to the characteristics of small size, high integration level, self-luminescence and the like of the Micro-LED chip, compared with an LCD and an OLED, the Micro-LED chip has the advantages of higher brightness, resolution, contrast, energy consumption, service life, response speed, thermal stability and the like in the aspect of display.
As shown in fig. 1, in a schematic structural diagram of a pixel scanning circuit of a Micro-LED Micro-display chip in the prior art, a row-column scanning circuit of the Micro-display panel employs a plurality of shift register units, an output Q of a previous stage of each shift register unit is connected to an input D of a next stage, and all shift register units sequentially output data under the action of a pixel clock. The output Q of the shift register of each stage is also connected to the corresponding scan chain, i.e. all scan columns or rows are turned on in sequence.
As can be seen from fig. 2, when the start signal is asserted, the next clock first stage register output is asserted, i.e., the first stage corresponding scan chain is opened. And then the output of the register at the second stage of the clock is valid, namely the scan chain corresponding to the second stage is opened. This in turn opens the scan chain. Therefore, the clock end of the shift register of each stage is turned, and if m clock cycles are used in a cycle of scanning once, each stage of the register only has one clock cycle, and clocks in other clock cycles are invalid and turned. In the actual working state, the time for opening the register output by each column or each row is far shorter than the non-working time, but the clock is always turned over, so that a plurality of invalid clock turns over, and the power consumption of the micro display chip is increased.
Therefore, the pixel scanning circuit of the micro display chip for controlling the invalid clock turnover so as to save power consumption is lacked in the prior art.
Disclosure of Invention
The technical purpose of the present invention is to provide a new scan circuit capable of controlling invalid clock inversion in a pixel scan circuit in a micro display chip, so as to reduce power consumption waste of the micro display chip caused by the invalid clock inversion.
In view of the above technical objects, the present invention provides a low power consumption pixel scan circuit applied to a micro display chip, the pixel scan circuit including a plurality of shift register units, an output of each of the shift register units being connected to a scan link in an active matrix panel;
the pixel scanning circuit also comprises a plurality of groups of clock control units, and each group of clock control units comprises a clock gate and an enabling circuit;
the multiple groups of clock control units are sequentially arranged along the data transmission direction of the scanning link; the clock gating is sequentially connected to the clock input ends of the plurality of shift register units in the data transmission direction of the scanning link;
the enabling circuit generates an enabling signal for controlling the clock gating to be turned on or off according to the first control signal and the plurality of second control signals; the first control signal is an initial data signal or a data signal output by the last shift register unit controlled by the previous group of clock control units; the plurality of second control signals are output signals of each shift register unit in the current group of clock control units;
inputting the pixel clock to all clock gates; the pixel clock is input to the shift register while the enable circuit controls the clock gating to be on.
In one embodiment, the enable circuit generates the enable signal according to a logical or operation of the first control signal and the plurality of second control signals.
In one embodiment, the plurality of sets of clock control units comprise a plurality of sets of first level clock control units and a plurality of sets of second level clock control units; each group of the first-stage clock control unit and the second-stage clock control unit comprises a clock gate and an enabling circuit; the multiple groups of first-stage clock control units and the multiple groups of second-stage clock control units are sequentially arranged along the data transmission direction of the scanning link;
the clock gating of the multiple groups of first-stage clock control units is sequentially connected to the clock input ends of the multiple shift register units in the data transmission direction of the scanning link;
the clock gating in the multiple groups of second-level clock control units is sequentially connected to the clock input ends of the clock gating in the multiple first-level clock control units in the data transmission direction of the scanning link.
In one embodiment, the enabling circuit in the first-stage clock control unit performs logical or operation according to the first control signal and a plurality of second control signals to generate an enabling signal for controlling whether clock gating in the first-stage clock control unit inputs the pixel clock into the shift register unit;
the enabling circuit in the second-level clock control unit performs logical OR operation according to a third control signal and a plurality of fourth control signals to generate a clock-gated enabling signal for controlling whether the clock gating in the second-level clock control unit inputs the pixel clock into the first-level clock control unit;
the third control signal is a starting data signal or a data signal output by an enabling circuit in the last group of first-stage clock control units in the previous group of second-stage clock control units;
the plurality of fourth control signals are output signals of the enabling circuit in each first-stage clock control unit in the current second-stage clock control unit.
In one embodiment, the shift register is comprised of D flip-flop logic elements.
Another aspect of the present invention is to provide a low power consumption pixel scanning method applied to a micro display chip, the method including:
arranging a plurality of shift register units in a pixel scanning circuit, and enabling the output of each shift register unit to be connected to one scanning link in an active matrix panel;
a plurality of groups of clock control units are arranged in the pixel scanning circuit, and each group of clock control units comprises a clock gate and an enabling circuit;
the multiple groups of clock control units are sequentially arranged along the data transmission direction of the scanning link; the clock gating is sequentially connected to the clock input ends of the plurality of shift register units in the data transmission direction of the scanning link;
the enabling circuit generates an enabling signal for controlling the clock gating to be turned on or off according to the first control signal and the plurality of second control signals; the first control signal is an initial data signal or a data signal output by the last shift register unit controlled by the previous group of clock control units; the plurality of second control signals are output signals of each shift register unit in the current group of clock control units;
inputting the pixel clock to all clock gates; the pixel clock is input to the shift register while the enable circuit controls the clock gating to be on.
In one embodiment, the enable circuit generates the enable signal according to a logical or operation of the first control signal and the plurality of second control signals.
In one embodiment, the plurality of sets of clock control units are arranged to include a plurality of sets of first level clock control units and a plurality of sets of second level clock control units; each group of the first-level clock control unit and the second-level clock control unit comprises a clock gate and an enabling circuit; the multiple groups of first-stage clock control units and the multiple groups of second-stage clock control units are sequentially arranged along the data transmission direction of the scanning link;
the clock gating of the multiple groups of first-stage clock control units is sequentially connected to the clock input ends of the multiple shift register units in the data transmission direction of the scanning link;
the clock gating in the multiple groups of second-level clock control units is sequentially connected to the clock input ends of the clock gating in the multiple first-level clock control units in the data transmission direction of the scanning link.
In one embodiment, the enabling circuit in the first-stage clock control unit performs logical or operation according to the first control signal and a plurality of second control signals to generate an enabling signal for controlling whether clock gating in the first-stage clock control unit inputs the pixel clock into the shift register unit;
the enabling circuit in the second-level clock control unit performs logical OR operation according to a third control signal and a plurality of fourth control signals to generate a clock-gated enabling signal for controlling whether the clock gating in the second-level clock control unit inputs the pixel clock into the first-level clock control unit;
the third control signal is a starting data signal or a data signal output by an enabling circuit in the last group of first-stage clock control units in the previous group of second-stage clock control units;
the plurality of fourth control signals are output signals of the enabling circuit in each first-stage clock control unit in the current second-stage clock control unit.
In one embodiment, the shift register is constructed from D flip-flop logic elements.
One or more embodiments of the present invention may have the following advantages over the prior art:
the invention utilizes the multi-level clock gating to control the pixel clock input to the shift register, thereby reducing the invalid turnover of the pixel clock in the shift register and reducing the power consumption waste of the micro display chip caused by the invalid clock turnover.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a pixel scan circuit of a micro display chip in the prior art;
FIG. 2 is a clock cycle diagram of a pixel scan circuit in the prior art;
FIG. 3 is a schematic diagram of a pixel scan circuit according to a first embodiment of the present invention;
FIG. 4 is a clock cycle diagram of a pixel scan circuit according to a first embodiment of the present invention;
fig. 5 is a schematic structural diagram of a pixel scanning circuit according to a second embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Example 1
As shown in fig. 3, the pixel scanning circuit of the present embodiment includes a plurality of shift register units, and the shift register units are formed by D flip-flop logic elements. The output of each shift register cell is connected to one scan chain in the active matrix panel. The pixel scanning circuit also comprises a plurality of groups of clock control units, each group of clock control units comprises a clock gate 1 and an enabling circuit 2, and the clock gate 1 in each group of clock control units is connected with the clock input ends of the plurality of shift register units and is used for controlling the clock input of the plurality of shift registers. The enabling circuit 2 in each group of clock control units is connected to the clock gate 1 in the group, and the enabling circuit 2 controls whether the clock gate 1 in the group outputs the pixel clock to the plurality of shift register units connected to the clock gate 1 in the group by generating the clock gate enabling signal. The clock gate 1 in each group of clock control units is sequentially connected to a plurality of shift register units in the data transmission direction of the scan link, and in this embodiment, the clock gate 1 in each group of clock control units is sequentially connected to three adjacent shift register units, that is, the clock gate 1 in the first group of clock control units in the data transmission direction along the scan link is connected to the clock input ends of the 1 st, 2 nd, and 3 rd shift register units in the data transmission direction of the scan link; clock gating 1 in the second group of clock control units along the data transmission direction of the scanning link is connected with the clock input end of the 4 th, 5 th and 6 th shift register units along the data transmission direction of the scanning link; a clock gate 1 in the third group of clock control units along the data transmission direction of the scanning link is connected with the clock input ends of 7 th, 8 th and 9 th shift register units along the data transmission direction of the scanning link; and so on.
The enable circuit 2 performs a logical or operation according to the first control signal and the plurality of second control signals to generate an enable signal for controlling whether the clock gate 1 inputs the pixel clock to the shift register unit. The first control signal is a start data signal or a data signal output by the last shift register unit controlled by the previous group of clock control units. The plurality of second control signals are output signals of each shift register unit in the current clock control unit.
The pixel clock is input to all clock gates 1, and the waiting enabling circuit 2 inputs the pixel clock to the shift register when the clock gates are controlled to be opened.
As shown in fig. 4, in the clock cycle diagram of the pixel scan circuit of this embodiment, for the nth group of clock control units, when the last shift register controlled by the (n-1) th group of clock control units outputs a data signal, the clock gating enable signal generated by the enable circuit 2 in the nth group of clock control units is converted to a high level. At the same time, clock gating 1 starts to output the pixel clock to the shift register unit controlled by the nth group of clock control units. When the output signal of the last shift register unit controlled by the nth group of clock control units changes to low level, the clock gate 1 of the nth group of clock control units stops outputting the pixel clock. The pixel clock starts to be output by the clock gate 1 of the (n + 1) th group of clock control units. Therefore, the pixel clock input into the shift register unit is sequentially input into the shift register unit under the regulation of the plurality of groups of clock control units, so that the power consumption waste caused by continuous turnover of the clock when the pixel clock is continuously input into all the shift register units is avoided.
Example 2
As shown in fig. 5, the pixel scanning circuit of the present embodiment includes a plurality of shift register units, and the shift registers are formed by D flip-flop logic elements. The output of each shift register cell is connected to one scan chain in the active matrix panel. The pixel scanning circuit also comprises a plurality of groups of first-stage clock control units and a plurality of groups of second-stage clock control units. Each set of the first-stage clock control unit and the second-stage clock control unit comprises a clock gate 1 and an enabling circuit 2.
The clock gating 1 in each group of first-stage clock control units is connected to the clock input ends of the shift register units and is used for controlling the clock input of the shift registers. The enabling circuit 2 in each group of first-stage clock control units is connected to the clock gating 1 in the group, and the enabling circuit 2 controls whether the clock gating 1 in the group outputs the pixel clock to the plurality of shift register units connected to the clock gating 1 in the group by generating a clock gating enabling signal. The clock gating 1 in each group of first-stage clock control units is sequentially connected to a plurality of shift register units in the data transmission direction of the scan link, and in this embodiment, the clock gating 1 in each group of first-stage clock control units is sequentially connected to three adjacent shift register units, that is, the clock gating 1 in the first group of clock control units in the first-stage clock control units in the data transmission direction of the scan link is connected to the clock input ends of the 1 st, 2 nd, and 3 rd shift register units in the data transmission direction of the scan link; clock gating 1 in a second group of clock control units in the first-stage clock control unit in the data transmission direction of the scanning link is connected with the clock input end of the 4 th, 5 th and 6 th shift register units in the data transmission direction of the scanning link; clock gating 1 in a third group of clock control units in the first-stage clock control unit in the data transmission direction of the scanning link is connected with the clock input ends of 7 th, 8 th and 9 th shift register units in the data transmission direction of the scanning link; and so on.
And the enabling circuit 2 in the first-stage clock control unit performs logical OR operation according to the first control signal and a plurality of second control signals to generate an enabling signal for controlling whether the clock gate 1 inputs the pixel clock into the shift register unit. The first control signal is an initial data signal or a data signal output by a last shift register unit controlled by a previous group of clock control units in the first stage of clock control unit. The plurality of second control signals are output signals of each shift register unit in the current clock control unit.
The clock gating 1 in each group of second-level clock control units is connected to the clock input end of the clock gating 1 in the plurality of groups of first-level clock control units, and the clock gating 1 in each group of second-level clock control units is sequentially connected to the clock input end of the clock gating 1 in the plurality of first-level clock control units in the data transmission direction of the scanning link.
And the enabling circuit 2 in the second-level clock control unit performs logical OR operation according to the third control signal and a plurality of fourth control signals to generate an enabling signal of the clock gating 1 for controlling whether the clock gating 1 inputs the pixel clock into the first-level clock control unit. The third control signal is a start data signal, or a data signal output by the enable circuit 2 in the last group of first-stage clock control units in the previous group of second-stage clock control units. The plurality of fourth control signals are output signals of the enable circuit 2 in each first-stage clock control unit in the current second-stage clock control unit.
Therefore, the pixel clock input into the shift register unit is sequentially input into the shift register unit under the regulation of the multi-stage and multi-group clock control units, so that the power consumption waste caused by continuous turnover of the clock when the pixel clock is continuously input into all the shift register units is avoided.
The above description is only an embodiment of the present invention, and the protection scope of the present invention is not limited thereto, and any person skilled in the art should modify or replace the present invention within the technical specification of the present invention.
Claims (10)
1. A low-power consumption pixel scanning circuit applied to a micro display chip is characterized by comprising a plurality of shift register units, wherein the output of each shift register unit is connected to a scanning link in an active matrix panel;
the pixel scanning circuit also comprises a plurality of groups of clock control units, and each group of clock control units comprises a clock gate and an enabling circuit;
the multiple groups of clock control units are sequentially arranged along the data transmission direction of the scanning link; the clock gating is sequentially connected to the clock input ends of the plurality of shift register units in the data transmission direction of the scanning link;
the enabling circuit generates an enabling signal for controlling the clock gating to be turned on or off according to the first control signal and the plurality of second control signals; the first control signal is an initial data signal or a data signal output by the last shift register unit controlled by the previous group of clock control units; the plurality of second control signals are output signals of each shift register unit in the current group of clock control units;
inputting the pixel clock to all clock gates; the pixel clock is input to the shift register while the enable circuit controls the clock gating to be on.
2. The low power consumption pixel scanning circuit of claim 1, wherein the enable circuit generates the enable signal according to a logical or operation of the first control signal and a plurality of second control signals.
3. The pixel scanning circuit with low power consumption according to claim 1, wherein the plurality of groups of clock control units comprise a plurality of groups of first-stage clock control units and a plurality of groups of second-stage clock control units; each group of the first-stage clock control unit and the second-stage clock control unit comprises a clock gate and an enabling circuit; the multiple groups of first-stage clock control units and the multiple groups of second-stage clock control units are sequentially arranged along the data transmission direction of the scanning link;
the clock gating of the multiple groups of first-stage clock control units is sequentially connected to the clock input ends of the multiple shift register units in the data transmission direction of the scanning link;
the clock gating in the multiple groups of second-level clock control units is sequentially connected to the clock input ends of the clock gating in the multiple first-level clock control units in the data transmission direction of the scanning link.
4. The pixel scanning circuit with low power consumption according to claim 3, wherein the enable circuit in the first-stage clock control unit performs logical OR operation according to the first control signal and a plurality of second control signals to generate an enable signal for controlling whether the clock gating in the first-stage clock control unit inputs the pixel clock into the shift register unit;
the enabling circuit in the second-level clock control unit performs logical OR operation according to a third control signal and a plurality of fourth control signals to generate a clock-gated enabling signal for controlling whether the clock gating in the second-level clock control unit inputs the pixel clock into the first-level clock control unit;
the third control signal is a starting data signal or a data signal output by an enabling circuit in the last group of first-stage clock control units in the previous group of second-stage clock control units;
the plurality of fourth control signals are output signals of the enabling circuit in each first-stage clock control unit in the current second-stage clock control unit.
5. The low power pixel scanning circuit of claim 1, wherein the shift register is comprised of D flip-flop logic elements.
6. A low-power-consumption pixel scanning method applied to a micro display chip is characterized by comprising the following steps:
arranging a plurality of shift register units in a pixel scanning circuit, and enabling the output of each shift register unit to be connected to one scanning link in an active matrix panel;
a plurality of groups of clock control units are arranged in the pixel scanning circuit, and each group of clock control units comprises a clock gate and an enabling circuit;
the multiple groups of clock control units are sequentially arranged along the data transmission direction of the scanning link; the clock gating is sequentially connected to the clock input ends of the plurality of shift register units in the data transmission direction of the scanning link;
the enabling circuit generates an enabling signal for controlling the clock gating to be turned on or off according to the first control signal and the plurality of second control signals; the first control signal is an initial data signal or a data signal output by the last shift register unit controlled by the previous group of clock control units; the plurality of second control signals are output signals of each shift register unit in the current group of clock control units;
inputting the pixel clock to all clock gates; the pixel clock is input to the shift register while the enable circuit controls the clock gating to be on.
7. The low-power-consumption pixel scanning method according to claim 6, wherein the enable circuit generates the enable signal according to a logical OR operation of the first control signal and a plurality of second control signals.
8. The low-power-consumption pixel scanning method according to claim 6, wherein the plurality of groups of clock control units are arranged to include a plurality of groups of first-stage clock control units and a plurality of groups of second-stage clock control units; each group of the first-stage clock control unit and the second-stage clock control unit comprises a clock gate and an enabling circuit; the multiple groups of first-stage clock control units and the multiple groups of second-stage clock control units are sequentially arranged along the data transmission direction of the scanning link;
the clock gating of the multiple groups of first-stage clock control units is sequentially connected to the clock input ends of the multiple shift register units in the data transmission direction of the scanning link;
the clock gating in the multiple groups of second-level clock control units is sequentially connected to the clock input ends of the clock gating in the multiple first-level clock control units in the data transmission direction of the scanning link.
9. The pixel scanning method with low power consumption according to claim 8, wherein the enable circuit in the first-stage clock control unit performs logical or operation according to the first control signal and a plurality of second control signals to generate an enable signal for controlling whether the clock gating in the first-stage clock control unit inputs the pixel clock into the shift register unit;
the enabling circuit in the second-level clock control unit performs logical OR operation according to a third control signal and a plurality of fourth control signals to generate a clock-gated enabling signal for controlling whether the clock gating in the second-level clock control unit inputs the pixel clock into the first-level clock control unit;
the third control signal is a starting data signal or a data signal output by an enabling circuit in the last group of first-stage clock control units in the previous group of second-stage clock control units;
the plurality of fourth control signals are output signals of the enabling circuit in each first-stage clock control unit in the current second-stage clock control unit.
10. The low-power pixel scanning method according to claim 6, wherein the shift register is composed of D flip-flop logic elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210901960.XA CN114974105B (en) | 2022-07-29 | 2022-07-29 | Low-power-consumption pixel scanning circuit and method applied to micro display chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210901960.XA CN114974105B (en) | 2022-07-29 | 2022-07-29 | Low-power-consumption pixel scanning circuit and method applied to micro display chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114974105A CN114974105A (en) | 2022-08-30 |
| CN114974105B true CN114974105B (en) | 2022-09-30 |
Family
ID=82970032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210901960.XA Active CN114974105B (en) | 2022-07-29 | 2022-07-29 | Low-power-consumption pixel scanning circuit and method applied to micro display chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114974105B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108492791A (en) * | 2018-03-26 | 2018-09-04 | 京东方科技集团股份有限公司 | A kind of display driver circuit and its control method, display device |
| CN111261116A (en) * | 2020-04-02 | 2020-06-09 | 合肥京东方卓印科技有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN111312145A (en) * | 2020-03-03 | 2020-06-19 | 昆山国显光电有限公司 | Display and driving method thereof |
| CN112908275A (en) * | 2019-11-19 | 2021-06-04 | 夏普株式会社 | Data signal line driving circuit and liquid crystal display device having the same |
| CN114646861A (en) * | 2022-02-24 | 2022-06-21 | 西安电子科技大学 | Capturing mode for single fixed fault model in multi-clock-domain integrated circuit |
-
2022
- 2022-07-29 CN CN202210901960.XA patent/CN114974105B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108492791A (en) * | 2018-03-26 | 2018-09-04 | 京东方科技集团股份有限公司 | A kind of display driver circuit and its control method, display device |
| CN112908275A (en) * | 2019-11-19 | 2021-06-04 | 夏普株式会社 | Data signal line driving circuit and liquid crystal display device having the same |
| CN111312145A (en) * | 2020-03-03 | 2020-06-19 | 昆山国显光电有限公司 | Display and driving method thereof |
| CN111261116A (en) * | 2020-04-02 | 2020-06-09 | 合肥京东方卓印科技有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN114646861A (en) * | 2022-02-24 | 2022-06-21 | 西安电子科技大学 | Capturing mode for single fixed fault model in multi-clock-domain integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114974105A (en) | 2022-08-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100442342C (en) | Organic light emitting display and driving method thereof | |
| KR100762690B1 (en) | scan driving circuit and Organic Light Emitting Display Using the same | |
| US5295174A (en) | Shifting circuit and shift register | |
| CN106991975B (en) | A kind of pixel circuit and its driving method | |
| CN110910834A (en) | Source driver, display panel, control method of display panel and display device | |
| CN109817141A (en) | Source electrode drive circuit and display device including the source electrode drive circuit | |
| CN100514404C (en) | Electric charge sharing apparatus for display panel | |
| CN104464613B (en) | Light emitting diode driving system and control method | |
| US7948466B2 (en) | Circuit structure for dual resolution design | |
| CN109712564A (en) | Driving method, driving circuit and display device | |
| CN114974105B (en) | Low-power-consumption pixel scanning circuit and method applied to micro display chip | |
| CN100538813C (en) | Circuit structure for dual resolution design reaches display panel and the electronic installation of using it | |
| CN103813579B (en) | Light emitting diode driving circuit and driving system of light emitting diode | |
| CN103582221B (en) | Light emitting diode driving circuit, driving system and driving method thereof | |
| CN209118742U (en) | A kind of data transmission circuit and display device of low-power consumption | |
| CN102044208B (en) | Display device | |
| US7714827B2 (en) | Integrated circuit for scan driving | |
| CN107731147B (en) | Scan driver and method of driving the same | |
| CN214624392U (en) | OLED grid driving circuit, display panel driving device and display device | |
| CN102074196B (en) | Driving circuit of active matrix organic light emitting display and drive method | |
| JP3142319B2 (en) | Control circuit | |
| CN102074197B (en) | Driving method for active matrix organic light emitting display | |
| US8423725B1 (en) | Multithreading implementation for flops and register files | |
| CN101295970B (en) | Trigger and shifting register | |
| CN112735503B (en) | Shifting register, display panel, driving method and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |