CN209118742U - A kind of data transmission circuit and display device of low-power consumption - Google Patents
A kind of data transmission circuit and display device of low-power consumption Download PDFInfo
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- CN209118742U CN209118742U CN201822036476.7U CN201822036476U CN209118742U CN 209118742 U CN209118742 U CN 209118742U CN 201822036476 U CN201822036476 U CN 201822036476U CN 209118742 U CN209118742 U CN 209118742U
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Abstract
The utility model proposes a kind of data transmission circuit of low-power consumption and its display devices, the data transmission circuit includes clock grouping module, clock processing module and register module, by enabling clock signal, clock signal is grouped in clock grouping module, clock signal is grouped in clock grouping module, and the clock signal after grouping is sequentially turned in the clock processing module, reduce the power consumption of clock overturning consumption.Meanwhile under the control of clock signal after grouping, the data conversion serially entered is transferred at parallel data by next stage by register module, to realize the data transmission of display device low-power consumption.
Description
Technical field
The utility model relates to display fields, more particularly, to the data transmission circuit and display device of a kind of low-power consumption.
Background technique
With the continuous development of digital display circuit, the requirement to the high efficiency of transmission and low power consumption transmission of data is higher and higher.?
It in micro display system, generally requires to a large amount of data while handling, the at this moment design of clock system just seems especially heavy
It has wanted.The data efficient received can be transferred on required circuit by good clock system, while power consumption can reach very
It is low.
Summary of the invention
In order to solve the above problems, the utility model proposes a kind of novel clock packet circuit and display device.
The main contents of the utility model include:
A kind of data transmission circuit of low-power consumption, including clock grouping module, clock processing module and registration module,
In,
The clock grouping module, have a clock signal input interface, n enabled clock signal input interfaces and
N grouping clock signal output interface；Clock control signal outside the clock signal input interface, when described enabled
Clock signal input interface receives clock enable signal, and when one of clock enable signal is high level, other clocks make
Energy signal is low level；
There is the clock processing module clock commencing signal input interface, n grouping clock signal input to connect
Mouth, N number of shift register and N number of control clock output interface；The n grouping clock signal input interface and the n are a
It is grouped the connection of clock signal output interface；The clock signal input of n grouping clock signal input interface and N number of shift register
End is one-to-many connection；N number of shift register is sequentially connected in series, and the data input of first shift register
End is connect with the clock commencing signal input interface；The output of N number of shift register and N number of control clock output
Interface connection；Wherein, n < N；
The register module is enabled with N number of control clock input interface, a serial date transfer interface, one
Signal input interface and a parallel data output interface；N number of control clock input interface and N number of control clock
Output interface connection, the serial date transfer interface are connect with external data channel.
Preferably, the clock grouping module includes n AND gate circuit, two inputs difference of the single AND gate circuit
It is connect with the clock signal input interface and an enabled clock signal input interface.
Preferably, the registration module includes buffering latch units and data output unit；The buffering latch units tool
There are N number of data cached output interface and N number of register, the input end of clock of N number of register and N number of control clock input
Interface connection；The data input pin of N number of register is connect with the serial date transfer interface；N number of register
Data-out port is connect with the data cached output interface, and the data cached output interface and data outputting unit connect
It connects.
Preferably, the data outputting unit has N number of latch and N number of data cached input interface, N number of lock
The enable signal input terminal of storage is connect with the enable signal input interface；The data input pin of N number of latch with it is N number of
Data cached input interface connection, N number of data cached input interface are connect with the data cached output interface；The N
The output end of a latch is connect with the parallel data output interface.
The utility model also proposed a kind of display device, including horizontal drive circuit, column drive circuit and pixel are shown
Unit and data input module, wherein the pixel display unit includes with the M of array manner arrangement × N number of pixel unit electricity
Road, the horizontal drive circuit and the column drive circuit are connect with the pixel unit circuit；The data input module packet
M data channel is included, the M data channel is connect with the column drive circuit；The column drive circuit is used as right is wanted
The data transmission circuit for asking 1 to 4 any low-power consumption, by the data conversion of serial input at being transmitted to institute after parallel data
State pixel display unit.
Preferably, the data transmission circuit for the low-power consumption that the column drive circuit uses includes clock point
Group module, the M clock processing modules and M register module；The clock grouping module respectively with M clocks
Processing module connection；The M register module is correspondingly connected with the M data channel.
The utility model has the beneficial effects that: the utility model proposes a kind of data transmission circuit of low-power consumption and
Using the data transmission circuit into the display device of Drive of row and column, by enabling clock signal, in clock grouping module clock synchronization
Clock signal is grouped, and sequentially turns on the clock signal after grouping in the clock processing module, reduces clock overturning
The power consumption of consumption.Meanwhile under the control of clock signal after grouping, the data conversion that will serially be entered by register module
It is transferred to next stage at parallel data, to realize the data transmission of display device low-power consumption.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the utility model data transmission circuit；
Fig. 2 is the structural schematic diagram of the utility model display device.
Specific embodiment
The technical solution protected below in conjunction with attached drawing to the utility model illustrates.
The utility model proposes a kind of data transmission circuits of low-power consumption, and carry out column drive using data transmission circuit
Dynamic display device.The display device includes horizontal drive circuit, column drive circuit and pixel display unit, and pixel is shown
The size of unit is denoted as M*N, i.e., the described pixel display unit is the matrix of M × N size, and the horizontal drive circuit described first chooses certain
Row, then the column drive circuit uses the data transmission circuit of the utility model by the data conversion of serial input at simultaneously line number
According to rear, simultaneous transmission to pixel display unit.
Please refer to Fig. 1 and Fig. 2.Below by taking the micro display chip of LCOS digital pixel driving as an example, illustrate the utility model
Content；The micro display chip of this LCOS digital pixel driving includes the M × N number of pixel unit circuit arranged with array manner,
The pixel unit circuit is connected with the output of row driving and column driving respectively.
In the present embodiment, the data transmission circuit of the column drive circuit includes a clock grouping module and M
Clock processing module and M register module, i.e., the described data transmission circuit can handle M group serial input data simultaneously, often
Group serial input data includes the data of N number of serial input；Wherein, a clock grouping module receives n enabled clocks
One clock signal is divided into n group by the driving of signal, and the clock signal after grouping is after the clock processing module, as institute
The control clock signal of shifting processing module is stated, that is, the clock signal after being grouped obtains successively after the clock processing module
The control clock signal of conducting, so that power consumption consumption when clock overturning is reduced, then through the latching buffer in register module
Memory cell successively latches N number of input data, finally under the control of the data outputting unit, by the input data of N number of latch
It exports simultaneously, to realize that serial data is converted into parallel data；The clock grouping module is simultaneously M clock processing module
Grouping clock signal is provided；Each clock processing module is connect with a register module.
The clock grouping module, have a clock signal input interface, n enabled clock signal input interfaces and
N grouping clock signal output interface；Clock control signal outside the clock signal input interface, when described enabled
Clock signal input interface receives clock enable signal, and when one of clock enable signal is high level, other clocks make
Energy signal is low level；
There is the clock processing module clock commencing signal input interface, n grouping clock signal input to connect
Mouth, N number of shift register and N number of control clock output interface；The n grouping clock signal input interface and the n are a
It is grouped the connection of clock signal output interface；The clock signal input of n grouping clock signal input interface and N number of shift register
End is one-to-many connection；N number of shift register is sequentially connected in series, and the data input of first shift register
End is connect with the clock commencing signal input interface；The output of N number of shift register and N number of control clock output
Interface connection；Wherein, n < N；
The registration module has N number of control clock input interface, a serial date transfer interface, an enabled letter
Number input interface and a parallel data output interface；N number of control clock input interface and N number of control clock are defeated
Outgoing interface connection, the serial date transfer interface are connect with external data channel.
In order to make it easy to understand, will illustrate the technical solution of the utility model for n=5 with N=30 below.
The clock grouping module is used to be grouped the clock signal of column drive circuit by enabled clock signal,
Specifically, the clock grouping module includes 5 AND gate circuits, and the clock grouping module has 1 clock signal input
Interface CLK1,5 enabled clock signal input interface CLK<0>, CLK<1>, CLK<2>, CLK<3>and CLK<4>and 5 points
Group clock signal output interface CLK_D<0>~CLK_D<4>；Two of AND gate circuit inputs respectively with the clock signal
Input interface is connected with one of them enabled clock signal input interface, i.e., by clock signal successively with 5 enabled clock signals
It carries out and operates, clock signal clk _ D<0>~CLK_D<4>after obtaining 5 groupings, and work as one of clock enable signal
When for high level, other clock enable signals are low level；I.e. under the action of first enabled clock signal clk<0>, clock
When preceding 6 pulses of signal CLK1 are effective, and subsequent clock waveform be continuously it is low；When second enabled clock signal clk<1>
When input, second group of 6 pulse of clock signal clk 1 are effective, and first group of 6 pulse and subsequent clock waveform continue
To be low, and so on, i.e., only one group of clock signal is effective every time.
The clock processing module receives the input of the clock grouping module, obtains control clock signal with low power,
The clock processing module in one of the embodiments, has a clock commencing signal input interface START, 5 groupings
Clock signal input interface CLK_DI<0>~CLK_DI<4>, 30 shift register shift and 30 control clock outputs
Interface 1_out~30_out；5 grouping clock signal input interface CLK_DI<the 0>~CLK_DI<4>with described 5 points
Group clock signal output interface CLK_D<0>~CLK_D<4>connection；5 grouping clock signal input interfaces are posted with 30 displacements
The clock signal input terminal of storage is one-to-many connection, i.e., one grouping clock signal input interface CLK_DI<0>~CLK_
DI<4>is connect with the clock signal input terminal of shift register described in one or more, it is preferred that each grouping clock signal
Input interface CLK_DI<0>~CLK_DI<4>is connect with the clock signal input terminal of 6 shift registers therein；And it is described
30 shift registers are sequentially connected in series, and the 5 grouping clock signal input interface CLK_DI<0>~CLK_DI<4>can be with
Successively it is connect in order with the shift register shift of 6 sequential concatenations；Meanwhile first shift register shift
Data input pin is connect with the clock commencing signal input interface START；The output of 30 shift registers with it is described
30 control clock output interface connections.
From the foregoing, it will be observed that effective due to only having a grouping clock signal every time, then only 6 shift registers wait every time
Work, remaining 24 shift register then when the grouping clock signal of its connection is effective, just start waiting；To reduce function
Consumption.
30 control clock signals of each clock processing module are sequentially generated, and are successively used as the registration module
Input control described in register module start to work；The registration module includes that buffering latches in one of the embodiments,
Unit and data outputting unit；The buffering latch units have 30 data cached output interfaces and 30 registers, institute
The input end of clock for stating 30 registers is connect with 30 control clock input interfaces；Since 30 control clock signals successively produce
It is raw, therefore 30 registers are sequentially generated its respective data output, for a serial date transfer interface DATA, successively
30 data that transmission comes then successively are connect with the data input pin of 30 registers as input respectively, to successively obtain 30
A data cached, this 30 data cached to be temporarily stored in the data outputting unit, waits the enabled of the output unit
When signal is effective, while by 30 data cached outputs；Correspondingly, the data outputting unit has 30 latch and 30
A data cached input interface, the enable signal input terminal and the enable signal input interface CLK2 of 30 latch connect
It connects；The data input pin of 30 latch is connect with 30 data cached input interfaces, 30 data cached inputs
Interface is connect with the data cached output interface；The output end and the parallel data output interface of 30 latch connect
It connects.
The above description is only the embodiments of the present invention, and therefore it does not limit the scope of the patent of the utility model, all
Equivalent structure or equivalent flow shift made based on the specification and figures of the utility model, is applied directly or indirectly in
Other related technical areas are also included in the patent protection scope of the utility model.
Claims (6)
1. a kind of data transmission circuit of low-power consumption, which is characterized in that including clock grouping module, clock processing module and post
Buffer module, wherein
The clock grouping module has a clock signal input interface, n enabled clock signal input interface and n
It is grouped clock signal output interface；Clock control signal outside the clock signal input interface, the enabled clock
Signal input interface receives clock enable signal, and when one of clock enable signal is high level, other clocks are enabled
Signal is low level；
The clock processing module has a clock commencing signal input interface, n grouping clock signal input interface, N number of
Shift register and N number of control clock output interface；When the n grouping clock signal input interface and the n grouping
The connection of clock signal output interface；The clock signal input terminal of n grouping clock signal input interface and N number of shift register is one
To more connections；N number of shift register is sequentially connected in series, and the data input pin of first shift register and institute
State the connection of clock commencing signal input interface；The output of N number of shift register and N number of control clock output interface connect
It connects；Wherein, n < N；
The register module has N number of control clock input interface, a serial date transfer interface, an enable signal
Input interface and a parallel data output interface；N number of control clock input interface and N number of control clock output
Interface connection, the serial date transfer interface are connect with external data channel.
2. a kind of data transmission circuit of low-power consumption according to claim 1, which is characterized in that the clock grouping module
Including n AND gate circuit, two inputs of the single AND gate circuit respectively with the clock signal input interface and one
Enabled clock signal input interface connection.
3. a kind of data transmission circuit of low-power consumption according to claim 1, which is characterized in that the register module packet
Include buffering latch units and data output unit；The buffering latch units have N number of data cached output interface and N number of post
Storage, the input end of clock of N number of register are connect with N number of control clock input interface；The data of N number of register are defeated
Enter end to connect with the serial date transfer interface；The data-out port of N number of register and the data cached output
Interface connection, the data cached output interface are connect with data outputting unit.
4. a kind of data transmission circuit of low-power consumption according to claim 3, which is characterized in that the data outputting unit
With N number of latch and N number of data cached input interface, the enable signal input terminal of N number of latch is enabled with described
Signal input interface connection；The data input pin of N number of latch is connect with N number of data cached input interface, described N number of slow
Deposit data input interface is connect with the data cached input interface；The output end of N number of latch and the parallel data
Output interface connection.
5. a kind of display device, which is characterized in that including horizontal drive circuit, column drive circuit and pixel display unit and data
Input module, wherein the pixel display unit includes the M × N number of pixel unit circuit arranged with array manner, and the row drives
Dynamic circuit and the column drive circuit are connect with the pixel unit circuit；The data input module includes that M data are logical
Road, the M data channel are connect with the column drive circuit；The column drive circuit is used such as any institute of Claims 1-4
The data conversion of serial input is shown list at the pixel is transmitted to after parallel data by the data transmission circuit for the low-power consumption stated
Member.
6. a kind of display device according to claim 5, which is characterized in that the low function that the column drive circuit uses
The data transmission circuit of consumption includes a clock grouping module, the M clock processing modules and M register mould
Block；The clock grouping module is connect with the M clock processing modules respectively；The M register module and the M numbers
It is correspondingly connected with according to channel.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201822036476.7U CN209118742U (en) | 2018-12-05 | 2018-12-05 | A kind of data transmission circuit and display device of low-power consumption |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201822036476.7U CN209118742U (en) | 2018-12-05 | 2018-12-05 | A kind of data transmission circuit and display device of low-power consumption |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110825210A (en) * | 2019-11-12 | 2020-02-21 | 天津飞腾信息技术有限公司 | Method, apparatus, device and medium for designing clock tree structure of system on chip |
| CN112820225A (en) * | 2019-11-15 | 2021-05-18 | 京东方科技集团股份有限公司 | Data cache circuit, display panel and display device |
| CN114239475A (en) * | 2021-12-17 | 2022-03-25 | 郑州信大华芯信息科技有限公司 | Low-frequency digital-analog mixed module clock structure and scan chain design method |
-
2018
- 2018-12-05 CN CN201822036476.7U patent/CN209118742U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110825210A (en) * | 2019-11-12 | 2020-02-21 | 天津飞腾信息技术有限公司 | Method, apparatus, device and medium for designing clock tree structure of system on chip |
| CN112820225A (en) * | 2019-11-15 | 2021-05-18 | 京东方科技集团股份有限公司 | Data cache circuit, display panel and display device |
| CN112820225B (en) * | 2019-11-15 | 2023-01-24 | 京东方科技集团股份有限公司 | Data cache circuit, display panel and display device |
| CN114239475A (en) * | 2021-12-17 | 2022-03-25 | 郑州信大华芯信息科技有限公司 | Low-frequency digital-analog mixed module clock structure and scan chain design method |
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