JP3142319B2 - Control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control circuit for a drive unit which is driven in response to a predetermined signal including a display device, and more particularly, to power consumption of driver means for driving the drive unit. And a control circuit capable of reducing the size of the output inverter.

[0002]

2. Description of the Related Art Conventionally, display means such as a liquid crystal display, an LED display, a plasma display, and a fluorescent tube display, which are generally used as an example of a driving unit driven in response to a predetermined signal, are respectively provided. It is necessary to turn on / off the pixel body at a predetermined timing, and therefore, a large number of driver circuits composed of ICs are used.

[0003] Such a display driver is mainly composed of C-MOS transistors, so that it generally consumes a large amount of power. In the case of this display device, the number of drivers is inevitably large. As the power consumption has increased, it has become an important issue how to reduce the power consumption.

On the other hand, as a driving unit driven in response to a predetermined signal, there are various kinds of driving means in addition to the information display device described above.
The driver circuit used for the display means as described above will be described using a liquid crystal display as an example, but it goes without saying that the present invention is not limited to only the example according to the present invention.

FIG. 10 shows an example of a conventional driving circuit for a color liquid crystal display. A color liquid crystal panel 1 for a color liquid crystal display has, for example, 640.times.RGB.times.480 pixels arranged in a matrix. Are arranged. In the color liquid crystal panel 1, the R,
Each of the one color pixel including three pixels of G and B is selected by selecting each of the gate driver circuits 21 to 2m (or 2) and the source driver circuits 31 to 3n (or 3). Display is performed.

The gate driver circuits 21 to 2m and the source driver circuits 31 to 3n are all connected to a timing generation circuit 5, and the source driver circuits 31 to 3n
Is connected to an RGB analog amplifier 4, and furthermore, the timing generation circuit 5 and the RGB analog amplifier 4
It is connected to the decoder circuit 6. The gate driver circuits 21 to 2m of the color liquid crystal display respectively receive a predetermined number of rows for the 480 rows provided in the display, and sequentially read the rows one by one according to a clock pulse of the timing generation circuit. Scan and select.

On the other hand, each of the source driver circuits 31 to 3n receives a predetermined number of columns from the number of 640 × RGB columns and scans the columns one by one according to a clock pulse of the timing generation circuit. Go. Therefore, in such a display, the scanning speed of the gate driver circuits 21 to 2m may be relatively low, but the scanning speed of the source driver circuits 31 to 3n is much larger than the scanning speed of the gate driver circuit 2. Need to be faster.
FIG. 11 shows a configuration example of the source driver circuit 3 of the display in the related art.

That is, the source driver circuits 31 to 3n
Are an X-bit shift register 301 composed of a bidirectional shift register and the like, an X-bit control gate 30
2, X-bit sample-and-hold circuit 303, X-bit latch circuit 304 and the X-bit output buffer 305. I Oh those which are composed of, the X-bit shift register 301, a start pulse input signal STI, the clock pulses CLK, shift direction indication signal L / R and a start pulse delivered determination control signal DS and the like are input, the start pulse output signal STO is configured to be output.

The X-bit shift register 301 and the X-bit shift register
An enable signal EN between the X-bit control gate 302 and the X-bit control gate 302 and the X-bit sample and hold circuit 303, respectively.
1, EN2 and EN3 and RGB signals are input. If more clarity in have One the specific description of the operation of the circuit according, as shown in FIG. 12, each such source driver circuit 3
An X-bit shift register 301 and the X-bit sample-and-hold circuit 303 are provided for each of the first to third n.
1 and the RGB signals are input to the X-bit sample and hold circuit 303, respectively.

Then, the X-bit shift register 301
Represents a plurality of adjacent source driver circuits 31 to 3n
X bit shift register 30 provided in
1, and the source driver circuits 31 to 3n are cascaded with each other. The sample and hold circuit 303 shifts in response to the shift of the X-bit shift register 301 in response to the clock pulse CLK, and latches the data at that time.

In the display having the above structure, when the X-bit shift register 301 of each source driver circuit is full, a drive command is issued to the next adjacent X-bit shift register 301 to shift the data. This operates the shift register. Therefore, the line of the display, that is, one line, that is, 640
Until 1920 × RGB pulses are output, the X-bit shift registers 301 of all the source driver circuits 31 to 3n continue to operate, and the sample hold circuit 303 also continues to store data during that time.

As described above, since the shift register circuit is usually formed of a C-MOS, a through current flows through each register every time the clock signal CLK is input. There is a problem that there is a fear that the number of the registers is enormous and the total amount of through current increases, thereby increasing power consumption.

[0013]

That is, in the above-described conventional display device, a plurality of source drivers 31 are provided.
3n are cascaded, so that the clock signal and R
Since GB signal is common to all the source driver circuit, say because another source driver circuit even if an attempt to write to one of a source driver circuit even become activated simultaneously become unnecessary power supply current flows and the problem, if the display panel brightness device Ru further name to a large source driver
Since coming more and more as necessary number of circuit increases also the current consumption of the above, in particular at the display de I spray device for the mobile phone, also a problem that the not stand to practical use because the consumption of the battery is violently Will happen.

Further, as the size of the display display device increases, the driving capability of the main clock and the RGB decreases, so that the size of the input buffer must be increased. In addition to being a factor, there is another problem that it is difficult to reduce the size and weight of the display device itself. SUMMARY OF THE INVENTION An object of the present invention is to solve the problems in the prior art, reduce power consumption, and reduce power consumption and reduce size and weight even when a driving device including a driving unit including a display device is enlarged. And a control circuit of the driving device that can realize the above.

[0015]

The present invention employs the following technical configuration to achieve the above object. That is, a plurality of units including a driving unit having a plurality of unit driving elements, and shift register means for independently controlling a plurality of predetermined regions including a predetermined number of unit driving element groups in the driving unit. I Oh in number of driver means, a plurality several driver means which are connected in cascade to each other through the shift register means, said double
In a control circuit composed of decoder means for supplying a predetermined signal to each of several driver means and timing generating means for supplying a predetermined timing signal to the shift register means, each of the driver means the includes a timing generator means and connected to control means, control means, other driver means while a particular driver means in said plurality several driver means is operating interrupted so its operation And the plurality of drivers
The means is a predetermined driver means in the plurality of driver means.
The shift register responds to a predetermined operation start control signal.
Operating the decoder means, and a signal supplied from the decoder means.
After performing the calculation processing and performing the display operation, the calculation end signal is output.
Generated and the operation end signal is adjacent to the predetermined driver means.
To the next-stage driver means,
In response to the
A control circuit configured to be inactive until a signal is input .

[0016]

[Action] The control circuit of the drive device including a drive unit according to the present invention, because it uses the above configuration, a plurality of driver means disposed on the control circuit, a predetermined driver means, While operating by receiving a predetermined signal,
The other driver means can interrupt its operation, so that the amount of current consumed by the control circuit to drive the drive unit is greatly reduced, and that the temporarily driven driver means Since the number becomes extremely small, the amount of load on the control circuit is reduced and the size of the input inverter can be reduced, so that it is possible to manufacture a low power consumption type drive device which can be reduced in size and weight.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a control circuit according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram illustrating a specific example of the control circuit according to the present invention, and also a diagram illustrating the principle of the control circuit according to the present invention. That is, FIG. 1 is an enlarged view of a main part of a driver means (source driver circuit ) of a driving device using the display means shown in FIG. 10 as an example according to the configuration of the present invention.

That is, FIG. 1 shows a driving section 1 having a plurality of unit driving elements (see FIG. 2 described later: FIGS. 2 and 10).
Ra corresponding to the liquid crystal panel), and a shift register unit 301 (FIG. 1 for controlling plurality of divided the predetermined area A1~An the independently comprising units driving circuitry of at predetermined number of the driving unit 1 and X bit shift register of FIG.
Supplies I Oh a plurality of driver means 31 ~ 3n, and driver means 31 ~ 3n which are cascade-connected to each other via the shift register unit 301, a predetermined signal to the respective driver means including a support) to Decoder means 6 (later
Refer to FIG. 3 described above: In the RGB decoder circuit of FIGS.
And a timing generating means 5 for supplying a predetermined timing signal to the shift register means 301 (see FIG.
(Refer to the timing generation circuits of FIGS. 3 and 10).
Each of ~ 3n includes a control unit 306 connected with the timing generator 5, control means 306,
While the specific driver means of the plurality in several driver means 31 ~ 3n is operating other driver means is a control circuit having a control unit 306 that is configured for interrupting its operation.

In the present invention, each driver means drives a driven element in a predetermined area A in a drive section which is shared by the driver means, as shown in FIG. May be included. In operation of the control unit 306 according to the present invention, the basic action of the control means, the control means 306 as described above, from the plurality several driver means 31 3
While specific driver means in n is operating another driver means be one that operates for interrupting its operation, specifically, now, in order to operate one of the driver unit 31 A predetermined clock signal CLK is supplied to the control unit 30.
6, the shift register 301 starts operating and drives the driven element in the drive area A1 of the drive unit while a predetermined number of pulses are input.

When a clock signal of a predetermined number of pulses is input, the shift register outputs a count-up signal, transmits the output to another driver 32 adjacent to the shift register, and transmits the output signal to the control unit 306. Return to In the control unit 306, when the count-up signal from the shift register 31 is input to the signal as a trigger, the clock signal CLK is prohibited from Ru is supplied to the shift register 301.

Therefore, at that time, the shift register 3
01 is stopped, but instead, the shift register of the adjacent driver means 32 continues to operate, and after the same operation, the shift register of the next driver means 33 starts operating. As described above , while the shift registers of the respective driver means are stopped one after another and the adjacent driver means are sequentially operated, the last driver means 3
Operate to n. Then, returning to the first driver means 31, the same operation is repeated.

In the control means 306 of the present invention, a predetermined control signal PD for realizing the above function is provided.
It is preferable to use I and perform the above operation after the control signal PDI is input. The control signal PDI takes an appropriate logic with the count-up signal from the shift register to supply the clock signal CLK to the shift register 301 and to output the RGB signal.
The supply of signals is prohibited. Specifically, the first
The control means 306 of the first driver means 31 supplies the count-up signal from the shift register of the preceding driver means to the control signal PDI. Function.

In the present invention, the shift register of each driver means is temporarily stopped by the above configuration, and then stopped until the control signal PDI is inputted and the shift register starts operating. Therefore, for example, in a liquid crystal display device or the like, a predetermined signal during that time,
Since a predetermined driven element must be illuminated, in such a case, it is preferable to use the above-described sample and hold circuit together.

FIGS. 2 and 3 show examples of the configuration of a color liquid crystal panel using the control circuit according to the present invention. In the figure, the same circuits as those in FIGS. 10 and 11 are denoted by the same reference numerals.
As can be seen from FIGS. 2 and 3, the shift register 301 of the driver means is cascaded with the shift register of the adjacent driver means, and the control means 306 of each driver means is connected to each other. Except for the control means of the first driver means, the count-up output PDO of the shift register of the preceding driver means is input to the control means. On the other hand, the control means 306 of said first driver means 31, a control signal PDI generated from the timing generating circuit 5 are inputted.

In FIGS. 2 and 3, the signals DS, L / R, STI and STO input to each shift register 301 are the same as those shown in FIG.
Further, in the conventional driver means, the clock signal CLK is directly input to the shift register. In the present invention, the clock signal CLK is input to the control means 306.

Similarly, in the conventional driver means, the RGB signal is input to the sample and hold circuit together with the signal from the control gate. In the present invention, the RGB signal is input to the control means. It is configured to be. In the driving device having such a configuration, first, the gate driver circuit 21 for driving the first line of the color liquid crystal panel is turned ON, and a control signal PDI is output from the timing generation circuit 5 once. It is input to the control means 306 of the driver means 31.

As a result, the shift register 301 of the driver means 31 starts operating, and the operation is continued in accordance with the above-mentioned procedure, and the shift registers up to the driver means 31 to 3n sequentially start and stop operating. Is repeated until the last stage driver means 3n of the line is reached. When the shift register of the last-stage driver outputs the count-up signal STO, the timing generator 5 generates a signal for driving the gate driver 22 and a new control signal PDI in response to the count-up signal STO. Is repeated.

Next, a specific example of the control means used in the present invention will be described below with reference to FIGS.
FIG. 4 shows a specific example of the control means according to the present invention, in which two NAND gate circuits 41 and 42, two inverters 43 and 44, and four transfer gates T are provided.
G1 to TG4 and a counter 45.

The two-input NAND gate circuits 41 and 42
Constitutes a latch circuit. One input of the two-input NAND gate 41 receives the control signal PDI, and the count-up signal PDO from the counter 45 receives the two-input NAND gate via the inverter 43. Gate circuit 4
2 is input to one of the inputs. The count-up signal PDO is supplied to the control signal PDI of the two-input NAND gate circuit 41 in the control means 306 of the next driver means.
This is input to the input corresponding to the input.

On the other hand, the output of the two-input NAND gate circuit 41 is connected to the other input of the two-input NAND gate circuit 42, and the output of the two-input NAND gate circuit 42 is connected to the other input of the two-input NAND gate circuit 41. Is connected to the input. The output of the NAND gate circuit 41 is connected to one of the transfer gates TG1 to TG4.
4 are connected to other gates of the transfer gates TG1 to TG4.

Further, the transfer gates TG1 to TG
One of the RGB signals is input to each input of G3, and the clock signal CLK is input to the input of the transfer gate TG4. Therefore, when the control signal PDI is now input, the NAND gate circuit 41
Outputs an "H" level signal and the inverter 44 outputs an "L" level signal, so that each of the transfer gates TG1 to TG4 is turned on,
Therefore, the signals RGB respectively transfer gates TG
(OR, OG, O)
B) While being input to the control gate, the clock signal CLK passes through the transfer gate TG4 and is input to the shift register as an output signal OCLK to operate the shift register.

Next, when the shift register counts a predetermined clock pulse, a count-up signal PDO is output from the counter 45, and when the count-up signal PDO is input to the NAND gate circuit 42 via the inverter 43, the NA
Since the output of the ND gate circuit 41 changes to "L" level and the output of the inverter 44 changes to "H" level, all of the transfer gates TG1 to TG4 are turned off.
Therefore, both the clock signal CLK and the signal RGB are cut off by the transfer gates TG1 to TG4 and are not supplied to the control gate and the shift register.

Therefore, the shift register of the driver means stops operating at that time and waits until the next control signal PDI is input. On the other hand, the count-up signal PDO output from the counter 45 is supplied to the control means of the next-stage driver means, and the control means executes the same operation as the control signal PDI. Will be executed. The timing of such an operation is shown by the waveform in FIG.

Next, another specific example of the control means according to the present invention is shown in FIG. In the specific example of FIG. 4, the clock signal C
Transfer gate TG for analog control of LK
In contrast, the control means of FIG. 6 employs a configuration in which the digital circuit of the 2-input NAND gate circuit 46 and the inverter 47 is replaced.

The operation of this circuit is substantially the same as that of the circuit of FIG. 4, and the operation timing is also shown in FIG. 7, but is the same as that of FIG. However, this specific example is different in that the polarity of the count-up signal PDO is reversed. FIG. 8 shows another specific example of the control means according to the present invention. In this specific example, a two-input NOR gate circuit 50 and two inverters 48 are used to control the clock signal CLK.
A digital circuit composed of 49 digital circuits is employed.

FIG. 9 shows a waveform diagram relating to the operation of the control means, which is substantially the same as that of FIG. Needless to say, the control circuit according to the present invention is also applicable to the gate driver circuit of FIG.

[0037]

Since the present invention adopts the above configuration, it is possible to reduce the power consumption of the entire control circuit, so may improve the driving capability of the clock signal, the size of the input buffer It is also possible to make it smaller.

[Brief description of the drawings]

FIG. 1 is a diagram showing the principle of Figure a is also controlling means according to the present invention showing the configuration of an embodiment of a control means used in the control circuit according to the present invention.

FIG. 2 is a block diagram showing a part of a specific example of a driving device using a control circuit according to the present invention.

FIG. 3 is a block diagram showing a part of a specific example of a driving device using a control circuit according to the present invention.

FIG. 4 is a block diagram showing a configuration of a specific example of a control unit according to the present invention.

FIG. 5 is a timing chart of the control means shown in FIG. 4;

FIG. 6 is a block diagram showing the configuration of another specific example of the control means according to the present invention.

FIG. 7 is a timing chart of the control means shown in FIG. 6;

FIG. 8 is a block diagram showing the configuration of another specific example of the control means according to the present invention.

FIG. 9 is a timing chart of the control means shown in FIG. 8;

FIG. 10 is a diagram illustrating an example of a conventional driving device.

FIG. 11 is a diagram illustrating a configuration example of a driver unit used in a conventional driving device.

FIG. 12 is a diagram for explaining an operation of a conventional driver means.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Drive part (color liquid crystal panel ) 2 ... Gate driver circuit 3 ... Source driver circuit 4 ... RGB analog amplifier 5 ... Timing generation circuit 6 ... RGB decoder circuit 41,42,46 ... 2-input NAND gate circuit 45 ... Counter 43 44, 47, 48, 49 inverter 50 two-input NOR gate circuit TG transfer gate 301 X bit shift register 302 X bit control gate 303 X bit sample and hold circuit 304 X bit latch circuit 305 X bit output Buffer 306: control means

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-56-4184 (JP, A) JP-A-55-164889 (JP, A) JP-A-58-75196 (JP, A) JP-A 61-184 254988 (JP, A) JP-A-60-91391 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/20 G02F 1/133 H03K 17/00 G09G 3/36

Claims (5)

(57) [Claims] A driving unit having a plurality of unit driving elements;
And, I Oh a plurality of driver means including shift register means for controlling plurality of divided predetermined region independently containing a predetermined number of unit driving element group in to the drive unit, the shift register means decoder means for supplying a plurality several driver means which are connected in cascade to each other, a predetermined signal to each of said plurality of de <br/> driver means through a
When, in the control circuit consisting of a timing generator means for supplying a predetermined timing signal to the shift register means, each of said plurality of driver means comprises control means connected to said timing generating means cage, said control means, while a particular driver means in said plurality several driver means is operating another driver means is configured so suspend its operation, further, the plurality of driver means , The plurality of dry
A predetermined driver means in the memory means activates the shift register means in response to a predetermined operation start control signal, performs an arithmetic operation on a signal supplied from the decoder means , executes a display operation, and then executes an operation end signal. It generates the said calculation end signal
Together transmitted to the next stage of the driver means adjacent to a predetermined driver means, responsive to said operation end signal to the state of inoperative until its own arithmetic processing function next operation start control signal is input Control characterized by being configured
Circuit . Wherein the control means, according to claim 1 Symbol, characterized in that the sample-and-hold circuit and a latch circuit is included
Control circuit of the mounting. 3. The control circuit according to claim 1, wherein said drive section includes a device for displaying information. 4. The information display means includes a liquid crystal panel, an LED,
4. The control circuit according to claim 3 , wherein the control circuit comprises one selected from a panel, a plasma display, a fluorescent display panel, and the like. 5. The control means is arranged such that a predetermined clock signal is not supplied to a shift register means of another driver means while a specific driver means among the plurality of driver means is operating. claim 1 Symbol, characterized in that is configured for interrupting the operation of said driver means
Control circuit of the mounting.