CN114970442B

CN114970442B - Multi-layer global wiring method considering bus perception

Info

Publication number: CN114970442B
Application number: CN202210604474.1A
Authority: CN
Inventors: 刘耿耿; 魏凌; 郭文忠; 陈国龙
Original assignee: Fuzhou University
Current assignee: Fuzhou University
Priority date: 2022-05-31
Filing date: 2022-05-31
Publication date: 2024-08-30
Anticipated expiration: 2042-05-31
Also published as: CN114970442A

Abstract

The invention provides a multi-layer global wiring method considering bus perception, which comprises the following key strategies: 1) By introducing a wiring density chart, a wiring model for controlling bus wiring through wiring density is designed, and the wiring rate of a non-bus and the deviation value of the bus can be considered at the same time; 2) The optimization of bus deviation is completed by dynamically adjusting a local disconnecting and re-distributing model of wiring resources, so that bus time delay is effectively reduced; 3) Designing a DFS-based multi-result tracking algorithm to obtain a plurality of wiring schemes; 4) A layer allocation algorithm based on bias perception is designed to significantly reduce bus bias of a 3D wiring scheme. A global wiring scheme with small bus skew and high quality can be obtained.

Description

Multi-layer global wiring method considering bus perception

Technical Field

The invention belongs to the technical field of integrated circuit computer aided design, and particularly relates to a multilayer global wiring method considering bus perception in a very large scale integrated circuit.

Background

With the continuous development of industrial manufacturing technology, advanced technology nodes enter into the deep nanometer age, and the design complexity of chips is dramatically increased. In modern VLSI designs, buses are increasingly being used in larger proportions in the network, and the buses that transmit are widely used for transmitting parallel signals between functional modules and macros. These signals need to be guaranteed to arrive at the same time, so the bus wiring is a determining factor in the VLSI wiring in determining timing and power consumption. Timing matching is an important bus design constraint in VLSI designs. Each signal bit in the same bus needs to transmit a corresponding signal, usually, the line length of the signal bit is used as a standard of signal transmission time, and if the line length is too long or too short, bus deviation can be generated, so that the time sequence of the chip is poor, and the performance of the chip is greatly reduced. Global routing can be generally divided into two stages, a 2D routing stage and a layer allocation stage, where the 2D routing stage is to wire-net multiple layers of routing resources and non-buses and buses onto a 2D plane, and then complete routing on the 2D plane to obtain an initial 2D routing result.

The idea of disconnecting and re-distributing is to select some wire net paths deteriorating the chip performance after the initial wiring is completed for dismantling, and then re-plan the paths according to a certain rule, update the paths into the original wiring, thereby achieving the purpose of improving the wiring quality. The wire-stripping-re-distribution wiring method is generally used for improving the wire-distribution rate of the wire net, and on the basis of the wire-stripping-re-distribution wiring method, factors such as time sequence analysis, the number of through holes and the like are gradually developed, so that the wire net can be smoothly distributed, and meanwhile, a desired high-quality result is obtained.

Disclosure of Invention

In order to make up for the blank and the deficiency of the prior art, the invention provides a multi-layer global wiring method considering bus perception, and aims to minimize the total wire length deviation, the total wiring rate and the total wire length by optimizing a global wiring algorithm.

The invention specifically comprises the following design processes:

1. a wiring density diagram is introduced in the process of 2D wiring, a wiring model for controlling bus wiring through wiring density is designed, and the wiring rate of non-buses and the deviation value of buses can be considered at the same time, so that the quality of a wiring result is ensured.

2. The optimization of bus deviation is completed by dynamically adjusting the local disconnecting and re-distributing model of the wiring resource, so that bus time delay is effectively reduced.

3. A DFS-based multi-result tracking algorithm is designed to pick a low-variance routing result that sacrifices a small number of routing wire lengths.

4. A layer allocation algorithm based on bias perception is designed to significantly reduce bus bias of a 3D wiring scheme by taking bus-to-non-bus differences into account.

As advanced technology nodes enter the deep nanometer age, the complexity of integrated circuit designs becomes more and more complex, the proportion of buses in the net becomes larger and larger, and bus wiring becomes a key factor affecting chip performance. The existing global wiring algorithm often ignores the existence of a bus, and directly leads to expansion of bus delay, thereby leading to reduced chip performance. In addition, in the prior art, bus wiring is not performed by distinguishing buses from non-buses in the complete wiring process, so the invention provides a multi-layer global wiring method considering bus perception, which comprises the following key strategies: 1) By introducing a wiring density chart, a wiring model for controlling bus wiring through wiring density is designed, and the wiring rate of a non-bus and the deviation value of the bus can be considered at the same time; 2) The optimization of bus deviation is completed by dynamically adjusting a local disconnecting and re-distributing model of wiring resources, so that bus time delay is effectively reduced; 3) Designing a DFS-based multi-result tracking algorithm to obtain a plurality of wiring schemes; 4) A layer allocation algorithm based on bias perception is designed to significantly reduce bus bias of a 3D wiring scheme. A global wiring scheme with small bus skew and high quality can be obtained.

The invention adopts the following technical scheme:

A multi-layer global wiring method considering bus perception is characterized in that: in the 2D wiring stage, firstly, wiring information is compressed onto a 2D wiring plane, a topological structure is generated for all wires by a FLUTE algorithm, and non-buses are subjected to L-type wiring so as to obtain a wiring density diagram;

Planning a wiring path of a bus by using a heuristic search algorithm based on wiring density based on the wiring density map; then, determining a re-wiring sequence and a re-wiring area of the wire mesh with larger deviation according to the 2D deviation of the bus and the wiring density map, finding a path with smaller deviation for the wire mesh with larger deviation on the premise of ensuring that overflow is not increased, and then dynamically adjusting the wiring resources of the bus wire mesh group with larger deviation by using a local re-wiring model with dynamically adjusted wiring resources to obtain a wiring scheme with more balanced wire length;

Then, optimizing the wiring path again by using a multi-result tracking algorithm based on DFS for the wire network with larger deviation;

in the layer distribution stage, firstly, determining the priority of wiring according to a 2D wiring result, then, carrying out single-net layer distribution on each net according to the priority to obtain a preliminary layer distribution result, then, carrying out re-change on the layer distribution sequence according to a deviation value obtained by the preliminary layer distribution scheme to shorten the deviation, and then, carrying out layer adjustment optimization on a bus line net group with larger deviation to obtain a final 3D wiring scheme;

The local stitch removal and redistribution model through dynamic adjustment of wiring resources specifically adopts the following steps:

Step A1: sorting the bus wire net groups according to the wire length and the signal bit number, and selecting a wire net group with larger deviation value for disconnecting;

step A2: selecting a plurality of two-end wire nets with longer and shorter lengths from the bus wire net group with larger deviation value;

Step A3: removing the wire nets, and simultaneously carrying out wiring on the shortest wire net for multiple times to obtain a wiring path with proper wire length;

step A4: then wiring the rest wire nets;

wherein, the judgment of the length, the short, the deviation and the suitability of the wire network is adjusted and determined according to experience;

The multi-result tracking algorithm based on DFS specifically adopts the following steps:

Step B1: selecting a bus line network group with larger bus deviation, and removing all the line networks passing through the area;

Step B2: searching N wiring schemes for one two-end wire net by using a DFS algorithm;

Step B3: after a plurality of wiring schemes of one wire net are obtained, sequentially traversing each wiring scheme to carry out subsequent wiring, and the like to obtain a plurality of final wiring results;

step B4: and selecting the most suitable wiring scheme from the obtained multiple wiring results.

Further, the method for generating the wiring density map specifically includes: firstly, projecting pin information of a plurality of nets onto a 2D plane in a 2D wiring stage; then, constructing a topology structure by using a FLUTE algorithm for each net; and generating an initial wiring result through L-shaped wiring according to the topological structure of the wire net, and finally constructing a wiring density chart according to the weighted record of the area through which the wiring passes.

Further, based on the wiring density map, using a heuristic search algorithm based on wiring density, the wiring path of the planned bus is specifically: after the complete wiring density diagram is constructed, initial wiring is carried out, and heuristic functions of A-type algorithm are introduced to evaluate nodes of path searching.

Further, in step B3, only a part of the nets are selected for backtracking.

Further, in the layer allocation stage, for each net, an initial layer allocation scheme is obtained according to the state of the current wiring resource; after the 3D wiring deviation of the wire network can be obtained after the initial layer distribution scheme is obtained, the bus deviation is optimized by re-distributing the bus wire network with serious time disorder, and the detailed steps are as follows:

step C1: all nets are removed;

step C2: the layer allocation sequence of the net is redetermined for the 3D deviation obtained by the last layer allocation to replace D (N _i) in the following formula;

the net priority Q (N _i) is calculated as follows:

wherein, each net N _i E N, alpha and beta are custom coefficients; p (N _i) is the pin count of N _i; l (N _i) is the 2D net length of N _i; b (N _i) is the number of inflection points of N _i; d (N _i) is the bus skew of net N _i, and if not, 0; bit is the number of signals of the net N _i, and if not, 0;

Step C3: after determining the layer allocation sequence, firstly obtaining a plurality of feasible layer allocation schemes for the first bus line network group through a DFS algorithm, then simultaneously carrying out layer allocation for the second line network group on a plurality of results, and the like to finally obtain a plurality of layer allocation schemes;

Step C4: after a plurality of layer allocation schemes are obtained, calculating the deviation and the line length of each layer allocation scheme;

step C5: and selecting an optimal layer allocation scheme with small 3D deviation and little increase of line length.

Further, step C3 is performed by selecting only the bus net with smaller signal bits and larger deviation value.

An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements a multi-layer global routing method taking bus awareness into account as described above when executing the program.

A computer readable storage medium having stored thereon a computer program, characterized in that the program when executed by a processor implements a multi-layer global routing method taking bus awareness into account as described above.

Compared with the prior art, the invention and the preferred scheme thereof comprise the following key strategies: 1) By introducing a wiring density chart, a wiring model for controlling bus wiring through wiring density is designed, and the wiring rate of a non-bus and the deviation value of the bus can be considered at the same time; 2) The optimization of bus deviation is completed by dynamically adjusting a local disconnecting and re-distributing model of wiring resources, so that bus time delay is effectively reduced; 3) Designing a DFS-based multi-result tracking algorithm to obtain a plurality of wiring schemes; 4) A layer allocation algorithm based on bias perception is designed to significantly reduce bus bias of a 3D wiring scheme. A global wiring scheme with small bus skew and high quality can be obtained.

Drawings

Fig. 1 is a schematic diagram of a bus wiring flow.

Fig. 2 is a global routing grid diagram.

FIG. 3 is a schematic diagram of a bus wiring model.

Fig. 4 is a schematic flow chart of an algorithm according to an embodiment of the invention.

FIG. 5 is a graph of wiring density constructed in accordance with an embodiment of the present invention, wherein: (a) initial net (b) builds a topology (c) L-type wiring (d) wiring density map.

FIG. 6 is a schematic diagram of bus routing path selection according to an embodiment of the present invention.

Fig. 7 is a schematic diagram illustrating a local adjustment of a bus routing path according to an embodiment of the present invention.

Fig. 8 is a schematic diagram of a layer allocation flow according to an embodiment of the present invention, in which (a) a 2D wiring scheme (b) a directed tree (c) a wiring pin sequence (D) e1 is allocated to a metal layer 1 (3) e1 is allocated to a metal layer 3.

Fig. 9 shows a layer allocation scheme 1 (c) and a layer allocation scheme 2 (D) and a layer allocation scheme 3 according to various embodiments of the present invention.

Detailed Description

In order to make the features and advantages of the present patent more comprehensible, embodiments accompanied with figures are described in detail below:

It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.

As shown in fig. 1 to 9, in view of the improvement of the prior art, the general scheme of the multi-layer global routing method considering bus perception provided in this embodiment includes the following:

1. bus wiring flow:

In the physical design wiring stage of the very large scale integrated circuit, the wiring area of the chip is distributed in a plurality of metal layers, each layer is generally divided into a plurality of rectangles with the same size by the overall wiring, the 2D wiring stage is to wire-mesh the wiring resources and the non-buses of the layers and the buses on the 2D plane, then complete the wiring on the 2D plane to obtain an initial 2D wiring result, as shown in fig. 1 (b), a 2D wiring scheme of one bus can be obtained, but due to limited wiring resources, if the allocation of the wiring resources of the buses and the non-buses cannot be balanced and the excessive single wiring mode can lead to overlong wire length or excessively poor bus time sequence of the 2D wiring scheme, so that the quality of the 3D wiring scheme obtained by the allocation of the subsequent layers is too low. Thus, a study of the routing algorithm that considers bus timing during the 2D routing phase is worth exploring.

The layer distribution stage distributes all sides of the 2D wiring scheme to the appropriate metal layers according to the specific wiring directions specified by the different metal layers, and the final wiring result of fig. 1 (c) can be obtained by performing layer distribution by the 2D wiring scheme of fig. 1 (b), wherein the dotted lines represent through holes, namely wires of different layers are connected, but the excessive number of through holes can cause timing disorder, so that the problems of excessive number of through holes, excessive 3D deviation and the like of the final result can be caused if only the layer distribution mode of 3D wire length is considered and the wiring sequence selection of non-bus and bus is not distinguished.

2. Global wiring process:

An example of global routing is represented by defining a grid graph g= (V, E), dividing a multi-layer routing area containing obstacles into rectangles of equal size as shown in fig. 2, defining them as routing cells G-cells, where each vertex V E V represents a routing cell G-cell in the grid, and there are pins and obstacles in each routing cell, where for each E represents a common boundary of two adjacent G-cells. There is a capacity c _e for each edge E to represent the routable number of the common boundary. While given a net set n= { N ₁,N₂,…,N_m } for non-buses, there is a set of pin sets p= { P ₁,p₂,…,p_k } for each net.

3. Bus deviation calculation:

the present embodiment introduces bus nets into wiring nets based on a conventional global wiring model. For a bus, a bus pin set is represented by a combination of pins, having p bus pin sets and r pins per pin set, as in one example shown in FIG. 3, having 3 bus pin sets, each pin set containing 4 pins, the pins of the same signal bit in each pin set requiring interconnection.

When the lengths WL of the pin interconnections between the two bus pin groups are inconsistent, signal transmission time is inconsistent, and a bus skew D _n is generated. In addition, the calculation modes of WL and D _n due to the different wiring phases can be divided into a 2D phase and a 3D phase as follows:

Wherein the method comprises the steps of A routing path of the jth signal bit from the source pin group to the ith sink pin group is represented, E represents edges crossing two adjacent G-cells in the path, and E _cost represents the routing cost of each edge; v _cost represents the via cost, e εe ^z represents whether the edge is overcoated.

Wherein the method comprises the steps ofRepresenting the wiring cost of the source pin set to the path with the largest wiring cost in the ith sink pin set, p-1 representing the sink pin set, and r representing the number of signal bits.

The main objective of the present invention is to simultaneously consider the minimization of the total bus deviation (TD) and the realization of higher distributability in the wiring process of the bus network and the non-bus network. The calculation mode of TD is as follows:

Where n is the number of buses.

4. The whole flow is described:

In the overall flow of the algorithm of this embodiment, as shown in fig. 4, in the 2D wiring stage, the wiring information is compressed onto the 2D wiring plane, a topology structure is generated for all the nets by the FLUTE algorithm, and thus, the non-bus is first routed in a simple L-shape, so as to obtain a wiring density map. The heuristic search algorithm based on the wiring density is used for effectively planning the wiring path of the bus, and the number of buses is far lower than that of non-buses, so that the wire length only slightly increases; and then, determining a re-wiring sequence and a re-wiring area according to the 2D deviation and the wiring density diagram of the bus, finding a path with smaller deviation for a wire net with larger deviation on the premise of ensuring that overflow is not increased, then dynamically adjusting the wiring resources of the bus wire net group with larger deviation by using a local re-wiring model with dynamic adjustment of the wiring resources to obtain a wiring scheme with more balanced wire length, and then optimizing the wiring path again for the wire net with larger deviation by using a multi-result tracking algorithm based on DFS so as to better promote wiring quality. In the layer distribution stage, firstly, the priority of the wiring is determined according to the 2D wiring result, then, single net layer distribution is carried out on each net according to the priority to obtain a preliminary layer distribution result, then, the layer distribution sequence is changed again according to the deviation value obtained by the preliminary layer distribution scheme so as to shorten the deviation, and then, the final result of layer adjustment and optimization is carried out on the bus line net group with larger deviation to obtain the final 3D wiring scheme.

5. Algorithm overview:

(1) Wiring density map

In the whole global wiring process, the result of the initial wiring determines the quality of the wiring and the required CPU time, and the initial topology of the wiring net deviates from the initial 2D. Therefore, in consideration of factors such as bus 2D deviation and bus length, the present embodiment proposes a bus routing algorithm that considers non-bus routing density, and uses the routing density to guide bus routing in the initial routing stage, so that the bus deviation of subsequent wire-stripping and rewinding can be effectively reduced, and the number of bus wires is far less than that of non-bus wires, so that the length of wires is not greatly increased.

In the implementation, as shown in fig. 5 (a), the pin information of multiple nets is first projected onto the 2D plane in the 2D wiring stage, and two groups of pins in fig. 5 (a) represent two groups of nets, respectively; then, constructing a topology as shown in fig. 5 (b) using a FLUTE algorithm for each net; then generating an initial wiring result as shown in fig. 5 (c) through the L-shaped wiring according to the topological structure of the wire net, wherein two line segments connected with two pins represent two possibilities of the L-shaped wiring, and finally constructing a wiring density chart according to the weighted record of the area where the wiring passes, as shown in fig. 5 (d), the priority of the area where the wiring passes twice in the subsequent wiring is greatly reduced, so that the subsequent bus wiring is ensured not to overflow excessively.

After the complete wiring density diagram is constructed, initial wiring is performed and heuristic functions of an A-algorithm are introduced to evaluate nodes of path searching, as shown in fig. 6, before bus initial wiring is only L-shaped wiring, wherein a plurality of overlapped wiring areas are passed, so that a large amount of overflow is generated after initial wiring, and a large amount of resources are wasted after subsequent disconnecting and re-laying, so that after the complete wiring density diagram is constructed, the original bus initial wiring is guided according to the instruction wiring, as shown in fig. 5, the original bus initial wiring is passed through the plurality of overlapped areas, and part of the increase of the wiring length is brought after the initial wiring is re-planned through the wiring density diagram, but the disconnecting and re-laying difficulty and the bus deviation are greatly reduced in the subsequent disconnecting and re-laying.

(2) Local stitch removal re-arrangement for dynamically adjusting wiring resources

After finding that the bias will be affected by the line difference between the longest net and the shortest net in a set of buses, an attempt is made to shorten the length of the longest net, but it is found that since the wiring sequence is later, it is difficult to preferentially shorten the length of the wiring resources alone and the effect is poor, so this embodiment considers the redistribution of the resources, and achieves the purpose of simultaneously shortening the longest bus net and lengthening the shortest net. The local adjustment steps of the wire mesh are as follows:

step 1: the bus line net groups are ordered according to the line length and the signal bit number, and the net group with larger deviation value is selected for disconnecting.

Step 2: and selecting a plurality of two-end wire nets with longer and shorter wire nets from the bus wire net group with larger deviation value.

Step 3: the nets are removed and the shortest net is routed multiple times to obtain a routing path with proper wire length.

Step 4: the remaining nets are then routed.

Because the shortest wiring path can vacate a plurality of key wiring resources after selecting other wiring lines, the wiring of other signal bits can generate chain reaction with probability, and the wire length of other wiring lines is reduced so as to achieve the purpose of optimizing deviation.

Taking fig. 7 as an example to illustrate local adjustment of nets, wherein the numbers in the diagram represent the number of nets that can pass, as shown in the left diagram of fig. 7, the original wiring result of the bus is that after the net of the signal bit No. 3 passes through due to limited wiring resources, the nets of the rest signal bits all need to bypass to reach the destination, so that the deviation generated by the net is larger, and the original deviation of the bus line group is (5-3) + (5-3) + (11-3) =12 after the net is brought into a deviation calculation formula; after the wiring of the signal bit No. 3 is rearranged, it is found that the signal bit No. 1 has other wiring modes than before, as shown in the right diagram of fig. 7. Changing its routing path, then, due to the absence of its critical routing resource, the subsequent routing will have a shorter routing path selection, and finally, the result of the right graph of fig. 7 is changed, where the deviation value is (5-5) + (5-5) + (9-5) =4; indicating that the wiring deviation value can be greatly reduced as compared with the previous one.

(3) Multi-result tracking algorithm based on DFS

The characteristics that can result in multiple routing results from the DFS algorithm are followed by path optimization steps that take into account the length matching of the wire lengths as follows:

Step 1: firstly, selecting a bus line network group with larger bus deviation, and removing all the line networks passing through the area;

step 2: the DFS algorithm is used for searching N routing schemes for a two-terminal net, and the DFS can explore each branch as much as possible without wrapping around before backtracking, and multiple solutions can be found through backtracking after accessing the target node.

Step 3: after a plurality of wiring schemes of one wire net are obtained, each wiring scheme is traversed in sequence to carry out subsequent wiring, and the like, a plurality of final wiring results can be obtained, and because the time complexity of the algorithm is higher, only part of wire nets are generally selected to carry out backtracking traversal.

Step 4: and selecting the most proper wiring scheme from a plurality of wiring results.

In this embodiment, the determination of the length, bias and suitability of the net can be empirically adjusted and determined.

The pseudo code of the DFS routing algorithm is shown in the following table:

(4) Layer allocation algorithm based on deviation perception

After the 2D routing result is obtained, each side of each net of the 2D routing result needs to be assigned to a different layer, as shown in fig. 5, the undirected graph of the 2D routing scheme shown in fig. 8a is first converted into the directed tree shown in fig. 8b and the root and leaf nodes of the tree of fig. 8c are determined, and finally e1 is considered to be assigned to metal layer 1 or metal layer 3 as shown in fig. 8D and 8 e.

For the single ply allocation algorithm used in the algorithm of this embodiment, a good quality ply allocation sequence can maximally utilize the routing resources, and finally, an optimal routing scheme is obtained. The priority of different nets 2D line length, pin number, inflection point number of wiring results, 2D deviation and other influencing factors are comprehensively calculated, and the higher the priority of the net is, so that a high-quality layer distribution wiring scheme is obtained.

When the line length of the wire net is longer, more resources are consumed for layer allocation, if the wiring is performed earlier, the layer allocation cannot be completed for part of the wire net, so that the number of through holes is more, and the priority is lower as the line length is longer; secondly, if the number of inflection points of the wire net is too large, the number of through holes is larger, and the occupied wiring resources are increased, so that the priority of the larger number of the wire net is required to be lowered along with the lowering; if the net is a bus, and its bias the priority of the net requires a relative raise; different bus nets have different numbers of signals, if the length of a net with a certain signal bit is too long, the more the signal bits are, the larger the deviation value is, and the more the number of signals is, the higher the priority is.

The priority Q (N _i) is calculated as follows:

Wherein, each net N _i E N, alpha and beta are self-defined coefficients; p (N _i) is the pin count of N _i; l (N _i) is the 2D net length of N _i; b (N _i) is the number of inflection points of N _i; d (N _i) is the bus skew of net N _i (0 if not the bus); bit is the number of signals of net N _i (0 if not the bus).

For each wire net, an initial layer allocation scheme is obtained according to the state of the current wiring resource; after the 3D wiring deviation of the wire network can be obtained after the initial layer distribution scheme is obtained, the optimization of the bus deviation is realized through the re-layer distribution of the bus wire network with serious time disorder. The detailed steps are as follows:

Step 1: all nets were removed. The purpose of all nets is to be removed because it is found in the routing process that better layer distribution results can be obtained by re-distributing the layers after re-adjusting the layer distribution order according to the 3D routing bias.

Step 2: to optimize the bus bias, the 3D bias obtained by the last layer assignment in this algorithm replaces D (N _i) in equation 7 to re-determine the layer assignment order of the net;

Step 3: since the DFS algorithm is generally used for finding all solutions, the space efficiency is high, after determining the layer allocation sequence, a plurality of feasible layer allocation schemes are obtained for the first bus network group through the DFS algorithm, then layer allocation for the second network group is simultaneously performed for a plurality of results, and a plurality of layer allocation schemes can be finally obtained by analogy.

Step 4: after a plurality of layer allocation schemes are obtained, calculating the deviation and the line length of each layer allocation scheme;

step 5: and selecting an optimal layer allocation scheme with small 3D deviation and little increase of line length.

As shown in fig. 9, a 2D routing scheme of this embodiment may obtain a plurality of layer allocation algorithms, although a partial layer allocation scheme may have poor results in the net, but may be capable of bringing huge routing profits in the performance of subsequent routing, but because of its need to traverse all feasible schemes, the routing complexity is huge, in this embodiment, more routing schemes may be obtained after selecting the best 3 schemes among the plurality of routing schemes to perform the next traversal for multiple times, selecting the better routing results therefrom, and the selected evaluation criteria are mainly the deviation, and the 3D wire length is auxiliary.

The program design scheme of the algorithm related to the embodiment can be stored in a computer readable storage medium in a coded form, and implemented in a computer program mode, and basic parameter information required by calculation is input through computer hardware, and a calculation result is output.

It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations of methods, apparatus (means), and computer program products according to embodiments of the invention. It will be understood that each flow of the flowchart, and combinations of flows in the flowchart, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the invention in any way, and any person skilled in the art may make modifications or alterations to the disclosed technical content to the equivalent embodiments. However, any simple modification, equivalent variation and variation of the above embodiments according to the technical substance of the present invention still fall within the protection scope of the technical solution of the present invention.

The present patent is not limited to the above-mentioned preferred embodiments, and any person can obtain other various types of multi-layer global wiring methods considering bus perception under the teaching of the present patent, and all equivalent changes and modifications made according to the claims of the present application shall be covered by the present patent.

Claims

1. A multi-layer global wiring method considering bus perception is characterized in that: in the 2D wiring stage, firstly, wiring information is compressed onto a 2D wiring plane, a topological structure is generated for all wires by a FLUTE algorithm, and non-buses are subjected to L-type wiring so as to obtain a wiring density diagram;

step A4: then wiring the rest wire nets;

wherein, the length, the deviation and the suitability of the wire net are experience parameters;

2. The bus aware multilayer global routing method of claim 1, wherein:

The wiring density map generation method specifically comprises the following steps: firstly, projecting pin information of a plurality of nets onto a 2D plane in a 2D wiring stage; then, constructing a topology structure by using a FLUTE algorithm for each net; and generating an initial wiring result through L-shaped wiring according to the topological structure of the wire net, and finally constructing a wiring density chart according to the weighted record of the area through which the wiring passes.

3. The bus aware multilayer global routing method of claim 1, wherein: based on the wiring density diagram, a heuristic search algorithm based on wiring density is used, and the wiring path of the planning bus is specifically: after the complete wiring density diagram is constructed, initial wiring is carried out, and heuristic functions of A-type algorithm are introduced to evaluate nodes of path searching.

4. The bus aware multilayer global routing method of claim 1, wherein: in step B3, only a part of nets are selected for backtracking traversal.

5. The bus aware multilayer global routing method of claim 1, wherein: in the layer allocation stage, for each wire net, an initial layer allocation scheme is obtained according to the state of the current wiring resource; after the initial layer distribution scheme is obtained to obtain the 3D wiring deviation of the wire net, the bus deviation is optimized by re-distributing the bus wire net with more serious timing disorder, and the detailed steps are as follows:

step C1: all nets are removed;

the net priority Q (N _i) is calculated as follows:

6. The bus aware multilayer global routing method of claim 5, wherein: and C3, only selecting a bus network with fewer signal bits and larger deviation value to execute the step C3.

7. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the bus aware multi-layer global routing method of any of claims 1-6 when the program is executed.

8. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the bus aware multi-layer global routing method according to any of claims 1-6.