CN117875254A - Layer allocation method considering bus topology structure - Google Patents

Abstract

The invention provides a layer distribution method considering a bus topology structure, which fully considers the problem of bus topology consistency in the layer distribution stage and provides a high-efficiency layer distribution method considering the bus topology structure, wherein the method is based on the following 3 strategies: 1) In the initial layer distribution stage, a wiring strategy for dynamically adjusting the layer distribution sequence is provided; 2) A layer allocation strategy based on bus signal bits; 3) A layer exchange strategy based on space utilization. The invention can obviously reduce bus topology deviation, thereby obtaining a high-quality layer distribution result.

Description

Layer allocation method considering bus topology structure

Technical Field

The invention belongs to the technical field of layer distribution in integrated circuit computer aided design and very large scale integrated circuits, and particularly relates to a layer distribution method considering a bus topological structure.

Background

In the current integrated circuit technology, the industrial application of the multilayer wiring technology is very wide, the number of wiring layers is gradually increased, and the intermediate link between global wiring and detailed wiring, namely layer allocation, becomes the focus of attention. In order to improve the resource utilization efficiency of large-scale multi-layer wiring in a chip, how to determine the final placement level of a wire net in the wiring process and properly connect wiring layers is a problem that must be considered in the layer allocation stage. In the 2.5D global routing process, the 2D routing scheme cannot provide complete guidance for detailed routing, each wire of the 2D routing scheme needs to be distributed to metal layers in the 3D routing structure diagram, and each metal layer can be interconnected through a through hole in the G-cell, so that the 2D routing scheme is converted into the 3D routing scheme. If the wiring paths cannot be reasonably distributed on the metal layer, the wiring indexes such as time delay, power consumption crosstalk and the like of the circuit are affected.

As chip fabrication processes enter the nanoscale, the number of wiring elements in a chip is increasing, and the proportion of transmission buses in the net is increasing. The buses play a role in connecting signal transmission of different functional modules in the chip, and due to complexity of signals, a plurality of buses are often required for signal transmission, meanwhile, transmitted information is often required to be formed by the signals transmitted by the buses together, and if the time of the signals reaching a destination is inconsistent, information errors can be caused. The measured arrival time is typically measured in terms of wire length. In the algorithmic study of buses, one key indicator for evaluating bus performance is timing matching of the bus. By requiring all signal bits forming the bus to have wire nets with similar lengths, signals transmitted by different wire nets in the bus are ensured to reach target positions in similar time, and the timing sequence is ensured not to be disordered.

The bus is used for transmitting control signals or data to corresponding functional modules in parallel, and the modern process technology can integrate hundreds of millions of components into a chip, so that the density of the bus is extremely high while the chip has more functions. Therefore, the method has significance in considering how to perform effective unified processing on the bus deviation in the layer distribution stage, and effectively reducing the probability of disordered chip time sequence, reduced turn-on rate and overlarge power consumption caused by overlarge bus deviation and better meeting design requirements.

In chips, the automatic routing algorithm of the bus usually focuses on the routing efficiency, but at the same time, there are problems of routing efficiency, signal integrity, electromagnetic interference, and the like. In the layer distribution process of the VLSI, the wiring of two adjacent layers are mutually perpendicular, interlayer coupling and interference can be reduced, and the condition that wires on the same wiring layer do not overflow is met, so that the occurrence of electromagnetic interference phenomenon in the bus wiring process can be reduced.

Disclosure of Invention

The invention relates to the construction of an overall wiring method in a very large scale integrated circuit in the technical field of integrated circuit computer aided design. With the high-speed development of the integrated circuit industry, the magnitude of components which can be accommodated by a chip is larger, the duty ratio of buses in a wire network is gradually increased, the quality degree of bus wiring directly influences the performances of time sequence matching, the wiring rate and the like of the chip, and in addition, the coupling effect between adjacent layers greatly influences the performance of the chip. In the current wiring design of multiple wiring layers, the bus topology structure is judged and optimized in the layer distribution stage, so that interlayer coupling and interference can be reduced better, and the chip performance is improved. Therefore, the invention fully considers the bus topology consistency problem in the layer allocation stage, and provides a high-efficiency layer allocation method considering the bus topology structure, which is based on the following 3 strategies: 1) In the initial layer distribution stage, a wiring strategy for dynamically adjusting the layer distribution sequence is provided; 2) A layer allocation strategy based on bus signal bits; 3) A layer exchange strategy based on space utilization. The invention can obviously reduce bus topology deviation, thereby obtaining a high-quality layer distribution result.

The technical scheme adopted for solving the technical problems is as follows:

a layer allocation method considering bus topology, characterized in that:

in the initial layer distribution stage, firstly, obtaining a bus 2D topology deviation by utilizing a 2D wiring scheme provided in a 2D wiring stage to determine an initial layer distribution sequence, then, fully arranging the layer distribution scheme of each net by a backtracking method to obtain an initial 3D wiring scheme, and re-determining the layer distribution sequence based on the initial 3D wiring scheme to perform disconnection re-distribution until the final wiring scheme meets the expected 3D topology deviation, and then, performing layer exchange;

in the layer exchange stage, dividing wire mesh pairs needing layer exchange according to the obtained 3D wiring layer distribution scheme;

considering the use of each metal layer space and the number of signal bits of the bus, using a layer exchange strategy based on space utilization, the available wiring space is further improved for the characteristics of the same layer of wires of the same topology of the bus, so as to further improve the layer allocation quality, and finally, an optimal layer allocation scheme is obtained.

Further, in the initial layer allocation phase, a 3D global wiring diagram G with z-layer metal layers is given ^z ＝(V ^z ,E ^z ) 2D wiring scheme set path= (Path ¹ ,Path ² ,…,Path ^p ) One bus wire net group set b= { B ₁ ,b ₂ ,…,b _n A set of non-bus nets n= { N } ₁ ,N ₂ ,…,N _m For each non-bus net, there is a set of pins p= { P ₁ ,P ₂ ,…,P _k If the bus line net group is given a group of bus pin groups bp= { BP } ₀ ,BP ₁ ,…,BP _r }, where BP is ₀ Defined as source pin group, BP _j Defined as a sink pin set; wiring capacity c= { C of each wiring layer ₁ ,C ₂ ,…,C _z Obstacle set o= { O } ₁ ,o ₂ ,…,o _i -a }; path is assembled according to the scheme of 2D wiring ¹ Is assigned to the corresponding layer of the wiring pattern G to obtain the final 3D wiring Path Path ^p The method comprises the steps of carrying out a first treatment on the surface of the The wiring edges of the same bus line network group have the same topology and are required to be on the same layer, and the standard is as follows:

wherein alpha and beta are constants, C _w Representing a bus line network group bus _i The ratio of the actual wire length to the theoretical shortest wire length of the wiring, # bits represents the bus of the bus line network group _i Number of bits of signal, C _s Representing a bus line network group bus _i The ratio of the actual number of segments to the theoretical shortest number of segments of the wiring, # segs represents the bus line network group bus _i Is the number of line segments; vias represents the number of vias in the routing path; the smaller the value of the above formula, the higher the topology consistency of its wiring scheme.

Further, the distribution sequence of the wire network layers is optimized by comprehensively considering the influence of different factors on the wire network so as to maximally utilize wiring resources, thereby obtaining an optimal wiring scheme; the higher priority net requires priority treatment to obtain a high quality layer distribution wiring scheme;

for each net, the priority is calculated by the following formula, and the layer allocation is firstly carried out on the net with high priority, and the calculation mode of the priority Q1 is as follows:

wherein,is net N _i If N _i Taking 0 for non-bus network, lambda is a custom parameter, PE (N _i ) Is N _i Pin distribution ranges of (a) are provided.

Further, an initial 3D routing scheme is obtained after initial layer allocation, and each wire metal layer is redistributed so as not to generate excessive wire length while optimizing bus deviation; the calculation method of the priority Q2 is as follows:

wherein each net N _i ∈N，Is net N _i If N _i Taking 0 for non-bus net and bit is net N _i If N _i For the non-bus network, 0 is taken, PE (N) _i ) Is N _i Pin distribution range of B (N) _i ) Is N _i Is the number of inflection points, α and β, are custom coefficients.

Further, in the layer distribution process, the buses and the non-buses are distinguished, and two layer selection strategies are set up, wherein the specific steps are as follows:

step A1: traversal N _i E N, sequentially for each net N according to layer allocation order _i Is decomposed into a plurality of edges e to be placed _i ；

Step A2: according to e _i If the bus is the side, selecting a wiring layer with the available capacity larger than the number of signal bits of the bus in the existing layer for the bus, and recording the wiring layer; if the side belongs to a non-bus wire network, considering the number of the through holes, and searching a layer distribution mode with the minimum number of the through holes by traversing each layer from bottom to top;

step A3: e is as follows _i The recorded layer is the starting point, if N _i ∈BN _i Then for the next edge e _i+1 Traversing the nearest metal layer in turn to find the wiring which can hold all signal bits of the bus, if N is not the bus, then making the next edge e _i+1 Searching a layer with the least number of through holes and no overflow, and recording the allocated layer;

step A4: if go to the last edge e _m Executing the next step; otherwise, turning to the step A2;

step A5: a final layer allocation scheme is constructed from the layers recorded on each side.

Further, the specific steps of the layer exchange strategy based on the space utilization rate are as follows:

step B1: selecting a bus line network group needing layer exchange according to the signal bit of the bus and the line network space utilization rate of the line segments of each group of buses calculated in the layer distribution process;

step B2: selecting a wiring line segment which cannot completely distribute all bus signal bits in the layer distribution process, and uniformly distributing the wiring line segments to the wire net of the same layer;

step B3: and removing the bus line network group with lower line network space utilization rate and the bus line network group with topology violations, and mutually exchanging the wiring layers where part of the wiring line segments are located.

Compared with the prior art, the bus topology consistency is improved by optimizing the layer allocation algorithm.

Drawings

The invention is described in further detail below with reference to the attached drawings and detailed description:

FIG. 1 is a diagram illustrating topology on layer allocation;

FIG. 2 is a diagram showing an example of a layer exchange process according to an embodiment of the present invention.

Detailed Description

In order to make the features and advantages of the present patent more comprehensible, embodiments accompanied with figures are described in detail below:

it should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.

The embodiment of the invention provides a layer allocation method considering a bus topology structure, aiming at improving the consistency of the bus topology structure by optimizing a layer allocation algorithm.

The method specifically comprises the following design processes:

1. in the initial layer distribution stage, firstly, a bus 2D topology deviation is obtained by utilizing a 2D wiring scheme provided in the 2D wiring stage to determine an initial layer distribution sequence, then, the layer distribution scheme of each net is fully arranged by a backtracking method to obtain an initial 3D wiring scheme, and the layer distribution sequence is redetermined on the basis to perform disconnection and redistribution until the final wiring scheme meets the expected 3D topology deviation, and then, layer exchange is performed.

2. In the layer exchange stage, wire mesh pairs requiring layer exchange are divided according to the 3D wiring layer distribution scheme obtained above.

Considering the use of each metal layer space and the number of signal bits of the bus, a layer exchange strategy based on space utilization rate is used, and the available wiring space is further improved according to the characteristics of wires with the same topology of the bus in the same layer, so that the layer allocation quality is further improved, and finally, an optimal layer allocation scheme is obtained.

1. Layer allocation process model:

the operation object of layer allocation is a 2D wiring scheme obtained in global wiring, the 2D wiring grid diagram shown in fig. 1 (a) is first expanded into a 3D wiring grid diagram of fig. 1 (b), and then each wire of fig. 1 (a) is allocated onto an appropriate metal layer. Since the 2D global routing algorithm takes the topology of the buses into account, the routing scheme for the 2D routing scheme will not change, and a 3D routing scheme can be obtained after each bus is allocated to a suitable layer, as shown in fig. 1 (c). However, insufficient wiring space is likely to occur during the wiring process, so that the same signal bit of the bus is not wired in the same layer, as shown in fig. 1 (d).

2. And (3) calculating a correlation standard:

given a 3D global wiring diagram G with z-layer metal layers ^z ＝(V ^z ,E ^z ) 2D wiring scheme set path= (Path ¹ ,Path ² ,…,Path ^p ) One bus wire net group set b= { B ₁ ,b ₂ ,…,b _n A set of non-bus nets n= { N } ₁ ,N ₂ ,…,N _m For each non-bus net, there is a set of pins p= { P ₁ ,P ₂ ,…,P _k If the bus line net group is given a group of bus pin groups bp= { BP } ₀ ,BP ₁ ,…,BP _r }, where BP is ₀ Defined as source pin group, BP _j Defined as a collection of pins. Wiring capacity c= { C of each wiring layer ₁ ,C ₂ ,…,C _z Obstacle set o= { O } ₁ ,o ₂ ,…,o _i }. Path is assembled according to the scheme of 2D wiring ¹ Is assigned to the corresponding layer of the wiring pattern G to obtain the final 3D wiring Path Path ^p . Wherein the need for the same topology in the routing edges of the same bus-line network group is on the same layer as shown in fig. 1 (c). The criteria are as follows:

wherein alpha and beta are constants, C _w Representing a bus line network group bus _i The ratio of the actual wire length to the theoretical shortest wire length of the wiring, # bits represents the bus of the bus line network group _i Number of bits of signal, C _s Representing a bus line network group bus _i The ratio of the actual number of segments to the theoretical shortest number of segments of the wiring, # segs represents the bus line network group bus _i Is a number of line segments of the pattern. vias represents the number of vias in the routing path. The smaller the value of the above formula, the higher the topology consistency of its wiring scheme.

(1) Priority order

By comprehensively considering the influence of different factors on the wire network, the distribution sequence of the wire network layer is optimized, so that the wiring resources can be utilized to the maximum extent, and the optimal wiring scheme is obtained. The priority of a net is related to factors such as its 2D line length, pin count, inflection point count, and 2D topology bias, and the higher the priority the more the net needs to be prioritized to obtain a high quality layer distribution wiring scheme.

In terms of layer allocation algorithm, the corresponding 2D wiring scheme is not changed, so that it is necessary to consider the 2D wiring scheme of the net when considering the allocation sequence of layer allocation, and for this purpose, the priority of each net is calculated by the formula (4), and the layer allocation is performed on the net with high priority first, so that a better initial layer allocation scheme can be provided for the subsequent operation, and more time is saved for the subsequent adjustment calculation. The manner of calculation of the priority Q1 is as follows:

wherein,is net N _i 2D topology bias of (if N) _i 0 for non-bus net), λ is a custom parameter, PE (N) _i ) Is N _i Pin distribution ranges of (a) are provided.

Because the topology difference of the network with larger 2D topology deviation can be further enlarged if the network with larger 2D topology deviation is placed behind for distribution, the network with larger 2D topology deviation is preferentially distributed in layers to ensure sufficient layer distribution space. The larger the span of the wire mesh pins is, the more wiring space is needed, if the wire mesh pins are not preferentially routed, the number of through holes is greatly increased due to insufficient later space, bus topology deviation is generated, and the higher the span of the wire mesh pins is, the higher the priority is.

An initial 3D routing scheme can be obtained after an initial layer allocation. The method comprises the steps of 3D bus topology deviation of the number of through holes, 3D wiring line length and the like, and according to the information, reallocating each wire metal layer so as not to generate excessive line length while optimizing the bus deviation. The calculation method of the priority Q2 is as follows:

wherein each net N _i ∈N，Is net N _i 3D topology bias of (0 if not bus), bit is net N _i Signal number (0 if not bus), PE (N _i ) Is N _i Pin distribution range of B (N) _i ) Is N _i Is the number of inflection points, α and β, are custom coefficients.

3. Single network layer distribution method based on bus signal bits

The goal of the single net layer allocation method based on bus signal bits is to perform layer allocation to each individual net and get a result of low topology deviation. The basic idea of the algorithm is: in the layer distribution process, buses and non-buses are distinguished, two layer selection strategies are set, the topological consistency of the buses is kept as much as possible, and the number of through holes generated by non-bus networks in the layer distribution process is as small as possible.

The specific steps are as follows:

step 1: traversal N _i E N, sequentially for each net N according to layer allocation order _i Is decomposed into a plurality of edges e to be placed _i 。

Step 2: according to e _i If the bus is the side, selecting a wiring layer with the available capacity larger than the number of signal bits of the bus in the existing layers, and recording the wiring layer. If the edge belongs to a non-bus wire network, the number of the through holes of the edge needs to be considered, and a layer distribution mode with the minimum number of the through holes is searched by traversing each layer from bottom to top.

Step 3: e is as follows _i The recorded layer is the starting point, if N _i ∈BN _i Then for the next edge e _i+1 The nearest metal layer is traversed in sequence,searching wiring capable of accommodating all signal bits of the bus, if N is not the bus, then for the next edge e _i+1 Find the layer with the least number of vias and without overflow and record the assigned layer.

Step 4: if go to the last edge e _m Executing the next step; otherwise, turning to step 2.

Step 5: a final layer allocation scheme is constructed from the layers recorded on each side.

3. Layer exchange strategy based on space utilization

Each wire net in the layer distribution stage can be distributed separately and sequentially, and each wire line segment of each signal bit in the bus wire net group must be kept consistent as far as possible to perform cooperative wiring, so that the situation of low wiring space utilization is easy to occur. This situation may result in insufficient wiring space for the remaining buses, requiring splitting of bus signal bits, which further enlarges the topology bias. In the layer allocation stage, a layer exchange strategy under the view of bus space utilization is proposed, and topology deviations are optimized by exchanging all the layers of the two bus wire network groups. The main idea of the strategy is: the utilization rate of the wiring line segments of each group of buses to the metal layer is obtained through calculation, a bus line network group with lower utilization rate and a bus line network group with topology violations caused by insufficient wiring resources are selected, and layers of partial line segments are exchanged, so that the bus topology structure consistency under 3D is ensured while the wiring utilization rate is improved.

The specific steps of the layer exchange strategy based on the space utilization rate are as follows:

step 1: and selecting the bus line network group needing layer exchange according to the signal bit of the bus and the line network space utilization rate of the line segments of each group of buses calculated in the layer distribution process. As shown in the left 3D wiring structure diagram of fig. 2, when the layer allocation is performed on the bus of 16-bit signal bits, the wiring capacity of one layer is found to be far greater than 16 bits, but the layer allocation process allocates the layer to the metal layer with sufficient space because the process is sequential and the subsequent congestion distribution situation cannot be predicted.

Step 2: in the layer distribution process, selecting wire segments which cannot completely distribute all bus signal bits to the wire net of the same layer. As shown in the left 3D wiring structure diagram of fig. 2, when a 32-bit bus is laid out, it is found that the wiring capacity of one layer is less than 32 bits, so that part of signal bits are distributed to other layers, which results in a topology violation being generated in part and the bus topology consistency is reduced.

Step 3: the bus line network group with lower space utilization rate of the wire network and the bus line network group with topology violations are removed, and the two parties exchange the wiring layers of partial wiring line segments mutually, as shown in a right 3D wiring structure diagram of fig. 2, under the condition that the number of partial through holes is sacrificed, the wiring layers of the rest wiring line segments are not changed, so that the topology consistency of the two bus line network groups is ensured, and meanwhile, the original topology deviation is reduced.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the invention in any way, and any person skilled in the art may make modifications or alterations to the disclosed technical content to the equivalent embodiments. However, any simple modification, equivalent variation and variation of the above embodiments according to the technical substance of the present invention still fall within the protection scope of the technical solution of the present invention.

The present invention is not limited to the above-mentioned preferred embodiments, and any person who can obtain other layer allocation methods considering bus topology under the teaching of the present invention shall fall within the scope of the present invention.

Claims (6)

1. A layer allocation method considering bus topology, characterized in that:

in the initial layer distribution stage, firstly, obtaining a bus 2D topology deviation by utilizing a 2D wiring scheme provided in a 2D wiring stage to determine an initial layer distribution sequence, then, fully arranging the layer distribution scheme of each net by a backtracking method to obtain an initial 3D wiring scheme, and re-determining the layer distribution sequence based on the initial 3D wiring scheme to perform disconnection re-distribution until the final wiring scheme meets the expected 3D topology deviation, and then, performing layer exchange;

in the layer exchange stage, dividing wire mesh pairs needing layer exchange according to the obtained 3D wiring layer distribution scheme;

considering the use of each metal layer space and the number of signal bits of the bus, using a layer exchange strategy based on space utilization, the available wiring space is further improved for the characteristics of the same layer of wires of the same topology of the bus, so as to further improve the layer allocation quality, and finally, an optimal layer allocation scheme is obtained.

2. The layer allocation method considering bus topology according to claim 1, wherein:

in the initial layer allocation phase, a 3D global wiring diagram G with z-layer metal layers is given ^z ＝(V ^z ,E ^z ) 2D wiring scheme set path= (Path ¹ ,Path ² ,…,Path ^p ) One bus wire net group set b= { B ₁ ,b ₂ ,…,b _n A set of non-bus nets n= { N } ₁ ,N ₂ ,…,N _m For each non-bus net, there is a set of pins p= { P ₁ ,P ₂ ,…,P _k If the bus line net group is given a group of bus pin groups bp= { BP } ₀ ,BP ₁ ,…,BP _r }, where BP is ₀ Defined as source pin group, BP _j Defined as a sink pin set; wiring capacity c= { C of each wiring layer ₁ ,C ₂ ,…,C _z Obstacle set o= { O } ₁ ,o ₂ ,…,o _i -a }; path is assembled according to the scheme of 2D wiring ¹ Is assigned to the corresponding layer of the wiring pattern G to obtain the final 3D wiring Path Path ^p The method comprises the steps of carrying out a first treatment on the surface of the The wiring edges of the same bus line network group have the same topology and are required to be on the same layer, and the standard is as follows:

wherein alpha and beta are constants, C _w Representing a bus line network group bus _i The ratio of the actual wire length to the theoretical shortest wire length of the wiring, # bits represents the bus of the bus line network group _i Number of bits of signal, C _s Representing a bus line network group bus _i The ratio of the actual number of segments to the theoretical shortest number of segments of the wiring, # segs represents the bus line network group bus _i Is the number of line segments; vias represents the number of vias in the routing path; the smaller the value of the above formula, the higher the topology consistency of its wiring scheme.

3. The layer allocation method considering the bus topology according to claim 2, wherein:

optimizing the distribution sequence of the wire network layers by comprehensively considering the influence of different factors on the wire network so as to maximize the utilization of wiring resources, thereby obtaining an optimal wiring scheme; the higher priority net requires priority treatment to obtain a high quality layer distribution wiring scheme;

for each net, the priority is calculated by the following formula, and the layer allocation is firstly carried out on the net with high priority, and the calculation mode of the priority Q1 is as follows:

wherein,is net N _i If N _i Is a non-bus networkThen take 0, λ is the custom parameter, PE (N _i ) Is N _i Pin distribution ranges of (a) are provided.

4. A layer allocation method taking into account bus topology according to claim 3, wherein:

obtaining an initial 3D wiring scheme after initial layer allocation, and reallocating each wire metal layer so as not to generate excessive wire length while optimizing bus deviation; the calculation method of the priority Q2 is as follows:

wherein each net N _i ∈N，Is net N _i If N _i Taking 0 for non-bus net and bit is net N _i If N _i For the non-bus network, 0 is taken, PE (N) _i ) Is N _i Pin distribution range of B (N) _i ) Is N _i Is the number of inflection points, α and β, are custom coefficients.

5. The layer allocation method considering bus topology according to claim 1, wherein:

in the layer distribution process, buses and non-buses are distinguished, two layer selection strategies are established, and the specific steps are as follows:

step A1: traversal N _i E N, sequentially for each net N according to layer allocation order _i Is decomposed into a plurality of edges e to be placed _i ；

Step A2: according to e _i If the bus is the side, selecting a wiring layer with the available capacity larger than the number of signal bits of the bus in the existing layer for the bus, and recording the wiring layer; if the edge belongs to the non-bus network, the pass-through of the edge needs to be consideredThe number of holes is traversed from bottom to top, and a layer distribution mode with the minimum number of through holes is searched;

step A3: e is as follows _i The recorded layer is the starting point, if N _i ∈BN _i Then for the next edge e _i+1 Traversing the nearest metal layer in turn to find the wiring which can hold all signal bits of the bus, if N is not the bus, then making the next edge e _i+1 Searching a layer with the least number of through holes and no overflow, and recording the allocated layer;

step A4: if go to the last edge e _m Executing the next step; otherwise, turning to the step A2;

step A5: a final layer allocation scheme is constructed from the layers recorded on each side.

6. The layer allocation method considering bus topology according to claim 1, wherein:

the specific steps of the layer exchange strategy based on the space utilization rate are as follows:

step B1: selecting a bus line network group needing layer exchange according to the signal bit of the bus and the line network space utilization rate of the line segments of each group of buses calculated in the layer distribution process;

step B2: selecting a wiring line segment which cannot completely distribute all bus signal bits in the layer distribution process, and uniformly distributing the wiring line segments to the wire net of the same layer;

step B3: and removing the bus line network group with lower line network space utilization rate and the bus line network group with topology violations, and mutually exchanging the wiring layers where part of the wiring line segments are located.