CN1149651C - Semiconductor chip device and its package method - Google Patents
Semiconductor chip device and its package method Download PDFInfo
- Publication number
- CN1149651C CN1149651C CNB001341642A CN00134164A CN1149651C CN 1149651 C CN1149651 C CN 1149651C CN B001341642 A CNB001341642 A CN B001341642A CN 00134164 A CN00134164 A CN 00134164A CN 1149651 C CN1149651 C CN 1149651C
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- China
- Prior art keywords
- electric conductor
- conductive contact
- semiconductor chip
- film layer
- packing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a semiconductor chip device and an encapsulation method thereof. The encapsulation method comprises the following steps: a semiconductor chip has an installation surface provided with welding pads, and a conductive contact is formed on each welding pad; a sensitive thin-film layer is formed on the installation surface; a photo mask is utilized to carry out photo-etching processing in order to expose the conductive contacts; conductive bodies are formed on the sensitive thin-film layer by conductive glue, and each conductive body forms a contact connection part, an extending part and an electrical-connection part. The semiconductor chip device comprises the semiconductor chip, wherein the semiconductor chip has the installation surface provided with welding pads, and each welding pad has the conductive contact; the sensitive thin-film layer is arranged on the installation surface; each conductive body arranged on the thin-film layer has the contact connection part, the extending part and the electrical-connection part.
Description
The present invention is relevant for a kind of semiconductor device, particularly a kind of semiconductor chip device and method for packing thereof.
In No. 00105468.6 case of Chinese invention patent, addressed the weld pad technology of relevant semiconductor wafer surface, development along with semiconductor fabrication process, weld pad on the wafer surface becomes more and more littler, and the distance between weld pad is also dwindled gradually, become very difficult so that be electrically connected with external circuit, and then influence the qualification rate of producing, even influence the continuation development of semiconductor fabrication process.
The object of the present invention is to provide a kind of semiconductor chip device and method for packing thereof of being electrically connected with external circuit be convenient to.
For achieving the above object, the present invention takes following technical measures:
The method for packing of semiconductor chip device of the present invention, semiconductor chip device are suitable for being installed on the substrate with several weld pads, comprise the steps:
A semiconductor transistor elements is provided, and it has a pad installation surface that is provided with several weld pads, forms a conductive contact on each weld pad, and the position of weld pad does not correspond to the bond pad locations on the substrate;
On the pad installation surface of brilliant unit, form a photosensitive film layer;
Cover photosensitive film layer to one and be seated on the photosensitive film layer, and photosensitive film layer is carried out exposure-processed corresponding to conductive contact photomask partly;
After removing photomask, with chemical irrigating medium photosensitive film layer is removed by the flushing of at least a portion in the photomask cover part, so that conductive contact exposes;
Form electric conductor with conducting metal glue on photosensitive film layer, each electric conductor has a contact connecting portion that is electrically connected with corresponding conductive contact, one and the contact connecting portion is electrically connected and be positioned at the corresponding electrical connection section of corresponding bond pad locations on extension free end and its position and the substrate as the extension and of circuit trace.
Wherein, after the step that forms electric conductor, also comprise the steps:
On the electrical connection section of each electric conductor, form a connecting terminal.
Wherein, described connecting terminal is conduction tin ball.
Wherein, in the step that forms connecting terminal, conductive contact and electric conductor are one-body molded.
A kind of semiconductor chip device of the present invention, it is suitable for being installed on the substrate with several weld pads, comprising:
A semiconductor transistor elements, it has a pad installation surface that is provided with several weld pads and forms by the conductive contact on each weld pad, and the position of weld pad does not correspond to the bond pad locations of substrate;
A photosensitive film layer, it is formed on the pad installation surface of brilliant unit, and is formed with several in order to expose the exposed hole of corresponding conductive contact head portion at least corresponding to conductive contact;
Several are formed on the electric conductor on the photosensitive film layer, and each electric conductor has one and is electrically connected with the contact connecting portion with contact connecting portion, that corresponding conductive contact is electrically connected and is positioned at extension free end and its position bond pad locations corresponding electrical connection section corresponding with substrate as the extension and of circuit trace.
Reaching embodiment in conjunction with the accompanying drawings is described in detail as follows architectural feature of the present invention and method feature:
Fig. 1 to Fig. 5 is the flow chart of method for packing first embodiment of semiconductor chip device of the present invention;
Fig. 6 is the cutaway view of semiconductor chip device second embodiment of the present invention;
Fig. 7 to Fig. 8 is the flow chart of method for packing the 3rd embodiment of semiconductor chip device of the present invention;
Fig. 9 is the schematic diagram of semiconductor chip device the 4th embodiment of the present invention;
Figure 10 is the schematic diagram of semiconductor chip device the 5th embodiment of the present invention;
Figure 11 is the schematic diagram of semiconductor chip device the 6th embodiment of the present invention;
Semiconductor chip device of the present invention is suitable for being installed on the substrate (not shown).Substrate in this substrate and the existing patent is similar, and it has a wafer installation region, is provided with several solder joints in the wafer installation region.
Shown in Fig. 1-5, it is the flow chart of method for packing first embodiment of semiconductor chip device of the present invention; See also Fig. 1, a semiconductor transistor elements 1 at first is provided, have one on it and be provided with several weld pads 11 pad installation surface 10 of (only showing in graphic), the position of weld pad 11 does not correspond to the bond pad locations of substrate.Then, utilize prior art, on each weld pad 11, form one as the conductive contact 2 as the conductive metal balls.
As shown in Figure 2, a photosensitive film layer 3 is formed on the pad installation surface 10 of brilliant unit 1, and then, as shown in Figure 3, a photomask 4 corresponding to conductive contact 2 parts that covers photosensitive film layer 3 is seated on the photosensitive film layer 3.Then, photosensitive film layer 3 is carried out exposure-processed so that the part that is not covered by photomask 4 on the photosensitive film layer 3 can be solidified.
See also shown in Figure 4ly, the existing optical lithography of the part utilization that photosensitive film layer 3 is covered by photomask 4 is removed, so that forms the exposed hole 30 that exposes corresponding conductive contact 2.
As shown in Figure 5, with conducting metal glue, on photosensitive film layer 3, form electric conductor 5.In the present embodiment, conducting metal glue can be a kind of conducting metal glue that is doped with in gold, silver, copper, iron, tin and aluminium or the like the conductive metallic material.Each electric conductor 5 has that a contact connecting portion that is electrically connected with corresponding conductive contact 2 500, one are electrically connected with contact connecting portion 500 and is positioned at extension 501 free ends and its position bond pad locations corresponding electrical connection section 502 corresponding with substrate as the extension 501 of circuit trace and one.Thereafter, electric conductor 5 is dried processing via heating and is solidified.
Should be noted that in the present embodiment,, be not described in detail in this because electric conductor 5 forms with existing printing means.
On the electrical connection section 502 of each electric conductor 5, form one as the connecting terminal 6 as the conductive metal balls with prior art.
See also shown in Figure 6ly, it is for the cutaway view of semiconductor chip device second embodiment of the present invention; In the present embodiment, connecting terminal 6 is when electric conductor 5 forms, and is one-body molded with electric conductor 5.
See also Fig. 7 and Fig. 8, it is the flow chart of method for packing the 3rd embodiment of semiconductor chip device of the present invention; Different with first preferred embodiment, after removing photomask, utilize the control washing time, the part that photosensitive film layer 3 is covered by photomask 4 only is rinsed removes a part, the exposed hole 30 that exposes with the head portion that only forms the corresponding contact 2 of correspondence.Then, again photosensitive film layer 3 is carried out exposure-processed.Then, as first embodiment,, on photosensitive film layer 3, form electric conductor 5, and on the electrical connection section 502 of each electric conductor 5, form the connecting terminal 6 as the conduction tin ball with conducting metal glue.
See also shown in Figure 9ly, it is for the schematic diagram of semiconductor chip device the 4th embodiment of the present invention; Different with second preferred embodiment, after removing photomask 4, utilize the control washing time, the part that photosensitive film layer 3 is covered by photomask 4 only is rinsed removes a part, to form the exposed hole 30 that only corresponding conductive contact 2 head portions is exposed.Then, again photosensitive film layer 3 is carried out exposure-processed.Then, as second embodiment,, on photosensitive film layer 3, form electric conductor 5 and connecting terminal 6 with conducting metal glue.
See also shown in Figure 10ly, it is for the schematic diagram of semiconductor chip device the 5th embodiment of the present invention; Different with first embodiment, electric conductor 5 is formed directly on the pad installation surface 10 of brilliant unit 1.
See also shown in Figure 11ly, it is for the schematic diagram of semiconductor chip device the 6th embodiment of the present invention; Different with second embodiment, electric conductor 5 is formed directly on the pad installation surface 10 of brilliant unit 1.
Compared with prior art, the present invention has following effect:
Because each electric conductor has a contact company that is electrically connected with corresponding conductive contact among the present invention Meet section, be electrically connected with the contact connecting portion and be positioned at this extension as the extension and of circuit trace Electrical connection section corresponding to bond pad locations that section's free end and its position substrate are corresponding. Therefore the present invention Device be electrically connected easily with external circuit, and then can improve the qualification rate of production.
Claims (27)
1, a kind of method for packing of semiconductor chip device, semiconductor chip device are suitable for being installed on the substrate with several weld pads, comprise the steps:
A semiconductor transistor elements is provided, and it has a pad installation surface that is provided with several weld pads, forms a conductive contact on each weld pad, and the position of weld pad does not correspond to the bond pad locations on the substrate;
On the pad installation surface of brilliant unit, form a photosensitive film layer;
Cover photosensitive film layer to one and be seated on the photosensitive film layer, and photosensitive film layer is carried out exposure-processed corresponding to conductive contact photomask partly;
After removing photomask, with chemical irrigating medium photosensitive film layer is removed by the flushing of at least a portion in the photomask cover part, so that conductive contact exposes;
Form electric conductor with conducting metal glue on photosensitive film layer, each electric conductor has one and is electrically connected with the contact connecting portion with contact connecting portion, that corresponding conductive contact is electrically connected and is positioned at the corresponding electrical connection section of corresponding bond pad locations on extension free end and its position and the substrate as the extension and of circuit trace.
2, method for packing as claimed in claim 1 is characterized in that, after the step that forms electric conductor, also comprises the steps:
On the electrical connection section of each electric conductor, form a connecting terminal.
3, method for packing as claimed in claim 2 is characterized in that, described connecting terminal is conduction tin ball.
4, method for packing as claimed in claim 2 is characterized in that, in the step that forms connecting terminal, conductive contact and described electric conductor are one-body molded.
5, method for packing as claimed in claim 1 is characterized in that, described conductive contact is conduction tin ball.
6, method for packing as claimed in claim 1 is characterized in that, described conducting metal glue is a kind of conducting metal glue that is doped with in the conductive metallic materials such as gold, silver, copper, iron, tin and aluminium.
7, method for packing as claimed in claim 1, it is characterized in that, in described chemical rinsing step, utilize the control washing time that photosensitive film layer only is rinsed by the photomask cover part and remove a part, to form the exposed hole that only corresponding conductive contact head portion is exposed, wherein, after described chemical rinsing step, also comprise the step of again photosensitive film layer being carried out exposure-processed.
8, a kind of method for packing of semiconductor chip device, semiconductor chip device are suitable for being installed on the substrate with several weld pads, comprise the steps:
A semiconductor transistor elements is provided, and it has one and is provided with several pad installation surface, forms a conductive contact on each weld pad, and the position of weld pad does not correspond to the bond pad locations of substrate;
Form electric conductor with conducting metal glue on the pad installation surface of this crystalline substance unit, each electric conductor has one and is electrically connected with the contact connecting portion with contact connecting portion, that corresponding conductive contact is electrically connected and is positioned at extension free end and its position and the corresponding electrical connection section of the corresponding bond pad locations of described substrate as the extension and of circuit trace.
9, method for packing as claimed in claim 8 is characterized in that, after the step that forms electric conductor, also comprises the steps:
On the electrical connection section of each electric conductor, form a connecting terminal.
10, method for packing as claimed in claim 9 is characterized in that, in the step that forms connecting terminal, connecting terminal forms conduction tin ball.
11, method for packing as claimed in claim 9 is characterized in that, in the step that forms connecting terminal, described conductive contact and described electric conductor are one-body molded.
12, method for packing as claimed in claim 8 is characterized in that, the conductive contact in the brilliant unit of described conductor is conduction tin ball.
13, method for packing as claimed in claim 8 is characterized in that, in the step that forms electric conductor, conducting metal glue is a kind of conducting metal glue that is doped with in the conductive metallic materials such as gold, silver, copper, iron, tin and aluminium.
14, a kind of semiconductor chip device, it is suitable for being installed on the substrate with several weld pads, comprising:
A semiconductor transistor elements, it has a pad installation surface that is provided with several weld pads and forms by the conductive contact on each weld pad, and the position of weld pad does not correspond to the bond pad locations of substrate;
A photosensitive film layer, it is formed on the pad installation surface of brilliant unit, and is formed with several in order to expose the exposed hole of corresponding conductive contact head portion at least corresponding to conductive contact;
Several are formed on the electric conductor on the photosensitive film layer, and each electric conductor has one and is electrically connected with the contact connecting portion with contact connecting portion, that corresponding conductive contact is electrically connected and is positioned at extension free end and its position bond pad locations corresponding electrical connection section corresponding with substrate as the extension and of circuit trace.
15, semiconductor device as claimed in claim 14 is characterized in that, also comprises the connecting terminal that is formed on described each electric conductor electrical connection section.
16, semiconductor device as claimed in claim 15 is characterized in that, described connecting terminal is conduction tin ball.
17, semiconductor device as claimed in claim 15 is characterized in that, described conductive contact and described electric conductor are integrally formed.
18, semiconductor device as claimed in claim 14 is characterized in that, described conductive contact is conduction tin ball.
19, semiconductor device as claimed in claim 14 is characterized in that, described electric conductor is formed by conducting metal glue.
20, semiconductor device as claimed in claim 19 is characterized in that, described conducting metal glue is a kind of conducting metal glue that is doped with in the conductive metallic materials such as gold, silver, copper, iron, tin and aluminium.
21, a kind of semiconductor chip device, it is suitable for being installed in one has on the substrate of several weld pads, comprising:
A semiconductor transistor elements, it has one and is provided with the pad installation surface of several weld pads and is formed on conductive contact on each weld pad, and the position of weld pad does not correspond to the bond pad locations of substrate;
Be formed on several electric conductors on brilliant first pad installation surface, each electric conductor has a corresponding electrical connection section in position that is electrically connected and is positioned at as the extension and of circuit trace corresponding solder joint on extension free end and its position and the substrate with contact connecting portion, that corresponding conductive contact is electrically connected with the contact connecting portion.
22, semiconductor die body device as claimed in claim 21 is characterized in that, also comprises the connecting terminal that is formed on each electric conductor electrical connection section.
23, semiconductor chip device as claimed in claim 22 is characterized in that, described connecting terminal is conduction tin ball.
24, semiconductor chip device as claimed in claim 22, its special sheet are that described conductive contact and described electric conductor are integrally formed.
25, semiconductor chip device as claimed in claim 21 is characterized in that, described conductive contact is conduction tin ball.
26, semiconductor chip device as claimed in claim 21 is characterized in that, described electric conductor is formed by conducting metal glue.
27, semiconductor chip device as claimed in claim 26 is characterized in that, described conducting metal glue is a kind of conducting metal glue that is doped with in the conductive metallic materials such as gold, silver, copper, iron, tin and aluminium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001341642A CN1149651C (en) | 2000-11-30 | 2000-11-30 | Semiconductor chip device and its package method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001341642A CN1149651C (en) | 2000-11-30 | 2000-11-30 | Semiconductor chip device and its package method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1355556A CN1355556A (en) | 2002-06-26 |
| CN1149651C true CN1149651C (en) | 2004-05-12 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001341642A Expired - Fee Related CN1149651C (en) | 2000-11-30 | 2000-11-30 | Semiconductor chip device and its package method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1149651C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100445871C (en) * | 2004-10-28 | 2008-12-24 | 探微科技股份有限公司 | Wafer bonding method |
| TWI611480B (en) * | 2014-10-17 | 2018-01-11 | 台灣積體電路製造股份有限公司 | Metal gate with silicon sidewall spacers |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7553700B2 (en) * | 2004-05-11 | 2009-06-30 | Gem Services, Inc. | Chemical-enhanced package singulation process |
| TWI460801B (en) * | 2010-10-22 | 2014-11-11 | Tsung Chi Wang | A wafer-level semiconductor wafer packaging method and a semiconductor wafer package |
| CN102593018B (en) * | 2011-01-11 | 2016-04-20 | 王琮淇 | Wafer level semiconductor wafer package method and semiconductor chip package |
-
2000
- 2000-11-30 CN CNB001341642A patent/CN1149651C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100445871C (en) * | 2004-10-28 | 2008-12-24 | 探微科技股份有限公司 | Wafer bonding method |
| TWI611480B (en) * | 2014-10-17 | 2018-01-11 | 台灣積體電路製造股份有限公司 | Metal gate with silicon sidewall spacers |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1355556A (en) | 2002-06-26 |
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| ASS | Succession or assignment of patent right |
Owner name: KAMEN INTERNATIONAL INVESTMENT LTD. Free format text: FORMER OWNER: CHEN YIMING Effective date: 20021018 |
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| C41 | Transfer of patent application or patent right or utility model | ||
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Effective date of registration: 20021018 Address after: British Virgin Islands Applicant after: Carmen International Investment Co., Ltd. Address before: Taiwan, China Applicant before: Chen Yiming |
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Owner name: IVY STOCK CO., LTD. Free format text: FORMER OWNER: KAMEN INTERNATIONAL INVESTMENT LTD. Effective date: 20040618 |
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| C41 | Transfer of patent application or patent right or utility model | ||
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Effective date of registration: 20040618 Address after: British Virgin Islands Patentee after: Changchunteng Holding Co., Ltd. Address before: British Virgin Islands Patentee before: Carmen International Investment Co., Ltd. |
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040512 Termination date: 20121130 |