CN114964569A - Quantum well bias and stress sensor - Google Patents
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- CN114964569A CN114964569A CN202210559764.9A CN202210559764A CN114964569A CN 114964569 A CN114964569 A CN 114964569A CN 202210559764 A CN202210559764 A CN 202210559764A CN 114964569 A CN114964569 A CN 114964569A
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- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/16—Measuring force or stress, in general using properties of piezoelectric devices
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Abstract
The present invention relates to quantum well bias and stress sensors and, according to one aspect of the invention, there is provided a bias and stress sensor comprising: a substrate; a first electrode disposed on the substrate; a semiconductor buffer layer disposed on the first electrode; a first semiconductor doping layer disposed on the semiconductor buffer layer; a first semiconductor isolation layer disposed on the first semiconductor doping layer; a second semiconductor isolation layer disposed on the first semiconductor isolation layer; a second semiconductor doping layer disposed on the second semiconductor isolation layer; a second electrode disposed on the second semiconductor doping layer; and a piezoelectric semiconductor layer disposed between the first and second semiconductor isolation layers and configured to have an induced bias and stress, wherein the quantum well is a semiconductor quantum well.
Description
Technical Field
The present invention relates to bias and stress sensors, and in particular, to bias and stress sensors using quantum wells.
Background
Bias and stress sensors are sensors that sense stress or pressure changes and convert them to usable output signals, and are widely used in engineering, application and other applications. Different types of bias and stress sensors are implemented mainly by a resistance strain gauge pressure sensor, a semiconductor strain gauge pressure sensor, a piezoresistive pressure sensor, an inductive pressure sensor, a capacitive pressure sensor, a resonant pressure sensor, a capacitive acceleration sensor, and the like, according to the characteristics of the sensor material and the electronic element. These types of strain gauge sensors often fail to accurately assess minute stress or voltage changes or require complex circuit structures.
In semiconductor physics, Spin Orbit Coupling (SOC) exists mainly in two forms, one is proposed by g.dreselhaus in 1955 when studying symmetry of zincblende semiconductors, and is hereinafter referred to as dreselhaus SOC, and the other is proposed by e.rashba et al when studying two-dimensional electron gas spin resonance, and is abbreviated as Rashba SOC. Rashba SOC is widely concerned because it originates from Structural Inversion Asymmetry (Structural Inversion Asymmetry) of materials, and can be manipulated in various ways, such as by electric field and stress. Electrons moving in the electric field will carry an effective magnetic field which interacts with the spin magnetic moments of the electrons to form spin-orbit coupling. Rasha SOC has received much attention in physical frontier research and applications such as spintronics, spin-orbit electronics, and topological quantum materials.
With some new semiconductor materials having piezoelectric properties and spin-orbit coupling properties, the properties of their SOC can be manipulated by bias and stress. The stress or bias voltage applied from the outside can control the interface polarization field of the structure, adjust the inversion asymmetry of the structure and adjust the Rashba SOC, and can change the material lattice deformation in the structure, adjust the inversion asymmetry of the structure and adjust the Dresselhaus SOC. Both effects contribute to a very high sensitivity to changes in strain, and only a simple sandwich structure is required to achieve high sensitivity to small bias and stress variations. The quantum well bias voltage and piezoelectric sensor is designed by utilizing the spin coupling characteristic and the piezoelectric property of materials, and compared with a common stress sensor, the novel sensor based on the spin coupling characteristic has the advantages of simple structure, low cost, low power consumption, high performance and the like.
Disclosure of Invention
Technical problem
In order to overcome the problem that micro stress is not easy to monitor, the invention provides a quantum well bias and piezoelectric sensor which can monitor external micro bias and stress.
The problem to be solved by the present invention is to provide a bias and stress sensor which is sensitive to a minute bias and stress and causes a large change in current, wherein the SOC coefficient of the piezoelectric semiconductor layer is largely changed by the influence of the bias and stress.
Further, another problem to be solved by the present invention is to provide a bias and stress sensor capable of effectively bringing applied bias and stress to the pickup portion and effectively amplifying or reducing the current inside.
Technical scheme
To solve the above problems, according to one aspect of the present invention, a bias and stress sensor is provided. The method comprises the following steps: a substrate; a first electrode disposed on the substrate; a semiconductor buffer layer disposed on the first electrode; a first semiconductor doping layer disposed on the semiconductor buffer layer; a first semiconductor isolation layer disposed on the first semiconductor doping layer; a second semiconductor isolation layer disposed on the first semiconductor isolation layer; a second semiconductor doping layer disposed on the second semiconductor isolation layer; a second electrode disposed on the second semiconductor doping layer; and a piezoelectric semiconductor layer disposed between the first semiconductor isolation layer and the second semiconductor isolation layer and configured to have an induced bias and a stress.
In addition, the quantum well is a semiconductor quantum well, and comprises a first semiconductor doping layer, a first semiconductor isolation layer, a piezoelectric semiconductor layer, a second semiconductor doping layer and a second semiconductor isolation layer.
In addition, the bias and stress sensor may further include a collecting portion for sensing the applied bias and stress, which is disposed on the piezoelectric semiconductor layer.
Further, according to another aspect of the present invention, there is provided a bias and stress sensor comprising a substrate; a first electrode disposed on the substrate; a semiconductor buffer layer disposed on the first electrode; a first semiconductor doping layer disposed on the semiconductor buffer layer; a first semiconductor isolation layer disposed on the first semiconductor doping layer; a second semiconductor isolation layer disposed on the first semiconductor isolation layer; a second semiconductor doping layer disposed on the second semiconductor isolation layer; a second electrode disposed on the second semiconductor doped layer; and a piezoelectric semiconductor layer disposed between the first semiconductor isolation layer and the second semiconductor isolation layer and configured to have an induced bias and a stress. In addition, the quantum well is a semiconductor quantum well. In addition, the bias and stress sensor may further include a collecting portion for sensing the applied bias and stress, which is disposed on the piezoelectric semiconductor layer.
Advantageous effects
As described above, the bias and stress sensor designed according to at least one example of the present invention changes the current transfer signal of the quantum well by regulating the SOC coefficient of the piezoelectric semiconductor layer by the bias and stress. The current transmission signal is further amplified or reduced by utilizing the bias and stress adjustability of the electrical properties and spin-orbit coupling properties of the quantum well, thereby being used for detecting small changes of external bias and stress. In addition, the bias voltage and the stress can be effectively induced by the collecting portion, and the efficiency of the bias voltage and the stress sensor can be improved. The device has the advantages of no need of complex circuits, simple structure, low power consumption, high sensitivity and the like.
Drawings
Fig. 1 is a schematic cross-sectional view showing a bias and stress sensor according to a first example of the present invention.
FIG. 2 is a schematic three-dimensional diagram illustrating a bias and stress sensor according to a first example of the present invention.
Fig. 3 is a schematic cross-sectional view showing a bias and stress sensor according to a second example of the present invention.
FIG. 4 is a schematic three-dimensional diagram illustrating a bias and stress sensor in accordance with a second example of the present invention.
Detailed Description
Hereinafter, a bias and stress sensor according to an example of the present invention will be described in detail with reference to the accompanying drawings.
In addition, the same or similar reference numerals are given to the same or corresponding components regardless of the reference numerals, redundant description thereof will be omitted, and the size and shape of each component member shown may be enlarged or reduced for convenience of description.
Fig. 1 is a schematic cross-sectional view showing a bias and stress sensor (10) according to a first example of the present invention.
The invention provides a bias and stress sensor (10) comprising a piezoelectric semiconductor layer formed between a first semiconductor isolation layer and a second semiconductor isolation layer. Further, the piezoelectric semiconductor layer is provided so that its SOC coefficient can be influenced by applied bias and stress.
The bias and stress sensor (10) designed by referring to the first example of fig. 1 comprises a substrate (11), a first electrode (12), a semiconductor buffer layer (13), a first semiconductor doping layer (14), a first semiconductor isolation layer (15), a piezoelectric semiconductor layer (16), a second semiconductor isolation layer (17), a second semiconductor doping layer (18) and a second electrode (19).
In particular, one example of the invention relates to a bias and stress sensor (10) comprising a substrate (11); a first electrode (12) disposed on the substrate; a semiconductor buffer layer (13) disposed on the first electrode; a first semiconductor doped layer (14) disposed on the semiconductor buffer layer; a first semiconductor isolation layer (15) disposed on the first semiconductor doped layer; a second semiconductor isolation layer (17) disposed on the first semiconductor isolation layer; a second semiconductor doped layer (18) disposed on the second semiconductor isolation layer; a second electrode (19) disposed on the second semiconductor doped layer; and a piezoelectric semiconductor layer (16) disposed between the first semiconductor isolation layer and the second semiconductor isolation layer and configured to have an induced bias and stress.
Further, the semiconductor buffer layer (13) and the second semiconductor doping layer (18) are provided to be electrically connected to the first electrode layer (12) and the second electrode layer (19), respectively.
Furthermore, a first semiconductor doping layer (14) and a second semiconductor isolation layer (17) are provided to be electrically connected to the semiconductor buffer layer (13) and the second semiconductor doping layer (18), respectively.
Furthermore, the first semiconductor isolation layer (15) and the piezoelectric semiconductor layer (16) are provided so as to be electrically connected to the first semiconductor doping layer (14) and the second semiconductor isolation layer (17), respectively.
Furthermore, the piezoelectric semiconductor layer (16) is provided so as to be electrically connected to the first semiconductor isolation layer (15) and the second semiconductor isolation layer (17).
Further, the piezoelectric semiconductor layer (16) is configured such that its SOC coefficient varies with applied bias and stress.
In the piezoelectric semiconductor layer (16), the quantum well can easily control the energy gap of the electronic structure by controlling the size and composition thereof.
The principle of operation of the bias and stress sensor (10) using quantum wells is to detect the current transfer signal in the piezoelectric semiconductor layer in real time and to take advantage of the change in the SOC coefficient of the piezoelectric semiconductor layer (16), which may be combined with a field effect Thin Film Transistor (TFT), for example, in the case of the bias and stress sensor (10) using quantum wells.
In particular, it may cause and measure a current transmission signal difference with respect to a change in the SOC coefficient, which is generated when the SOC coefficient of the piezoelectric semiconductor layer (16) is changed according to the applied bias voltage and stress induction with respect to the piezoelectric semiconductor layer (16).
In addition, the semiconductor layer (16) may be formed in the form of a film.
Furthermore, the difference in current delivered signal due to the change in SOC coefficient caused by applied bias and stress, which are inversely related to applied bias and stress, respectively, is a new and highly feasible measurement method.
Further, the semiconductor buffer layer usable in the present invention is any one or more selected from the group consisting of: ALGaN, InGaN, MgZnO, CdZnO, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, GaNAs, GaNSb, GaAs, GaSb, InNP, InNAs, InSb, InPAS, InPSb, SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbPbS, SnPbSe, SnPbTe.
Further, the first and second semiconductor doped layers useful in the present invention are any one or more selected from the group consisting of: ALGaN, InGaN, MgZnO, CdZnO, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, GaNAs, GaNSb, GaAs, GaSb, InNP, InNAs, InSb, InPAS, InPSb, SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbPbS, SnPbSe, SnPbTe.
In addition, the first semiconductor doping layer and the second semiconductor doping layer should have a certain doping concentration.
Further, the first semiconductor isolation layer and the second semiconductor isolation layer usable in the present invention are any one or more selected from the group consisting of: ALGaN, InGaN, MgZnO, CdZnO, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, GaNAs, GaNSb, GaAs, GaSb, InNP, InNAs, InSb, InPAS, InPSb, SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbPbS, SnPbSe, SnPbTe.
In addition, as a usable quantum well in the present invention, a semiconductor quantum well is preferably used. When a semiconductor quantum well is used, the semiconductor quantum well may be formed between the first electrode (12) and the second electrode (19) by methods including, but not limited to, molecular beam epitaxy, solution methods, etc., and may be uniformly distributed.
As the piezoelectric semiconductor, any one or more selected from the following may be used: GaN, ZnO, BN, BP, BAs, AlN, AlP, AlAs, AlSb, GaP, GaAs, GaSb, InN, InP, InAs, InSb.
In addition, the first electrode (12) and the second electrode (19) may be respectively formed of a metal, and any one or more selected from the following may be used: cr, MO, Al, Ti, Au, Ag, Cu, and Pt.
Further, the substrate (11) is selected from any one or more of the following (flexible material): polyvinyl alcohol (PVA), polyesters (e.g. PET), Polyimide (PI), polyethylene naphthalate (PEN), paper sheets, textile materials, Polytetrafluoroethylene (PTFE), Polydimethylsiloxane (PDMS).
In addition, the remaining structure other than the first electrode (12), the semiconductor buffer layer (13), the first semiconductor doping layer (14), the first semiconductor isolation layer (15), the piezoelectric semiconductor layer (16), the second semiconductor isolation layer (17), the second semiconductor doping layer (18), and the second electrode (19) as described above is not particularly limited as long as it can be generally used in the bias and stress sensor (10).
Fig. 3 is a schematic cross-sectional view showing a bias and stress sensor (100) according to a second example of the present invention.
The bias and stress sensor (100) designed with reference to the second example of fig. 3 comprises a substrate (110), a first electrode (120), a first semiconductor doped layer (140), a piezoelectric semiconductor layer (160), a second semiconductor doped layer (180), and a second electrode (190).
In particular, one example of the invention relates to a bias and stress sensor (100) comprising a substrate (110); a first electrode (120) disposed on the substrate; a first semiconductor doping layer (140) disposed on the semiconductor buffer layer; a second doped semiconductor layer (180) disposed on the first doped semiconductor layer; a second electrode (190) disposed on the second semiconductor doped layer; and a piezoelectric semiconductor layer (160) disposed between the first and second doped semiconductor layers and configured to have an induced bias and stress.
Further, the first semiconductor doping layer (140) and the second semiconductor doping layer (180) are provided to be electrically connected to the first electrode layer (120) and the second electrode layer (190), respectively.
Further, the piezoelectric semiconductor layer (160) is provided to be electrically connected to the first semiconductor doping layer (140) and the second semiconductor doping layer (180).
Further, the piezoelectric semiconductor layer (160) is configured such that its SOC coefficient varies with applied bias and stress.
In the piezoelectric semiconductor layer (160), the quantum well can easily control the energy gap of the electronic structure by controlling the size and composition thereof.
The operating principle of the bias and stress sensor (100) using quantum wells is to detect the current transfer signal in the piezoelectric semiconductor layer in real time and to utilize the SOC coefficient variation of the piezoelectric semiconductor layer (160), which can be combined with a field effect Thin Film Transistor (TFT) in the case of the bias and stress sensor (100) using quantum wells, for example.
In particular, it may cause and measure a current transfer signal difference with respect to a change in the SOC coefficient, which is generated when the SOC coefficient of the piezoelectric semiconductor layer (160) is changed according to the applied bias voltage and stress induction of the piezoelectric semiconductor layer (160).
In addition, the semiconductor layer (160) may be formed in a film form.
Furthermore, the difference in current delivered signal due to the change in SOC coefficient caused by applied bias and stress, which are inversely related to applied bias and stress, respectively, is a new and highly feasible measurement method.
Further, the first and second semiconductor doped layers useful in the present invention are any one or more selected from the group consisting of: ALGaN, InGaN, MgZnO, CdZnO, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, GaNAs, GaNSb, GaAs, GaPSb, InNP, InNAs, InNb, InPAs, InPSb, SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbPbS, Sn56Se, SnPbTe.
In addition, the first semiconductor doping layer and the second semiconductor doping layer should have a certain doping concentration.
In addition, as a usable quantum well in the present invention, a semiconductor quantum well is preferably used. When a semiconductor quantum well is used, the semiconductor quantum well may be formed between the first electrode (120) and the second electrode (190) by methods including, but not limited to, molecular beam epitaxy, solution methods, etc., and may be uniformly distributed.
As the piezoelectric semiconductor, any one or more selected from the following may be used: GaN, ZnO, BN, BP, BAs, AlN, AlP, AlAs, AlSb, GaP, GaAs, GaSb, InN, InP, InAs, InSb.
In addition, the first electrode (120) and the second electrode (190) may be respectively formed of a metal, and any one or more selected from the following may be used: cr, MO, Al, Ti, Au, Ag, Cu, and Pt.
Further, the substrate (110) is selected from any one or more of the following (flexible materials): polyvinyl alcohol (PVA), polyesters (e.g. PET), Polyimide (PI), polyethylene naphthalate (PEN), paper sheets, textile materials, Polytetrafluoroethylene (PTFE), Polydimethylsiloxane (PDMS).
In addition, the remaining structure except the first electrode (120), the first semiconductor doping layer (140), the piezoelectric semiconductor layer (160), the second semiconductor doping layer (180), the second electrode (190) as described above is not particularly limited as long as it can be generally used in the bias and stress sensor (100).
The preferred embodiments of the present invention as described above are disclosed for illustrative purposes, and those skilled in the art will appreciate that modifications, variations and additions are possible, within the spirit and scope of the invention, and such modifications, variations and additions are contemplated as falling within the claims below.
INDUSTRIAL APPLICABILITY
The bias and stress sensor designed according to at least one example of the present invention can detect bias and stress by measuring a change in SOC coefficient of the piezoelectric semiconductor layer based on the sensing of the piezoelectric semiconductor layer before the bias and stress are applied.
Claims (19)
1. A quantum well bias and stress sensor comprising;
a substrate;
a first electrode disposed on the substrate;
a semiconductor buffer layer disposed on the first electrode;
a first semiconductor doping layer disposed on the semiconductor buffer layer;
a first semiconductor isolation layer disposed on the first semiconductor doping layer;
a second semiconductor isolation layer disposed on the first semiconductor isolation layer;
a second semiconductor doping layer disposed on the second semiconductor isolation layer;
a second electrode disposed on the second semiconductor doping layer;
and a piezoelectric semiconductor layer disposed between the first semiconductor isolation layer and the second semiconductor isolation layer and configured to have an induced bias and a stress.
Wherein the quantum well is a semiconductor quantum well.
2. The bias and stress sensor according to claim 1, comprising a pickup portion for sensing bias and stress, the pickup portion being disposed on the piezoelectric semiconductor layer.
3. The bias and stress sensor according to claim 2, wherein the pick-up portion is influenced by a bias voltage including, but not limited to, one or more of: alternating current, direct current, pulse.
4. The bias and stress sensor according to claim 2, wherein the pick-up portion is capable of being affected by stresses in the form of one or more of, but not limited to: stretching, compressing, rotating, twisting.
5. The bias and stress sensor according to claims 3-4, wherein the bias is applied at a first electrode and the second electrode.
6. The bias and stress sensor according to claims 3-4, wherein said stress is applied to a surface of said sensor.
7. The bias and stress sensor according to claim 1, wherein the piezoelectric semiconductor layer is selected from any one or more of the following (typically as a group III-V semiconductor): GaN, ZnO, BN, BP, BAs, AlN, AlP, AlAs, AlSb, GaP, GaAs, GaSb, InN, InP, InAs, InSb.
8. The bias and stress sensor according to claim 1, wherein said quantum well comprises a first semiconductor doped layer, a first semiconductor isolation layer, a piezoelectric semiconductor layer, a second semiconductor doped layer, and a second semiconductor isolation layer.
9. The bias and stress sensor of claim 7, wherein the spin-orbit coupling (SOC) coefficient of the piezoelectric semiconductor is affected by stress or bias.
10. The bias and stress sensor according to claim 1, wherein the quantum wells have quantum transport properties that can be influenced by stress or bias.
11. The bias and stress sensor according to claim 8, wherein current within the quantum well is affected by stress or bias.
12. The bias and stress sensor of claim 1, wherein said first and second semiconductor isolation layers are selected from any one or more of the group consisting of: ALGaN, InGaN, MgZnO, CdZnO, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, GaNAs, GaNSb, GaAs, GaSb, InNP, InNAs, InSb, InPAS, InPSb, SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbPbS, SnPbSe, SnPbTe.
13. The bias and stress sensor according to claim 1, wherein said first and second doped semiconductor layers are selected from any one or more of the group consisting of: ALGaN, InGaN, MgZnO, CdZnO, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, GaNAs, GaNSb, GaAs, GaPSb, InNP, InNAs, InNSb, InPAs, InPSb, SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe.
14. The first and second doped semiconductor layers of claim 10 having a dopant concentration.
15. The bias and stress sensor according to claim 1, wherein said semiconductor buffer layer is selected from any one or more of the group consisting of: ALGaN, InGaN, MgZnO, CdZnO, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, GaNAs, GaNSb, GaAs, GaSb, InNP, InNAs, InSb, InPAS, InPSb, SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbPbS, SnPbSe, SnPbTe.
16. The bias and stress sensor according to claim 1, wherein the first and second electrodes are selected from any one or more of the following (metals): cr, MO, Al, Ti, Au, Ag, Cu, and Pt.
17. The bias and stress sensor according to claim 1, wherein the substrate is selected from any one or more of the following (flexible material): polyvinyl alcohol (PVA), polyesters (e.g. PET), Polyimides (PI), polyethylene naphthalate (PEN), paper sheets, textile materials, Polytetrafluoroethylene (PTFE) Polydimethylsiloxane (PDMS).
18. A quantum well bias and stress sensor comprising;
a substrate;
a first electrode disposed on the substrate;
a semiconductor buffer layer disposed on the first electrode;
a first semiconductor doping layer disposed on the semiconductor buffer layer;
a first semiconductor isolation layer disposed on the first semiconductor doping layer;
a second semiconductor isolation layer disposed on the first semiconductor isolation layer;
a second semiconductor doping layer disposed on the second semiconductor isolation layer;
a second electrode disposed on the second semiconductor doping layer;
and a piezoelectric semiconductor layer disposed between the first semiconductor isolation layer and the second semiconductor isolation layer and configured to have an induced bias and a stress.
Wherein the quantum well is a semiconductor quantum well.
19. The bias and stress sensor according to claim 18, comprising a harvesting portion for sensing bias and stress, the harvesting portion being disposed on the piezoelectric semiconductor layer.
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