CN114943156A - Power consumption evaluation method, device, equipment, medium and product - Google Patents
Power consumption evaluation method, device, equipment, medium and product Download PDFInfo
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Abstract
The invention discloses a power consumption evaluation method, a power consumption evaluation device, power consumption evaluation equipment, power consumption evaluation media and a power consumption evaluation product. The method comprises the following steps: acquiring a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated; determining a target time sequence key path, a capacitance turnover rate, a total capacitance of a target circuit and a working voltage corresponding to the target process library file of the target circuit according to the target process library file and the target circuit file; and determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file.
Description
Technical Field
The embodiment of the invention relates to the technical field of computers, in particular to a power consumption evaluation method, a power consumption evaluation device, power consumption evaluation equipment, power consumption evaluation media and a power consumption evaluation product.
Background
In order to better improve the performance of the processor, it is often necessary to evaluate the power consumption of the processor at an early design stage. In terms of power consumption assessment, a structure level power consumption assessment tool is a method which is used more in the early stage of design. To improve processor performance, the processor is typically required to handle different loads over a wide voltage range.
In past research, the input of the structure-level power consumption assessment tool often needs a performance simulator to perform clock-accurate simulation acquisition, the process is time-consuming, the time is often several days, ten days or even longer, and rapid design space exploration is difficult to perform. In addition, the traditional structure level power consumption evaluation tool has poor evaluation effect on the condition of wide voltage, does not consider the change of the working frequency of the processor under different voltages, always calculates the power consumption of the processor at a fixed working frequency, and does not provide good help for the energy efficiency evaluation of a new wide-voltage high-energy-efficiency processor.
Disclosure of Invention
The embodiment of the invention provides a power consumption evaluation method, a power consumption evaluation device, a power consumption evaluation equipment, a power consumption evaluation medium and a power consumption evaluation product, so that the power consumption evaluation precision can be improved.
According to an aspect of the present invention, there is provided a power consumption evaluation method including:
acquiring a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated;
determining a target time sequence key path, a capacitance turnover rate, a total capacitance of a target circuit and a working voltage corresponding to the target process library file of the target circuit according to the target process library file and the target circuit file;
and determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file.
Further, the target circuit includes: at least one circuit unit, the target process library file comprising: the power consumption value of the circuit unit under the target process condition and the time delay value of the unit circuit under the target process condition;
correspondingly, determining a target time sequence critical path, a capacitance turnover rate, a total capacitance of the target circuit and a working voltage corresponding to the target process library file according to the target process library file and the target circuit file comprises:
determining netlist information, timing constraint information and a circuit top-level file of the target circuit according to the target circuit file;
and determining a target time sequence key path, a capacitance turnover rate, a total capacitance of the target circuit and a working voltage corresponding to the target process library file of the target circuit according to the netlist information, the time sequence constraint information, the top-level file of the circuit, the power consumption value of the circuit unit under the target process condition and the time delay value of the circuit unit under the target process condition.
Further, determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file, including:
determining a time delay value of the processor to be evaluated corresponding to a preset voltage value and a preset temperature value according to the target time sequence key path, the preset voltage value and the preset temperature value;
and determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the time delay value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.
Further, determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the time delay value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value, including:
calculating the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value based on the following formula:
P i,j ＝αCV 2 f i,j ；
wherein, P i,j When the voltage value is i and the temperature value is j, the power consumption value of the processor to be evaluated, alpha is the turnover rate of the capacitor, C is the total capacitor of the target circuit, V is the working voltage corresponding to the target process library file,
i is a voltage value, j is a temperature value, f i,j The operating frequency, Delay, of the processor to be evaluated at a voltage value of i and a temperature value of j i,j The time delay value of the processor to be evaluated is when the voltage value is i and the temperature value is j.
Further, determining a delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence critical path, the preset voltage value and the preset temperature value includes:
generating a spice file according to the target time sequence key path, a preset voltage value and a preset temperature value;
packaging the spice file to obtain a sub-circuit file;
and performing spice simulation based on the sub-circuit file to obtain the time delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.
Furthermore, i takes a value of 0.6V to 1.0V, and j takes a value of-25 ℃ to 125 ℃.
According to another aspect of the present invention, there is provided a power consumption evaluation apparatus including:
the system comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated;
the path determining module is used for determining a target time sequence key path, a capacitance turnover rate, a total capacitance of the target circuit and a working voltage corresponding to the target process library file according to the target process library file and the target circuit file;
and the power consumption value determining module is used for determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file.
According to another aspect of the present invention, there is provided an electronic apparatus including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform the power consumption assessment method according to any of the embodiments of the invention.
According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the power consumption assessment method according to any one of the embodiments of the present invention when the computer instructions are executed.
According to another aspect of the invention, a computer program product is provided, which computer program, when being executed by a processor, carries out the power consumption assessment method according to any one of the embodiments of the invention.
The method comprises the steps of obtaining a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated; determining a target time sequence key path, a capacitance turnover rate, a total capacitance of a target circuit and a working voltage corresponding to the target process library file of the target circuit according to the target process library file and the target circuit file; and determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file, so that the power consumption evaluation precision can be improved.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a flow chart of a power consumption assessment method in an embodiment of the invention;
FIG. 2 is a schematic structural diagram of a power consumption evaluation apparatus according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device in an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example one
Fig. 1 is a flowchart of a power consumption evaluation method provided in an embodiment of the present invention, where this embodiment is applicable to a power consumption evaluation situation, and the method may be executed by a power consumption evaluation apparatus in an embodiment of the present invention, and the apparatus may be implemented in a software and/or hardware manner, as shown in fig. 1, the method specifically includes the following steps:
s110, acquiring a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated.
It should be noted that manufacturers provide process library files for different process conditions, preset research environments, that is, target process conditions, and determine the process library files under the target process conditions as target process library files.
Wherein the target circuit comprises: at least one circuit unit, the target process library file comprising: a power consumption value of the circuit unit under a target process condition, and a delay value of the unit circuit under the target process condition, which may be a process condition determined according to a research environment. For example, there may be 7nm1.1v, 40nm0.6v library documents, where 7nm and 40nm are both process, i.e., processor transistor dimensions.
The target circuit file comprises a plurality of subfiles, and each subfile is a file containing circuit submodule information. The subfiles are input files for Design Compiler and Primetime, a common EDA tool used in timing analysis.
And S120, determining a target time sequence key path, a capacitance turnover rate, a total capacitance of the target circuit and a working voltage corresponding to the target process library file of the target circuit according to the target process library file and the target circuit file.
Specifically, the method for determining the target timing critical path, the capacitance turnover rate, the total capacitance of the target circuit, and the working voltage corresponding to the target process library file according to the target process library file and the target circuit file may be: and inputting the target process library file and the target circuit file into Primetime to obtain a target time sequence key path, a capacitance turnover rate, a total capacitance of the target circuit and a working voltage corresponding to the target process library file. The method for determining the target time sequence critical path, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file according to the target process library file and the target circuit file can also be as follows: determining netlist information, timing constraint information and a circuit top-level file of the target circuit according to the target circuit file; and determining a target time sequence key path, a capacitance turnover rate, a total capacitance of the target circuit and a working voltage corresponding to the target process library file of the target circuit according to the netlist information, the time sequence constraint information, the top-level file of the circuit, the power consumption value of the circuit unit under the target process condition and the time delay value of the circuit unit under the target process condition.
Optionally, the target circuit includes: at least one circuit unit, the target process library file comprising: the power consumption value of the circuit unit under the target process condition and the time delay value of the unit circuit under the target process condition;
correspondingly, determining a target time sequence critical path, a capacitance turnover rate, a total capacitance of the target circuit and a working voltage corresponding to the target process library file according to the target process library file and the target circuit file comprises:
determining netlist information, timing constraint information and a circuit top-level file of the target circuit according to the target circuit file;
and determining a target time sequence key path, a capacitance turnover rate, a total capacitance of the target circuit and a working voltage corresponding to the target process library file of the target circuit according to the netlist information, the time sequence constraint information, the top-level file of the circuit, the power consumption value of the circuit unit under the target process condition and the time delay value of the circuit unit under the target process condition.
Wherein the netlist information of the target circuit comprises: logical relationships between circuit units and attribute information of each circuit unit.
Wherein the timing constraint information comprises: clock, input delay, output time, and output load, etc.
The circuit top-level file is a subfile which is operated at the beginning in a plurality of subfiles contained in the target circuit file, namely, the circuit top-level file is operated at first, and then other subfiles are called.
The netlist information and the timing constraint information of the target circuit can be obtained in the following modes: and inputting the target circuit file into Design Compiler to obtain netlist information and timing constraint information of the target circuit.
Specifically, the method for determining the target time sequence critical path, the capacitance inversion rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file according to the netlist information, the timing constraint information, the top-level file of the circuit, the power consumption value of the circuit unit under the target process condition and the time delay value of the circuit unit under the target process condition of the target circuit may be: and inputting the netlist information, the timing constraint information, the top-level circuit file, the power consumption value of the circuit unit under the target process condition and the time delay value of the circuit unit under the target process condition into Primetime to obtain a target timing critical path, a capacitance turnover rate, a total capacitance of the target circuit and a working voltage corresponding to the target process library file of the target circuit.
In a specific example, the target circuit file is input into a Design Compiler to obtain netlist information, timing constraint information and a circuit top-level file of the target circuit, the netlist information, the timing constraint information, the circuit top-level file of the target circuit, the power consumption value of the circuit unit under the target process condition and the delay value of the circuit unit under the target process condition are input into a Primetime to obtain a target timing critical path and a power consumption file of the target circuit, the power consumption file comprises W,
wherein alpha is the capacitance turnover rate, C is the total capacitance of the target circuit, V is the working voltage corresponding to the target process library file, K is the clock, and the value of AC is determined according to W, V and K.
And S130, determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file.
The value range of the preset voltage can be as follows: 0.6V-1.0V, and the value range of the preset temperature value can be as follows: -25 ℃ to 125 ℃.
The power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value can be displayed in a list, wherein the list comprises: voltage value, temperature value and power consumption value of the processor to be evaluated. For example, the power consumption value a of the processor to be evaluated when the voltage value is 0.6V and the temperature value is-25 ℃, the voltage value is 0.7V, the power consumption value B of the processor to be evaluated when the temperature value is 40 ℃, the voltage value is 0.6V, the power consumption value C of the processor to be evaluated when the temperature value is-10 ℃ and the like, which are not limited in this embodiment of the present invention.
Specifically, the method for determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit, and the working voltage corresponding to the target process library file may be: determining a time delay value of the processor to be evaluated corresponding to a preset voltage value and a preset temperature value according to the target time sequence key path, the preset voltage value and the preset temperature value; and determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the time delay value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.
Optionally, determining, according to the target timing critical path, a preset voltage value, a preset temperature value, a capacitance inversion rate, a total capacitance of the target circuit, and a working voltage corresponding to the target process library file, a power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value includes:
determining a time delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence key path, the preset voltage value and the preset temperature value;
and determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the time delay value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.
Specifically, the method for determining the time delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence critical path, the preset voltage value and the preset temperature value may be: generating a spice file according to the target time sequence key path, a preset voltage value and a preset temperature value; packaging the spice file to obtain a sub-circuit file; and performing spice simulation based on the sub-circuit file to obtain the time delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.
In a specific example, after obtaining a spice file containing a target timing critical path by using Primetime, packaging the spice file to obtain a sub-circuit file, and performing spice simulation based on the sub-circuit file. After the sub-circuit packaging work of the target time sequence critical path is completed, the time delay values of the processor to be evaluated under different voltage and temperature conditions can be obtained by utilizing spice simulation.
Specifically, the method for determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the time delay value, the capacitance inversion rate, the total capacitance of the target circuit, and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value may be: determining the reciprocal of the delay value as a power consumption value, for example, the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value may be calculated based on the following formula:
calculating the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value based on the following formula:
P i,j ＝αCV 2 f i,j ；
wherein, P i,j When the voltage value is i and the temperature value is j, the power consumption value of the processor to be evaluated, alpha is the turnover rate of the capacitor, C is the total capacitor of the target circuit, V is the working voltage corresponding to the process library file,
i is a voltage value, j is a temperature value, f i,j The operating frequency, Delay, of the processor to be evaluated at a voltage value of i and a temperature value of j i,j The time delay value of the processor to be evaluated is when the voltage value is i and the temperature value is j.
It should be noted that, because the process library files provided by a general chip foundry only include power consumption values and delay values of the standard circuit unit under several specific voltage and temperature environmental conditions, the delay information under the several specific process conditions can only be obtained by directly using the process library files, and the circuit delay information in a wide voltage range cannot be obtained. In order to realize the voltage scanning function, Primetime is used for extracting time sequence key paths of a target circuit under a process library condition, and then spice simulation is carried out on the extracted time sequence key paths to generate processor time delay values to be evaluated of the target circuit under different voltage and temperature conditions.
Optionally, determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the delay value, the capacitance turnover rate, the total capacitance of the target circuit, and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value includes:
calculating the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value based on the following formula:
P i,j ＝αCV 2 f i,j ；
wherein, P i,j Is the power consumption value of the processor to be evaluated when the voltage value is i and the temperature value is j, alpha is the turnover rate of the capacitor, C is the total capacitance of the target circuit, V isThe working voltage corresponding to the target process library file,
i is a voltage value, j is a temperature value, f i,j The operating frequency, Delay, of the processor to be evaluated at a voltage value of i and a temperature value of j i,j The time delay value of the processor to be evaluated is when the voltage value is i and the temperature value is j.
Specifically, when modeling circuit delay information, the influence of voltage and temperature changes on target circuit delay is mainly considered, and the relationship between the voltage and temperature changes and the circuit delay is described by selecting simple regression of single independent variables in a linear regression method. The processor's latency value may then be used to represent the power consumption value of the processor under different voltage and temperature conditions.
Optionally, determining, according to the target timing critical path, a preset voltage value, and a preset temperature value, a delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value includes:
generating a spice file according to the target time sequence key path, a preset voltage value and a preset temperature value;
packaging the spice file to obtain a sub-circuit file;
and performing spice simulation based on the sub-circuit file to obtain the time delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.
It should be noted that since the spice simulation cannot be directly performed based on the spice file, the spice file needs to be packaged to obtain the sub-circuit file, and then the spice simulation is performed on the sub-circuit file.
Optionally, i is 0.6V-1.0V, and j is-25 ℃ to 125 ℃.
It should be noted that, at different operating voltages and temperatures, the actual frequency of the processor is not fixed, and generally, the actual system main frequency is reduced while the system supply voltage is reduced in the case of meeting the performance requirement of the processor. At this time, like the original structure level power consumption evaluation tool, if the same system main frequency is used to calculate the power consumption for different working voltages, a non-negligible error will be generated.
According to the technical scheme of the embodiment, a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated are obtained; determining a target time sequence key path, a capacitance turnover rate, a total capacitance of a target circuit and a working voltage corresponding to the target process library file of the target circuit according to the target process library file and the target circuit file; according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file, the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is determined.
Example two
Fig. 2 is a schematic structural diagram of a power consumption evaluation apparatus according to an embodiment of the present invention. The present embodiment may be applicable to the case of power consumption evaluation, where the apparatus may be implemented in a software and/or hardware manner, and the power consumption evaluation apparatus may be integrated in any device that provides a power consumption evaluation function, as shown in fig. 2, where the power consumption evaluation apparatus specifically includes: an acquisition module 210, a path determination module 220, and a power consumption value determination module 230.
The system comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated;
the path determining module is used for determining a target time sequence key path, a capacitance turnover rate, a total capacitance of a target circuit and a working voltage corresponding to the target process library file according to the target process library file and the target circuit file;
and the power consumption value determining module is used for determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file.
The product can execute the method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
According to the technical scheme of the embodiment, a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated are obtained; determining a target time sequence key path, a capacitance turnover rate, a total capacitance of a target circuit and a working voltage corresponding to the target process library file of the target circuit according to the target process library file and the target circuit file; according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file, the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value is determined.
EXAMPLE III
FIG. 3 illustrates a schematic diagram of an electronic device 10 that may be used to implement an embodiment of the present invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 3, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a Read Only Memory (ROM)12, a Random Access Memory (RAM)13, and the like, wherein the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM)12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data necessary for the operation of the electronic apparatus 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.
A number of components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, or the like; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.
The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, or the like. The processor 11 performs the various methods and processes described above, such as the power consumption assessment method.
In some embodiments, the power consumption assessment method may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the power consumption evaluation method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured by any other suitable means (e.g., by means of firmware) to perform the power consumption assessment method:
acquiring a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated;
determining a target time sequence key path, a capacitance turnover rate, a total capacitance of a target circuit and a working voltage corresponding to the target process library file of the target circuit according to the target process library file and the target circuit file;
and determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file.
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. A computer program can execute entirely on a machine, partly on a machine, as a stand-alone software package partly on a machine and partly on a remote machine or entirely on a remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service are overcome.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.
An embodiment of the present invention further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the method for power consumption assessment according to any embodiment of the present invention is implemented.
The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A power consumption evaluation method, comprising:
acquiring a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated;
determining a target time sequence key path, a capacitance turnover rate, a total capacitance of a target circuit and a working voltage corresponding to the target process library file of the target circuit according to the target process library file and the target circuit file;
and determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file.
2. The method of claim 1, wherein the target circuit comprises: at least one circuit unit, the target process library file comprising: the power consumption value of the circuit unit under the target process condition and the time delay value of the unit circuit under the target process condition;
correspondingly, determining a target time sequence critical path, a capacitance turnover rate, a total capacitance of the target circuit and a working voltage corresponding to the target process library file according to the target process library file and the target circuit file comprises:
determining netlist information, timing constraint information and a circuit top-level file of the target circuit according to the target circuit file;
and determining a target time sequence key path, a capacitance turnover rate, a total capacitance of the target circuit and a working voltage corresponding to the target process library file of the target circuit according to the netlist information, the time sequence constraint information, the top-level file of the circuit, the power consumption value of the circuit unit under the target process condition and the time delay value of the circuit unit under the target process condition.
3. The method of claim 1, wherein determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, a preset voltage value, a preset temperature value, a capacitance turnover rate, a total capacitance of the target circuit, and the operating voltage corresponding to the target process library file comprises:
determining a time delay value of the processor to be evaluated corresponding to a preset voltage value and a preset temperature value according to the target time sequence key path, the preset voltage value and the preset temperature value;
and determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the time delay value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.
4. The method according to claim 3, wherein determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the delay value, the capacitance inversion rate, the total capacitance of the target circuit, and the operating voltage corresponding to the target process library file of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value comprises:
calculating the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value based on the following formula:
P i,j ＝αCV 2 f i,j ；
wherein, P i,j When the voltage value is i and the temperature value is j, the power consumption value of the processor to be evaluated, alpha is the turnover rate of the capacitor, C is the total capacitor of the target circuit, V is the working voltage corresponding to the target process library file,
i is a voltage value, j is a temperature value, f i,j The operating frequency, Delay, of the processor to be evaluated at a voltage value of i and a temperature value of j i,j The time delay value of the processor to be evaluated is when the voltage value is i and the temperature value is j.
5. The method according to claim 3, wherein determining the delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target timing critical path, the preset voltage value and the preset temperature value comprises:
generating a spice file according to the target time sequence key path, a preset voltage value and a preset temperature value;
packaging the spice file to obtain a sub-circuit file;
and performing spice simulation based on the sub-circuit file to obtain the time delay value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value.
6. The method of claim 4, wherein i is 0.6V to 1.0V and j is-25 ℃ to 125 ℃.
7. A power consumption evaluation apparatus, comprising:
the system comprises an acquisition module, a processing module and a processing module, wherein the acquisition module is used for acquiring a target process library file corresponding to a processor to be evaluated and a target circuit file corresponding to the processor to be evaluated;
the path determining module is used for determining a target time sequence key path, a capacitance turnover rate, a total capacitance of a target circuit and a working voltage corresponding to the target process library file according to the target process library file and the target circuit file;
and the power consumption value determining module is used for determining the power consumption value of the processor to be evaluated corresponding to the preset voltage value and the preset temperature value according to the target time sequence key path, the preset voltage value, the preset temperature value, the capacitance turnover rate, the total capacitance of the target circuit and the working voltage corresponding to the target process library file.
8. An electronic device, characterized in that the electronic device comprises:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the power consumption assessment method of any one of claims 1-6.
9. A computer-readable storage medium storing computer instructions for causing a processor to perform the power consumption assessment method of any one of claims 1-6 when executed.
10. A computer program product, characterized in that the computer program product comprises a computer program which, when being executed by a processor, implements the power consumption assessment method according to any one of claims 1-6.
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