CN114942901B - Method, device, equipment and readable medium for serial coding - Google Patents

Method, device, equipment and readable medium for serial coding Download PDF

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CN114942901B
CN114942901B CN202210748338.XA CN202210748338A CN114942901B CN 114942901 B CN114942901 B CN 114942901B CN 202210748338 A CN202210748338 A CN 202210748338A CN 114942901 B CN114942901 B CN 114942901B
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cpld
value
rising edge
output register
clock signal
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CN114942901A (en
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张叶梅
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a serial coding method, a serial coding device, serial coding equipment and a readable medium, wherein the serial coding method comprises the following steps: assigning 1 to a CPLD code output register at the rising edge of each CPLD clock signal within a first threshold number; assigning a value to the encoding output register of the CPLD according to the value of the SDA data at the rising edge of each CPLD clock signal within the second threshold value number to encode the SDA data; assigning a value to the encoding output register of the CPLD according to the value of the SCL data at the rising edge of each CPLD clock signal within the third threshold value number to encode the SCL data; assigning a value to a CPLD code output register according to the value of the 5V signal data at the rising edge of each CPLD clock signal in the fourth threshold number to code the 5V signal; and assigning a value of 0 to the encoded output register of the CPLD at the rising edge of each CPLD clock signal within the fifth threshold value number, and repeating the steps. By using the scheme of the invention, the method has the advantages of simple coding mode, stable transmission and low decoding error rate.

Description

Method, device, equipment and readable medium for serial coding
Technical Field
The present invention relates to the field of computers, and more particularly to a method, apparatus, device and readable medium for serial encoding.
Background
The conventional HDMI (high definition multimedia interface) extender transmits by using an analog signal, and the farther the transmission distance is, the stronger the attenuation degree is, and the data transmission of several hundred meters cannot be satisfied. The new technology adopts an optical fiber mode for remote transmission, and a controller at a receiving and transmitting end is responsible for encoding serial signals into parallel signals and decoding the serial signals into the parallel signals. Serial coding defines that a data stream consisting of 1 and 0 is transmitted on a transmission channel, and generally includes a frame header, a data bit and a frame tail, and an unreasonable coding mode can cause difficulty in decoding due to clock offset and other problems, so that communication is unstable.
The 8B/10B coding is a coding mode commonly used in the current high-speed serial communication, the coding mode aims at direct current balance, 8bit original data can be divided into two parts, the lower 5 bits of the 8bit original data can be subjected to 5B/6B coding, the upper 3 bits of the 8bit original data can be subjected to 3B/4B coding, and the two mapping relations become a standardized table at the moment. One would like to represent 8bit data in the form dx.y, with x=5 LSB (least significant bit least significant bit), y=3 MSB (most significant bit most significant bit). However, the coding specifications such as 8b/10b are too complex to be suitable for CPLD with limited resources.
Disclosure of Invention
In view of the above, an object of the embodiments of the present invention is to provide a serial encoding method, apparatus, device and readable medium, which have the advantages of simple encoding mode, stable transmission and low decoding error rate by using the technical scheme of the present invention.
Based on the above object, an aspect of an embodiment of the present invention provides a method of serial encoding, including the steps of:
assigning 1 to a code output register of the CPLD at the rising edge of each CPLD clock signal within a first threshold number to form a frame header;
assigning a value to the encoding output register of the CPLD according to the value of the SDA data at the rising edge of each CPLD clock signal within the second threshold value number to encode the SDA data;
assigning a value to the encoding output register of the CPLD according to the value of the SCL data at the rising edge of each CPLD clock signal within the third threshold value number to encode the SCL data;
assigning a value to a CPLD code output register according to the value of the 5V signal data at the rising edge of each CPLD clock signal in the fourth threshold number to code the 5V signal;
the rising edge of each CPLD clock signal within the fifth threshold number assigns a value of 0 to the encoded output register of the CPLD to form the end of frame, and the above steps are repeated.
According to one embodiment of the invention, assigning the value of the encoded output register of the CPLD to encode the SDA data in accordance with the value of the SDA data at the rising edge of each CPLD clock signal within the second threshold number comprises:
in response to the value of the SDA data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the second threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD.
According to one embodiment of the invention, assigning the value of the encoded output register of the CPLD to encode the SCL data in accordance with the value of the SCL data at the rising edge of each CPLD clock signal within the third threshold number comprises:
in response to the value of SCL data being 0, the rising edge of the last CPLD clock signal in the third threshold number assigns a 1 to the encoded output register of the CPLD, and the rising edge of each other CPLD clock signal assigns a 0 to the encoded output register of the CPLD.
According to one embodiment of the invention, assigning a value to the CPLD's encoded output register to encode the 5V signal in accordance with the value of the 5V signal data at the rising edge of each CPLD clock signal within the fourth threshold number comprises:
in response to the value of the 5V signal data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the fourth threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD.
In another aspect of an embodiment of the present invention, there is also provided an apparatus for serial encoding, including:
a first encoding module configured to assign 1 to the CPLD's encoded output register at a rising edge of each CPLD clock signal within a first threshold number to form a frame header;
the second encoding module is configured to assign a value to the encoding output register of the CPLD according to the value of the SDA data at the rising edge of each CPLD clock signal within a second threshold number so as to encode the SDA data;
a third encoding module configured to assign a value to the encoding output register of the CPLD in accordance with the value of the SCL data at a rising edge of each CPLD clock signal within a third threshold number to encode the SCL data;
a fourth encoding module configured to assign a value to the encoding output register of the CPLD according to the value of the 5V signal data at the rising edge of each CPLD clock signal within a fourth threshold number to encode the 5V signal;
and a fifth encoding module configured to assign 0 to the CPLD's encoded output register at the rising edge of each CPLD clock signal within a fifth threshold number to form a frame end, and repeat the above steps.
According to an embodiment of the invention, the second encoding module is further configured to:
in response to the value of the SDA data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the second threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD.
According to an embodiment of the invention, the third encoding module is further configured to:
in response to the value of SCL data being 0, the rising edge of the last CPLD clock signal in the third threshold number assigns a 1 to the encoded output register of the CPLD, and the rising edge of each other CPLD clock signal assigns a 0 to the encoded output register of the CPLD.
According to an embodiment of the invention, the fourth encoding module is further configured to:
in response to the value of the 5V signal data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the fourth threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD.
In another aspect of the embodiments of the present invention, there is also provided a computer apparatus including:
at least one processor; and
and a memory storing computer instructions executable on the processor, the instructions when executed by the processor performing the steps of any of the methods described above.
In another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of any of the methods described above.
The invention has the following beneficial technical effects: the serial coding method provided by the embodiment of the invention is characterized in that a 1 is assigned to a CPLD coding output register through the rising edge of each CPLD clock signal in a first threshold number to form a frame header; assigning a value to the encoding output register of the CPLD according to the value of the SDA data at the rising edge of each CPLD clock signal within the second threshold value number to encode the SDA data; assigning a value to the encoding output register of the CPLD according to the value of the SCL data at the rising edge of each CPLD clock signal within the third threshold value number to encode the SCL data; assigning a value to a CPLD code output register according to the value of the 5V signal data at the rising edge of each CPLD clock signal in the fourth threshold number to code the 5V signal; the rising edge of each CPLD clock signal in the fifth threshold number assigns 0 to the encoding output register of the CPLD to form a frame tail, and the technical scheme of repeating the steps is that the encoding mode is concise, the transmission is stable, and the decoding error rate is low.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method of serial encoding according to one embodiment of the invention;
FIG. 2 is a schematic diagram of an apparatus for serial encoding according to one embodiment of the invention;
FIG. 3 is a schematic diagram of a computer device according to one embodiment of the invention;
fig. 4 is a schematic diagram of a computer-readable storage medium according to one embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
With the above object in view, there is provided, in a first aspect of an embodiment of the present invention, an embodiment of a method of serial encoding. Fig. 1 shows a schematic flow chart of the method.
As shown in fig. 1, the method may include the steps of:
s1 assigns a 1 to the CPLD' S encoded output register at the rising edge of each CPLD clock signal within a first threshold number to form a frame header. The first threshold number is 4, i.e. the value in the register after each of the rising edges of the 4 CPLD clock signals assigns 1 to the encoded output register of the CPLD, e.g. 4 clock signals, is 1111.TX_SO is the encoded output register of the CPLD at the transmitting end, clk_cnt is the count register, and the count register can be used to count the rising edges.
S2, assigning a value to a coding output register of the CPLD according to the value of the SDA data at the rising edge of each CPLD clock signal within the second threshold value number to code the SDA data. The second threshold number is 4, i.e. the encoded output register of the CPLD is assigned on each of the rising edges of the 4 CPLD clock signals, which follow the upper 4 clock signals, e.g. 4 clock signals in this step, the value in the register is 11110001, according to the value of the SDA data.
S3, assigning a value to the encoding output register of the CPLD according to the value of the SCL data at the rising edge of each CPLD clock signal within the third threshold value number to encode the SCL data. The third threshold number is 4, i.e. the encoded output register of the CPLD is assigned on each of the rising edges of the 4 CPLD clock signals, which follow the upper 4 clock signals, e.g. 4 clock signals in this step, the value in the register is 111100010001, according to the value of the SCL data.
S4, assigning a value to a CPLD coding output register according to the value of 5V signal data at the rising edge of each CPLD clock signal in the fourth threshold value number to code the 5V signal. The fourth threshold number is 4, i.e. the encoded output register of the CPLD is assigned at each of the rising edges of the 4 CPLD clock signals, which are followed by the upper 4 clock signals, e.g. 4 clock signals in this step, the value in the register is 1111000100010001, according to the value of the 5V signal data.
S5, assigning 0 to the CPLD code output register at the rising edge of each CPLD clock signal in the fifth threshold value number to form a frame tail, and repeating the steps. The fifth threshold number is 4, i.e., the encoded output register of the CPLD is assigned a value of 0 at each of the rising edges of the 4 CPLD clock signals that follow the 4 clock signals above, e.g., the value in the register is 11110001000100010000 after the 4 clock signals in this step. The above steps are then repeated, e.g. the next clock signal starts and a new frame header is formed. The CPLD at the receiving end can obtain the needed data signal by decoding according to the encoding method. The method is particularly suitable for encoding CPLD with limited resources.
The technical scheme of the invention has the advantages of simple coding mode, stable transmission and low decoding error rate.
In a preferred embodiment of the present invention, the assigning the value of the encoded output register of the CPLD to encode the SDA data in accordance with the value of the SDA data at the rising edge of each CPLD clock signal within the second threshold number comprises:
in response to the value of the SDA data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the second threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD. The clk_cnt register accumulates 1 on the rising edge of clk (clock signal of CPLD), and when clk_cnt is equal to 0, the input SDA signal is determined to be 0, tx_so is assigned 0, and if 1, tx_so is assigned 1. When clk_cnt is equal to 1, if the input SDA signal is judged to be equal to 0, TX_SO is assigned to 0, and if the input SDA signal is equal to 1, TX_SO is assigned to 1. When clk_cnt is equal to 2, judging that if clk_cnt is equal to 0, assigning TX_SO to 0; if equal to 1, TX_SO is assigned to 1. When clk_cnt is equal to 3, if the input SDA signal is equal to 0, TX_SO is assigned to 1; if equal to 1, TX_SO is assigned 0 and clk_cnt is assigned 0. That is, in the rising edge of 4 clock signals, if the SDA signal is 0, the value of the register is 0001, and if the SDA signal is 1, the value of the register is 1110.
In a preferred embodiment of the present invention, assigning the value of the encoding output register of the CPLD to encode the SCL data in accordance with the value of the SCL data at the rising edge of each CPLD clock signal within the third threshold number comprises:
in response to the value of SCL data being 0, the rising edge of the last CPLD clock signal in the third threshold number assigns a 1 to the encoded output register of the CPLD, and the rising edge of each other CPLD clock signal assigns a 0 to the encoded output register of the CPLD. The clk_cnt register accumulates 1 on the rising edge of clk, and when clk_cnt is equal to 0, the input SCL signal is asserted to be 0 if it is equal to 0, and to be 1 if it is equal to 1. When clk_cnt is equal to 1, the input SCL signal is asserted to be 0 if it is equal to 0, and to be 1 if it is equal to 1. When clk_cnt is equal to 2, the input SCL signal is asserted to assign 0 to TX_SO if it is equal to 0, and to assign 1 to TX_SO if it is equal to 1. When clk_cnt is equal to 3, if the input SDA signal is judged to be equal to 0, TX_SO is assigned to 1, if the input SDA signal is equal to 1, TX_SO is assigned to 0, and clk_cnt is assigned to 0. That is, on the rising edge of 4 clock signals, the register value is 0001 if the SCL signal is 0, and 1110 if the SCL signal is 1.
In a preferred embodiment of the present invention, assigning the value of the encoded output register of the CPLD to encode the 5V signal according to the value of the 5V signal data at the rising edge of each CPLD clock signal within the fourth threshold number comprises:
in response to the value of the 5V signal data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the fourth threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD. The clk_cnt register accumulates 1 on the rising edge of clk, and when clk_cnt is equal to 0, the input 5V signal is asserted to be 0 if it is equal to 0, and to be 1 if it is equal to 1. When clk_cnt is equal to 1, if the input 5V signal is judged to be equal to 0, TX_SO is assigned to 0, and if the input 5V signal is equal to 1, TX_SO is assigned to 1. When clk_cnt is equal to 2, if the input 5V signal is judged to be equal to 0, TX_SO is assigned to 0, and if the input 5V signal is equal to 1, TX_SO is assigned to 1. When clk_cnt is equal to 3, if the input 5V signal is judged to be equal to 0, TX_SO is assigned to 1, if the input 5V signal is equal to 1, TX_SO is assigned to 0, and clk_cnt is assigned to 0. That is, in the rising edge of 4 clock signals, if the 5V signal data is 0, the value of the register is 0001, and if the 5V signal data is 1, the value of the register is 1110.
The technical scheme of the invention has the advantages of simple coding mode, stable transmission and low decoding error rate.
It should be noted that, it will be understood by those skilled in the art that all or part of the procedures in implementing the methods of the above embodiments may be implemented by a computer program to instruct related hardware, and the above program may be stored in a computer readable storage medium, and the program may include the procedures of the embodiments of the above methods when executed. Wherein the storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), or the like. The computer program embodiments described above may achieve the same or similar effects as any of the method embodiments described above.
Furthermore, the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a CPU, which may be stored in a computer-readable storage medium. When executed by a CPU, performs the functions defined above in the methods disclosed in the embodiments of the present invention.
With the above object in view, in a second aspect, an apparatus for serial encoding is provided according to an embodiment of the present invention, as shown in fig. 2, an apparatus 200 includes:
the acquisition module is configured to acquire the basic information of each intelligent network card of the server and store the basic information into the BMC of the server;
a first encoding module configured to assign 1 to the CPLD's encoded output register at a rising edge of each CPLD clock signal within a first threshold number to form a frame header;
the second encoding module is configured to assign a value to the encoding output register of the CPLD according to the value of the SDA data at the rising edge of each CPLD clock signal within a second threshold number so as to encode the SDA data;
a third encoding module configured to assign a value to the encoding output register of the CPLD in accordance with the value of the SCL data at a rising edge of each CPLD clock signal within a third threshold number to encode the SCL data;
a fourth encoding module configured to assign a value to the encoding output register of the CPLD according to the value of the 5V signal data at the rising edge of each CPLD clock signal within a fourth threshold number to encode the 5V signal;
and a fifth encoding module configured to assign 0 to the CPLD's encoded output register at the rising edge of each CPLD clock signal within a fifth threshold number to form a frame end, and repeat the above steps.
In a preferred embodiment of the invention, the second encoding module is further configured to:
in response to the value of the SDA data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the second threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD.
In a preferred embodiment of the invention, the third encoding module is further configured to:
in response to the value of SCL data being 0, the rising edge of the last CPLD clock signal in the third threshold number assigns a 1 to the encoded output register of the CPLD, and the rising edge of each other CPLD clock signal assigns a 0 to the encoded output register of the CPLD.
In a preferred embodiment of the invention, the fourth encoding module is further configured to:
in response to the value of the 5V signal data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the fourth threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD.
Based on the above object, a third aspect of the embodiments of the present invention proposes a computer device. Fig. 3 is a schematic diagram of an embodiment of a computer device provided by the present invention. As shown in fig. 3, an embodiment of the present invention includes the following means: at least one processor 21; and a memory 22, the memory 22 storing computer instructions 23 executable on the processor, the instructions when executed by the processor performing the method of:
assigning 1 to a code output register of the CPLD at the rising edge of each CPLD clock signal within a first threshold number to form a frame header;
assigning a value to the encoding output register of the CPLD according to the value of the SDA data at the rising edge of each CPLD clock signal within the second threshold value number to encode the SDA data;
assigning a value to the encoding output register of the CPLD according to the value of the SCL data at the rising edge of each CPLD clock signal within the third threshold value number to encode the SCL data;
assigning a value to a CPLD code output register according to the value of the 5V signal data at the rising edge of each CPLD clock signal in the fourth threshold number to code the 5V signal;
the rising edge of each CPLD clock signal within the fifth threshold number assigns a value of 0 to the encoded output register of the CPLD to form the end of frame, and the above steps are repeated.
In a preferred embodiment of the present invention, the assigning the value of the encoded output register of the CPLD to encode the SDA data in accordance with the value of the SDA data at the rising edge of each CPLD clock signal within the second threshold number comprises:
in response to the value of the SDA data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the second threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD.
In a preferred embodiment of the present invention, assigning the value of the encoding output register of the CPLD to encode the SCL data in accordance with the value of the SCL data at the rising edge of each CPLD clock signal within the third threshold number comprises:
in response to the value of SCL data being 0, the rising edge of the last CPLD clock signal in the third threshold number assigns a 1 to the encoded output register of the CPLD, and the rising edge of each other CPLD clock signal assigns a 0 to the encoded output register of the CPLD.
In a preferred embodiment of the present invention, assigning the value of the encoded output register of the CPLD to encode the 5V signal according to the value of the 5V signal data at the rising edge of each CPLD clock signal within the fourth threshold number comprises:
in response to the value of the 5V signal data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the fourth threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD.
Based on the above object, a fourth aspect of the embodiments of the present invention proposes a computer-readable storage medium. Fig. 4 is a schematic diagram of an embodiment of a computer-readable storage medium provided by the present invention. As shown in fig. 4, the computer-readable storage medium 31 stores a computer program 32 that, when executed by a processor, performs the method as described above.
Furthermore, the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. The above-described functions defined in the methods disclosed in the embodiments of the present invention are performed when the computer program is executed by a processor.
Furthermore, the above-described method steps and system units may also be implemented using a controller and a computer-readable storage medium storing a computer program for causing the controller to implement the above-described steps or unit functions.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or general purpose or special purpose processor. Further, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.

Claims (10)

1. A method of serial encoding comprising the steps of:
assigning 1 to a code output register of the CPLD at the rising edge of each CPLD clock signal within a first threshold number to form a frame header;
assigning a value to the encoding output register of the CPLD according to the value of the SDA data at the rising edge of each CPLD clock signal within the second threshold value number to encode the SDA data;
assigning a value to the encoding output register of the CPLD according to the value of the SCL data at the rising edge of each CPLD clock signal within the third threshold value number to encode the SCL data;
assigning a value to a CPLD code output register according to the value of the 5V signal data at the rising edge of each CPLD clock signal in the fourth threshold number to code the 5V signal;
the rising edge of each CPLD clock signal within the fifth threshold number assigns a value of 0 to the encoded output register of the CPLD to form the end of frame, and the above steps are repeated.
2. The method of claim 1, wherein assigning the encoded output register of the CPLD to encode the SDA data according to the value of the SDA data at the rising edge of each CPLD clock signal within the second threshold number comprises:
in response to the value of the SDA data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the second threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD.
3. The method of claim 1, wherein assigning the encoding output register of the CPLD to encode the SCL data according to the value of the SCL data at the rising edge of each CPLD clock signal within the third threshold number comprises:
in response to the value of SCL data being 0, the rising edge of the last CPLD clock signal in the third threshold number assigns a 1 to the encoded output register of the CPLD, and the rising edge of each other CPLD clock signal assigns a 0 to the encoded output register of the CPLD.
4. The method of claim 1, wherein assigning a value to the CPLD's encoded output register to encode the 5V signal based on the value of the 5V signal data at the rising edge of each CPLD clock signal within the fourth threshold number comprises:
in response to the value of the 5V signal data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the fourth threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD.
5. An apparatus for serial encoding, the apparatus comprising:
a first encoding module configured to assign 1 to the CPLD's encoded output register at a rising edge of each CPLD clock signal within a first threshold number to form a frame header;
a second encoding module configured to assign a value to the encoding output register of the CPLD according to the value of the SDA data at a rising edge of each CPLD clock signal within a second threshold number to encode the SDA data;
a third encoding module configured to assign a value to the encoding output register of the CPLD in accordance with the value of the SCL data at a rising edge of each CPLD clock signal within a third threshold number to encode the SCL data;
a fourth encoding module configured to assign a value to the encoding output register of the CPLD according to the value of the 5V signal data at the rising edge of each CPLD clock signal within a fourth threshold number to encode the 5V signal;
and a fifth encoding module configured to assign 0 to the CPLD's encoded output register at the rising edge of each CPLD clock signal within a fifth threshold number to form a frame end, and repeat the above steps.
6. The apparatus of claim 5, wherein the second encoding module is further configured to:
in response to the value of the SDA data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the second threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD.
7. The apparatus of claim 5, wherein the third encoding module is further configured to:
in response to the value of SCL data being 0, the rising edge of the last CPLD clock signal in the third threshold number assigns a 1 to the encoded output register of the CPLD, and the rising edge of each other CPLD clock signal assigns a 0 to the encoded output register of the CPLD.
8. The apparatus of claim 5, wherein the fourth encoding module is further configured to:
in response to the value of the 5V signal data being 0, the rising edge of the last CPLD clock signal assigns a 1 to the encoded output register of the CPLD within the fourth threshold number, and the rising edge of each of the other CPLD clock signals assigns a 0 to the encoded output register of the CPLD.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of any one of claims 1-4.
10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method of any of claims 1-4.
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