CN114924615B - Memory clock adjusting method and device, electronic equipment and storage medium - Google Patents
Memory clock adjusting method and device, electronic equipment and storage medium Download PDFInfo
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- 238000004891 communication Methods 0.000 claims description 18
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- 230000005236 sound signal Effects 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000005070 sampling Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
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- 238000003384 imaging method Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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Abstract
The embodiment of the invention provides a memory clock adjusting method and device. The method comprises the following steps: when the specific register is set to different values, two adjacent clock cycles of a plurality of memory units are respectively acquired, the specific register is used for adjusting the jitter of the clock cycles, the difference value between the two adjacent clock cycles is calculated, the corresponding difference value of each memory unit when the specific register is set to different values is obtained, the target value of the specific register is determined according to the corresponding difference value of each memory unit when the specific register is set to different values, the absolute value of the difference value is smaller than or equal to a threshold value, the specific register is set to the target value, each main board can independently set the specific register to a value suitable for the main board according to the characteristics of the main board, the effect of reducing the absolute value of the difference value between the two adjacent clock cycles is achieved, the jitter of the clock cycles of the memory units is then reduced, the consistency of the clock cycles of the main boards in mass production is improved, and the main board stability test yield is improved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a memory clock adjustment method, a memory clock adjustment device, an electronic device, and a readable storage medium.
Background
At present, on a part of motherboard platforms, a double clock is used as a memory clock, and the double clock is a mode of digitally generating a secondary clock, which is generated by phase shifting a clock generated by a first stage PLL (Phase Locked Loop, phase-locked loop) by 90 degrees and then xoring to generate the secondary clock, so that every two clock cycles are accurate and stable, but different on-chip clock cycle jitter appears inconsistent for a single clock cycle.
In mass production of mainboards, clock cycles of different memory units are adjusted according to the same parameters, memory clock signals of some mainboards are good, and the problems of poor uniformity of the clock cycles of the mainboards and low test yield of the mainboards are caused by poor memory clock signals of some mainboards.
Disclosure of Invention
The embodiment of the invention aims to solve the technical problems of poor clock cycle consistency of a main board and low test yield of the stability of the main board by providing a memory clock adjusting method, a memory clock adjusting device, electronic equipment and a readable storage medium.
In order to solve the above problems, the present invention provides a memory clock adjustment method, including:
when a specific register is set to be different values, respectively acquiring two adjacent clock cycles of a plurality of memory units, wherein the specific register is used for adjusting the jitter of the clock cycles of the memory units;
calculating the difference value between the two adjacent clock cycles to obtain the corresponding difference value of each memory unit when the specific register is set to each different value;
determining a target value of the specific register according to the difference value corresponding to each memory unit when the specific register is set to each different value, so that the absolute value of the difference value between the two adjacent clock cycles is smaller than or equal to a threshold value when the specific register is set to the target value;
the specific register is set to the target value.
Optionally, when the specific register is set to each different value, acquiring two adjacent clock cycles of the plurality of memory units respectively includes:
setting the specific registers to a plurality of preset values one by one;
and when the specific register is set to each preset value, acquiring two adjacent clock cycles of each memory unit one by one.
Optionally, the calculating the difference between the two adjacent clock cycles to obtain the difference corresponding to each memory unit when the specific register is set to each different value includes:
after each acquisition of two adjacent clock cycles of a memory cell, the difference between the two adjacent clock cycles is calculated.
Optionally, the determining the target value of the specific register according to the difference value corresponding to each memory unit when the specific register is set to each different value includes:
for each memory unit, selecting the value set by the specific register when the absolute value of the corresponding difference value is minimum as a candidate value;
and selecting the candidate value with the largest occurrence number as the target value.
The invention also provides a memory clock adjusting device, which comprises:
the period acquisition module is used for respectively acquiring two adjacent clock periods of a plurality of memory units when a specific register is set to be different values, wherein the specific register is used for adjusting the jitter of the clock periods of the memory units;
the difference value calculation module is used for calculating the difference value between the two adjacent clock cycles to obtain the corresponding difference value of each memory unit when the specific register is set to each different value;
The target value determining module is used for determining a target value of the specific register according to the difference value corresponding to each memory unit when the specific register is set to be different values, so that the absolute value of the difference value between the two adjacent clock cycles is smaller than or equal to a threshold value when the specific register is set to be the target value;
and the target value setting module is used for setting the specific register as the target value.
Optionally, the period acquisition module includes:
a setting submodule, configured to set the specific registers to a plurality of preset values one by one;
and the period acquisition sub-module is used for acquiring two adjacent clock periods of each memory unit one by one when the specific register is set to each preset value.
Optionally, the difference calculating module includes:
and the difference value calculation sub-module is used for calculating the difference value between two adjacent clock cycles after each two adjacent clock cycles of one memory unit are acquired.
Optionally, the target value determining module includes:
the candidate value selecting submodule is used for selecting the value set by the specific register when the absolute value of the corresponding difference value is minimum for each memory unit as a candidate value;
And the target value selecting sub-module is used for selecting the candidate value with the largest occurrence number as the target value.
The embodiment of the invention also discloses an electronic device which is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;
a memory for storing a computer program;
and the processor is used for realizing one or more steps of the memory clock regulating method in the embodiment of the invention when executing the program stored in the memory.
The embodiment of the invention also discloses a readable storage medium, and when the instructions in the storage medium are executed by a processor of the electronic device, the electronic device can execute one or more of the memory clock adjustment methods in the embodiment of the invention.
According to the embodiment of the invention, when the specific register is set to be different values, two adjacent clock cycles of a plurality of memory units are respectively acquired, wherein the specific register is used for adjusting the jitter of the clock cycles of the memory units, calculating the difference value between the two adjacent clock cycles, obtaining the difference value corresponding to each memory unit when the specific register is set to be different values, determining the target value of the specific register according to the difference value corresponding to each memory unit when the specific register is set to be different values, enabling the absolute value of the difference value between the two adjacent clock cycles to be smaller than or equal to a threshold value when the specific register is set to be the target value, and setting the specific register to be the target value, so that each motherboard can be independently set to be suitable for own value according to the characteristics of own memory, thereby achieving the effect of reducing the absolute value of the difference value between the two adjacent clock cycles, further reducing the jitter of the clock cycles of the memory units, and improving the consistency of the clock cycles of the mass-produced motherboard and the stability test yield of the motherboard.
Drawings
FIG. 1 is a flowchart illustrating steps of a method for adjusting a memory clock according to an embodiment of the present invention;
FIG. 2 is a schematic diagram showing waveform comparison of clock cycles of memory cells provided by an example of the present invention before and after register setting;
FIG. 3 is a flowchart illustrating a method for adjusting a memory clock according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of an example memory clock adjustment process according to the present invention;
FIG. 5 is a block diagram illustrating an embodiment of a memory clock adjustment device according to another embodiment of the present invention;
fig. 6 illustrates a block diagram of an electronic device for memory clock adjustment, according to an example embodiment.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
The clock signal is added when the internal memory works, and the clock period of the internal memory unit represents the highest frequency that the internal memory can operate. A smaller clock period means a higher operating frequency. Because of the problem of clock cycle jitter, a special register is designed on the main board, and is used for adjusting the clock cycle jitter of each memory unit in the memory, which is called a specific register. The jitter of the clock cycles of the memory cells is adjusted according to the values in the specific registers. Therefore, for mass-produced memories, because of various reasons such as manufacturing errors existing in different memories of the same batch, if the specific registers are set to the same value, clock cycle jitter of memory units of some main board memories is smaller, clock signals are better, but the clock cycle jitter of the memory units of some main board memories is larger, the clock signals are worse, so that the main board clock cycle consistency is poor, and the main board stability test yield is low.
Fig. 1 is a flowchart illustrating steps of a memory clock adjustment method according to an embodiment of the present invention. Referring to fig. 1, the memory clock adjustment method provided in this embodiment may include the following steps:
step 101, when a specific register is set to each different value, two adjacent clock cycles of a plurality of memory units are respectively acquired, wherein the specific register is used for adjusting jitter of the clock cycles of the memory units.
In the embodiment of the invention, the value of a specific register is independently adjusted according to the characteristics of each memory. The memory clock adjustment method according to the embodiment of the present invention may be implemented by firmware, which may be UEFI or a conventional BIOS (basic input output system ) including PMON (Prom Monitor). The SECurity verification (SEC, SECurity) phase of UEFI (unified extensible firmware interface ) is the first phase of platform initialization, and the computer system should enter this phase after power-up or reboot, which mainly completes some basic configuration of the CPU, such as initializing memory, so that it can start running the code of UEFI. The embodiment of the invention provides a mechanism capable of adding the value of the automatic training specific register in the SEC stage of UEFI, so that each main board can independently set the specific register to be suitable for the value according to the characteristic of the internal memory of the main board. For PMON, the state of CPU can be initialized after power-on, namely the position of memory is initialized, and a mechanism for automatically training the value of a specific register is added. As an alternative, the firmware can train the value of the specific register on the flash memory (flash) of the main board when the firmware is started for the first time, the trained value is stored in the flash, and then the firmware is restarted to directly take the value out of the flash without training the value of the specific register, so that the time for initializing the memory is reduced. If the memory bank is found to be replaced, training is carried out again, then the value obtained after training is stored in the flash, and the previous value is covered.
In an embodiment of the invention, the settable value is a limited number of values for a particular register. To test which value a particular register is set to is best for the clock signal of the memory cell, it is necessary to set the particular register to all the settable values, respectively, or to set the particular register to a selected settable partial value, respectively. For example, the settable value may start from 0, each time +1, up to 0x3f, i.e. a maximum of 6 bits occupied at the register.
In the embodiment of the present invention, when setting the value of the specific register, the specific register may be set to different values sequentially from small to large, or may be set to different values sequentially from large to small, or may be set to different values according to a set order, or may be set to different values according to a random order, or any other applicable manner, which is not limited in this embodiment of the present invention.
In the embodiment of the present invention, when a specific register is set to one value, two adjacent clock cycles of a plurality of memory units are acquired, and when the specific register is set to another value, two adjacent clock cycles of the plurality of memory units are acquired.
For example, since every two clock cycles is accurate and stable, one clock cycle is denoted by T, and the duration of 2T is known. The theoretical duration of T is calculated using the known duration of 2T. The clock signal of the memory cell is sampled at a frequency of 128 times (or other times) per 1T of duration, and the interval between two adjacent samples is equal, i.e., each interval is T/128. The clock signal is 1, i.e. rising edges in the clock cycle, and the clock signal is 0, i.e. falling edges in the clock cycle. The number of clock signals sampled in the rising edge is 1 multiplied by the interval time, so that the duration of the rising edge can be obtained. The number of clock signals sampled in the falling edge is 0 multiplied by the interval time, so that the duration of the falling edge can be obtained. The rising and falling edges of equal duration form one clock cycle, the total duration of which, i.e. the duration of one clock cycle. The rising and falling edges following the clock cycle constitute adjacent clock cycles, the total duration of the rising and falling edges, i.e. the duration of an adjacent one of the clock cycles.
In an embodiment of the present invention, a memory is composed of a plurality of memory cells. Memory cells, also known as memory chips or memory granules, are the most core components in memory. The clock signal needs to be provided to each memory cell in the memory through the circuit. There may be inconsistencies in the clock cycles of multiple memory cells due to various reasons such as circuit design and manufacturing errors. Thus, for each memory cell, two adjacent clock cycles are acquired, respectively. That is, when the specific register is set to one value, two adjacent clock cycles of each memory cell are acquired respectively, and when the specific register is set to another value, two adjacent clock cycles of each memory cell are acquired respectively, and the above steps are repeated until the adjacent clock cycles of each memory cell are acquired when the specific register is set to a plurality of different values.
Step 102, calculating the difference between the two adjacent clock cycles to obtain the corresponding difference of each memory unit when the specific register is set to each different value.
In the embodiment of the invention, the difference between two adjacent clock cycles of each memory unit is calculated for each value set by a specific register. And finally obtaining the corresponding difference value of each memory unit when the specific register is set to each different value. For example, for two adjacent clock cycles, the preceding one is subtracted from the following one to obtain the difference.
In the embodiment of the present invention, when the difference between the two adjacent clock cycles is calculated to obtain the different values set by the specific register, the implementation manner of the difference corresponding to each memory unit may include various manners, for example, after each two adjacent clock cycles of one memory unit are obtained, the difference between the two adjacent clock cycles is calculated; or after acquiring two adjacent clock cycles of all the memory units, calculating a difference between the two adjacent clock cycles, or any other applicable manner, the embodiment of the present invention is not limited thereto.
And step 103, determining a target value of the specific register according to the difference value corresponding to each memory unit when the specific register is set to each different value, so that the absolute value of the difference value between the two adjacent clock cycles is smaller than or equal to a threshold value when the specific register is set to the target value.
In the embodiment of the invention, in order to reduce the jitter of the clock cycles of the memory unit, the absolute value of the difference between two adjacent clock cycles needs to be reduced, and the smaller the absolute value of the difference between two adjacent clock cycles is, the better. Based on this, for each motherboard, the specific register is individually set to a value suitable for itself according to the characteristics of the memory on the motherboard, specifically, the specific register is set to a value such that the absolute value of the difference between the adjacent two clock cycles is less than or equal to the threshold value.
The threshold may be determined according to actual needs, for example, the threshold is a minimum value, or the threshold is a second minimum value, which is not limited in the embodiment of the present invention. In the execution of the practical application, the threshold value does not necessarily need to be a truly existing parameter, for example, when a specific register is determined to be a certain value, the absolute value of the difference between two adjacent clock cycles is the smallest or the next smallest, that is, the effect that the absolute value of the difference between two adjacent clock cycles is smaller than or equal to the threshold value is achieved.
In the embodiment of the present invention, the specific implementation manner of determining the target value of the specific register may include multiple specific implementations according to the difference value corresponding to each memory unit when the specific register is set to each different value. For example, for each memory cell, the value set by the specific register when the corresponding absolute value is the smallest is selected as a candidate value, and then the candidate value with the largest occurrence number is selected as the target value. For another example, an average value of absolute values corresponding to respective memory cells when the specific register is set to respective values is calculated, and then a value set by the specific register corresponding to the smallest average value among them is set as the target value. For example, when the specific register is set to each value, the largest absolute value is selected, and the value set in the specific register when the largest absolute value is the smallest is set as the target value. And in particular may comprise any suitable implementation, to which embodiments of the invention are not limited.
And 104, setting the specific register as the target value.
In the embodiment of the present invention, after the target value is determined, a specific register is set as the target value. Thereafter, the clock cycle of the memory cell is modified based on the target value set in the particular register. The example of the present invention as shown in fig. 2 provides a schematic diagram of waveform comparison of clock cycles of a memory cell before and after register setting. Before the register is set, two adjacent clock cycles of the memory unit are 2T, and the lengths of the two adjacent clock cycles are greatly different. After the register is set, the adjacent two clock cycles of the memory cell are still 2T, but the length difference between the adjacent two clock cycles is small. That is, after the specific register is set to the target value, the jitter of the clock cycle of the memory cell is reduced.
According to the embodiment of the invention, when the specific register is set to be different values, two adjacent clock cycles of a plurality of memory units are respectively acquired, the specific register is used for adjusting the jitter of the clock cycles of the memory units, the difference value between the two adjacent clock cycles is calculated, when the specific register is set to be different values, the corresponding difference value of each memory unit is obtained, when the specific register is set to be different values, the corresponding difference value of each memory unit is determined, the target value of the specific register is determined, when the specific register is set to be the target value, the absolute value of the difference value between the two adjacent clock cycles is smaller than or equal to the threshold value, the specific register is set to be the target value, so that each motherboard can be independently set to be suitable for the value according to the characteristics of own memory, the effect of reducing the absolute value of the difference value between the two adjacent clock cycles is achieved, the jitter of the clock cycles of the memory units is then reduced, and the consistency of the clock cycles of mass production and the motherboard test yield are improved.
Fig. 3 is a flowchart illustrating a memory clock adjustment method according to another embodiment of the present invention. Referring to fig. 3, the memory clock adjustment method provided in this embodiment may include the following steps:
in step 201, the specific registers are set to a plurality of preset values one by one.
In the embodiment of the present invention, the preset value is a value that can be set by a specific register, and the preset value includes a plurality of values. Specific implementations of setting a particular register to a plurality of preset values one by one include a plurality of. For example, the preset values are set one by one in a set order. For another example, as shown in the schematic diagram of the memory clock adjustment flow shown in fig. 4, a specific register is set to a minimum preset value, after two adjacent clock cycles of a plurality of memory units (slices) are acquired one by one, a next preset value is obtained after adding one to the previous preset value, the specific register is set to the next preset value, two adjacent clock cycles of a plurality of memory units (slices) are acquired one by one again, and the above operation is performed in a circulating manner until the value in the specific register reaches a settable maximum value.
Step 202, when the specific register is set to each preset value, two adjacent clock cycles of each memory unit are acquired one by one.
In the embodiment of the present invention, in the process of setting a plurality of preset values one by one, when a specific register is set to each preset value, two adjacent clock cycles of each memory unit are acquired one by one. For example, as shown in fig. 4, after sampling one memory cell (slice (i)) for two adjacent clock cycles, i+1 is performed, and then the next memory cell is sampled until i exceeds a preset number, such as 8, i.e., all memory cells are sampled.
In step 203, after each two adjacent clock cycles of a memory cell are acquired, a difference between the two adjacent clock cycles is calculated.
In the embodiment of the invention, when the specific register is set to a certain preset value, after each two adjacent clock cycles of one memory unit are acquired, the difference value between the two adjacent clock cycles is calculated, and the two adjacent clock cycles of the next memory unit can be acquired after the difference value is recorded without recording the two adjacent clock cycles. Finally, when the specific register is set to different values, the corresponding difference value of each memory unit is obtained.
For example, as shown in fig. 4, after sampling adjacent clock cycles of one memory cell, comparing the two clock cycles to obtain an absolute value of the difference, recording the absolute value of the difference, and then sampling the next memory cell.
And 204, selecting the value set by the specific register when the absolute value of the corresponding difference value is minimum as a candidate value for each memory unit.
In the embodiment of the present invention, through the above steps, for each memory cell, each different value set by the specific register and the corresponding difference value or the absolute value of the difference value when the specific register is set to each different value are stored.
And selecting the value set by the specific register when the absolute value of the corresponding difference value is minimum as a candidate value for each memory unit. For example, as shown in fig. 4, the value set by the specific register corresponding to the minimum value of each slice is selected, that is, one slice corresponds to the value set by the selected specific register, and different slices correspond to the values set by the selected specific registers, which are the same and different.
And 205, selecting the candidate value with the largest occurrence number as the target value.
In the embodiment of the invention, one memory unit corresponds to one candidate value, and the candidate value with the largest occurrence number is selected as the target value. Thus, when a particular register is set to a target value, the absolute value of the difference between two adjacent clock cycles with the largest number of memory cells is minimized. In this manner, when the target value is determined, the threshold value of the difference between the adjacent two clock cycles may be the maximum value of the absolute value of the difference between the adjacent two clock cycles of each memory cell when the specific register is set as the target value, or the threshold value may include a plurality of threshold values, and for each memory cell, there may be a corresponding one of the threshold values, which may be the absolute value of the difference between the adjacent two clock cycles of the memory cell when the corresponding specific register is set as the target value. In this way, the selected target value may satisfy a condition that the absolute value of the difference between two adjacent clock cycles is less than or equal to the threshold value.
For example, as shown in fig. 4, for the value of the specific register selected correspondingly for each slice, the value with the largest number of occurrences is selected as the final value, that is, the target value.
Step 206, setting the specific register as the target value.
In the embodiments of the present invention, the specific implementation manner of this step may be referred to the description in the foregoing embodiments, which is not repeated herein.
According to the embodiment of the invention, the specific registers are set as a plurality of preset values one by one, when the specific registers are set as each preset value, two adjacent clock cycles of each memory unit are acquired one by one, after two adjacent clock cycles of one memory unit are acquired, the difference value between the two adjacent clock cycles is calculated, when the absolute value of the corresponding difference value is minimum for each memory unit, the value set by the specific registers is selected as a candidate value, the candidate value with the largest occurrence number is selected as the target value, and the specific registers are set as the target values, so that each main board can be independently set as a value suitable for the own according to the characteristics of the own memory, the effect that the absolute value of the difference value between the two adjacent clock cycles is minimum is achieved, the jitter of the clock cycles of the memory unit is reduced, and the consistency of the clock cycles of the main boards produced in batches and the main board stability test yield are improved.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
Referring to fig. 5, a block diagram of an embodiment of a memory clock adjusting device according to another embodiment of the present invention is shown, which may specifically include the following modules:
a period obtaining module 301, configured to obtain two adjacent clock periods of the plurality of memory units when a specific register is set to each different value, where the specific register is used to adjust jitter of the clock periods of the memory units;
the difference calculating module 302 is configured to calculate a difference between the two adjacent clock cycles, so as to obtain a difference corresponding to each memory unit when the specific register is set to each different value;
A target value determining module 303, configured to determine a target value of the specific register according to a difference value corresponding to each memory unit when the specific register is set to each different value, so that an absolute value of the difference value between the two adjacent clock cycles is less than or equal to a threshold value when the specific register is set to the target value;
a target value setting module 304, configured to set the specific register to the target value.
In an embodiment of the present invention, optionally, the period obtaining module includes:
a setting submodule, configured to set the specific registers to a plurality of preset values one by one;
and the period acquisition sub-module is used for acquiring two adjacent clock periods of each memory unit one by one when the specific register is set to each preset value.
In an embodiment of the present invention, optionally, the difference calculating module includes:
and the difference value calculation sub-module is used for calculating the difference value between two adjacent clock cycles after each two adjacent clock cycles of one memory unit are acquired.
In an embodiment of the present invention, optionally, the target value determining module includes:
the candidate value selecting submodule is used for selecting the value set by the specific register when the absolute value of the corresponding difference value is minimum for each memory unit as a candidate value;
And the target value selecting sub-module is used for selecting the candidate value with the largest occurrence number as the target value.
According to the embodiment of the invention, when the specific register is set to be different values, two adjacent clock cycles of a plurality of memory units are respectively acquired, the specific register is used for adjusting the jitter of the clock cycles of the memory units, the difference value between the two adjacent clock cycles is calculated, the corresponding difference value of each memory unit when the specific register is set to be different values is obtained, the target value of the specific register is determined according to the corresponding difference value of each memory unit when the specific register is set to be different values, the absolute value of the difference value between the two adjacent clock cycles is smaller than or equal to a threshold value when the specific register is set to be the target value, each motherboard can be independently set to be suitable for the own value according to the characteristics of the own memory, the effect of reducing the absolute value of the difference value between the two adjacent clock cycles is achieved, the jitter of the clock cycles of the memory units is then reduced, and the consistency of the clock cycles of the mass-produced masters and the stability test yield of the masters are improved.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
Fig. 6 is a block diagram illustrating an electronic device 700 for memory clock adjustment, according to an example embodiment. For example, the electronic device 700 may be a mobile phone, computer, digital broadcast terminal, messaging device, game console, tablet device, medical device, exercise device, personal digital assistant, or the like.
Referring to fig. 6, an electronic device 700 may include one or more of the following components: a processing component 702, a memory 704, a power component 706, a multimedia component 708, an audio component 710, an input/output (I/O) interface 712, a sensor component 714, and a communication component 716.
The processing component 702 generally controls overall operation of the electronic device 700, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 702 may include one or more processors 720 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 702 can include one or more modules that facilitate interaction between the processing component 702 and other components. For example, the processing component 702 may include a multimedia module to facilitate interaction between the multimedia component 708 and the processing component 702.
Memory 704 is configured to store various types of data to support operations at device 700. Examples of such data include instructions for any application or method operating on the electronic device 700, contact data, phonebook data, messages, pictures, video, and so forth. The memory 704 may be implemented by any type of volatile or non-volatile memory device or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.
The power supply component 706 provides power to the various components of the electronic device 700. Power supply components 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for electronic device 700.
The multimedia component 708 includes a screen between the electronic device 700 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may sense not only the boundary of a touch or slide action, but also the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 708 includes a front-facing camera and/or a rear-facing camera. When the electronic device 700 is in an operational mode, such as a shooting mode or a video mode, the front camera and/or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.
The audio component 710 is configured to output and/or input audio signals. For example, the audio component 710 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 700 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 704 or transmitted via the communication component 716. In some embodiments, the audio component 710 further includes a speaker for outputting audio signals.
The I/O interface 712 provides an interface between the processing component 702 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.
The sensor assembly 714 includes one or more sensors for providing status assessment of various aspects of the electronic device 700. For example, the sensor assembly 714 may detect an on/off state of the device 700, a relative positioning of the components, such as a display and keypad of the electronic device 700, a change in position of the electronic device 700 or a component of the electronic device 700, the presence or absence of a user's contact with the electronic device 700, an orientation or acceleration/deceleration of the electronic device 700, and a change in temperature of the electronic device 700. The sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 714 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 714 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 716 is configured to facilitate communication between the electronic device 700 and other devices, either wired or wireless. The electronic device 700 may access a wireless network based on a communication standard, such as WiFi, 2G, or 3G, or a combination thereof. In one exemplary embodiment, the communication component 716 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 716 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.
In an exemplary embodiment, the electronic device 700 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for executing the methods described above.
In an exemplary embodiment, a non-transitory computer readable storage medium is also provided, such as memory 704, including instructions executable by processor 720 of electronic device 700 to perform the above-described method. For example, the non-transitory computer readable storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.
A computer readable storage medium, which when executed by a processor of a terminal, causes the terminal to perform a memory clock adjustment method, the method comprising:
when a specific register is set to be different values, respectively acquiring two adjacent clock cycles of a plurality of memory units, wherein the specific register is used for adjusting the jitter of the clock cycles of the memory units;
calculating the difference value between the two adjacent clock cycles to obtain the corresponding difference value of each memory unit when the specific register is set to each different value;
determining a target value of the specific register according to the difference value corresponding to each memory unit when the specific register is set to each different value, so that the absolute value of the difference value between the two adjacent clock cycles is smaller than or equal to a threshold value when the specific register is set to the target value;
the specific register is set to the target value.
Optionally, when the specific register is set to each different value, two adjacent clock cycles of each memory unit are acquired respectively, and the specific register is used for adjusting jitter of the clock cycles of the memory units, including:
Setting the specific registers to a plurality of preset values one by one;
and when the specific register is set to each preset value, acquiring two adjacent clock cycles of a plurality of memory units one by one.
Optionally, the calculating the difference between the two adjacent clock cycles to obtain the difference corresponding to each memory unit when the specific register is set to each different value includes:
after each acquisition of two adjacent clock cycles of a memory cell, the difference between the two adjacent clock cycles is calculated.
Optionally, the determining the target value of the specific register according to the difference value corresponding to each memory unit when the specific register is set to each different value includes:
for each memory unit, selecting the value set by the specific register when the absolute value of the corresponding difference value is minimum as a candidate value;
and selecting the candidate value with the largest occurrence number as the target value.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The above description of the memory clock adjusting method and the memory clock adjusting device provided by the invention applies specific examples to illustrate the principles and embodiments of the invention, and the above examples are only used to help understand the method and core ideas of the invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (10)
1. A memory clock adjustment method, comprising:
when a specific register is set to be different values, respectively acquiring two adjacent clock cycles of a plurality of memory units, wherein the specific register is used for adjusting the jitter of the clock cycles of the memory units;
calculating the difference value between the two adjacent clock cycles to obtain the corresponding difference value of each memory unit when the specific register is set to each different value;
determining a target value of the specific register according to the difference value corresponding to each memory unit when the specific register is set to each different value, so that the absolute value of the difference value between the two adjacent clock cycles is smaller than or equal to a threshold value when the specific register is set to the target value;
the specific register is set to the target value to reduce jitter of clock cycles of the memory cells.
2. The method of claim 1, wherein each of the two adjacent clock cycles of the plurality of memory cells is acquired when the particular register is set to a respective different value, comprising:
setting the specific registers to a plurality of preset values one by one;
And when the specific register is set to each preset value, acquiring two adjacent clock cycles of each memory unit one by one.
3. The method of claim 2, wherein said calculating the difference between the adjacent two clock cycles to obtain the corresponding difference for each memory cell when the particular register is set to each different value comprises:
after each acquisition of two adjacent clock cycles of a memory cell, the difference between the two adjacent clock cycles is calculated.
4. The method of claim 1, wherein determining the target value of the particular register based on the difference value corresponding to each memory cell when the particular register is set to each different value comprises:
for each memory unit, selecting the value set by the specific register when the absolute value of the corresponding difference value is minimum as a candidate value;
and selecting the candidate value with the largest occurrence number as the target value.
5. A memory clock adjustment apparatus, comprising:
the period acquisition module is used for respectively acquiring two adjacent clock periods of a plurality of memory units when a specific register is set to be different values, wherein the specific register is used for adjusting the jitter of the clock periods of the memory units;
The difference value calculation module is used for calculating the difference value between the two adjacent clock cycles to obtain the corresponding difference value of each memory unit when the specific register is set to each different value;
a target value determining module, configured to determine a target value of the specific register according to a difference value corresponding to each memory unit when the specific register is set to each different value, so that an absolute value of the difference value between the two adjacent clock cycles is less than or equal to a threshold value when the specific register is set to the target value;
and the target value setting module is used for setting the specific register to the target value so as to reduce the jitter of the clock cycle of the memory unit.
6. The apparatus of claim 5, wherein the period acquisition module comprises:
a setting submodule, configured to set the specific registers to a plurality of preset values one by one;
and the period acquisition sub-module is used for acquiring two adjacent clock periods of each memory unit one by one when the specific register is set to each preset value.
7. The apparatus of claim 6, wherein the difference calculation module comprises:
And the difference value calculation sub-module is used for calculating the difference value between two adjacent clock cycles after each two adjacent clock cycles of one memory unit are acquired.
8. The apparatus of claim 5, wherein the target value determination module comprises:
the candidate value selecting submodule is used for selecting the value set by the specific register when the absolute value of the corresponding difference value is minimum for each memory unit as a candidate value;
and the target value selecting sub-module is used for selecting the candidate value with the largest occurrence number as the target value.
9. An electronic device comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus;
a memory for storing a computer program;
a processor for implementing the method steps of any one of claims 1-4 when executing a program stored on a memory.
10. A readable storage medium, characterized in that instructions in said storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the memory clock adjustment method according to one or more of the method claims 1-4.
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