CN1149159A - Disc matrix system integrating method - Google Patents

Disc matrix system integrating method Download PDF

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Publication number
CN1149159A
CN1149159A CN 96104467 CN96104467A CN1149159A CN 1149159 A CN1149159 A CN 1149159A CN 96104467 CN96104467 CN 96104467 CN 96104467 A CN96104467 A CN 96104467A CN 1149159 A CN1149159 A CN 1149159A
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China
Prior art keywords
slave
bus
host
code translator
address
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Granted
Application number
CN 96104467
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Chinese (zh)
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CN1060872C (en
Inventor
张江陵
金海�
周功业
张威
赵跃龙
周欣荣
冯丹
姚荻
汪振华
郭海宇
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Huazhong University of Science and Technology
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Huazhong University of Science and Technology
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Priority to CN96104467A priority Critical patent/CN1060872C/en
Publication of CN1149159A publication Critical patent/CN1149159A/en
Application granted granted Critical
Publication of CN1060872C publication Critical patent/CN1060872C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

An integrating method for disk array system is suitable to constitute storage system of computer with universal boards or cards and dedicated high-speed master-slave communication interfaces. The link and coordination of its units are realized by means of hardware and software. Router is used to implement parallel or concurrent operations between strings. Other techniques used include high-speed master-slave communication interface design, array control, cache manage and system scheduling.

Description

A kind of disc matrix system integrating method
The present invention relates to computer realm, be specially adapted to a kind of system integration occasion of use a computer general integrated circuit board and the master and slave communication interface formation of specialized high-speed computing machine external memory system.
American David Patterson summed up achievement in the past in 1987, the theory of structure disk array has at first been proposed, and six kinds of array structures such as 0,1,3,4,5 have been defined, some manufacturers have carried out the practicability exploitation later on, make and designed several disk array cards, these array control cards all are to use special chip to constitute, and it is unfavorable for upgrading along with the renewal of the innovation of computer science and technology and Control Software version, has limited the reduction of self usage range and cost.
At the shortcoming that above-mentioned prior art exists, task of the present invention provides a kind of system integration method of disk array.
The present invention implements by following measure.It is a kind of general calculation machine plate that utilizes, card and special-purpose high speed master, constitute the integrated approach of disk array system from communication interface, it is main at a high speed, connect with the bus of main frame 1 from communication interface 2 one ends, the other end connects with the bus 11 of slave, articulate the ROM (read-only memory) 3 that deposits Basic Input or Output System (BIOS) on the bus 11, the central processing unit 4 of slave, be used to deposit the static random-access memory 5 of block data, test monitoring equipment 7, the routing designator 6 that is used for the work of console panel array, read-only optical disc 10 and a plurality of series controller 8, series controller 8 one ends connect with bus 11, other end serial connection storage device 9.Described routing designator 6 presets 15 by the scheduling Buffer of instruction decode 16 address translation 17, command queuing 18, device drives 19, Cache and constitutes, instruction stream 13 and data stream 14 are through instruction decode 16 and address translation 17, preset at Cache scheduling and Buffer under 15 the control and carry out command queuing, drive through device drives 19 forming devices and order.Described high speed master, from communication interface 2, it is by dual port RAM 31, GAL34, host data impact damper 29, host address code translator 30, slave data buffer 35 and slave addresses code translator 36 constitute, host data impact damper 29 1 ends connect with host bus 23, the other end connects with twoport 31, host address code translator 30 1 ends connect with the low order address of host bus 23, the other end connects with twoport 31, host data impact damper and host address code translator choose high address line 25 by host bus, 26,27 through 34 realizations, slave data buffer one end connects with twoport 31, the other end connects with slave bus 43, one end of slave addresses code translator 36 connects with twoport 31, the other end connects with the low order address 37 of slave bus, slave data buffer 35 and slave addresses code translator 36 choose high-order ground bit lines 38 by the slave bus, 39,40,41 finish through 34.
Advantage of the present invention is: (1) adopts the general-purpose computations machine board card, connects by bus and equipment polyphone, realizes scheduling by routing designator.Except that routing designator, can use multiple general integrated circuit board to be beneficial to absorb the computing machine results new technology, reach the purpose that improves quality parameter and reduce cost; (2) systemic-function can arbitrarily be expanded, and is not subjected to the restriction of dedicated devices; (3) can articulate the combination of disc driver or CD drive or multiple memory device; (4) system scale and system architecture flexible variable help forming the series of products that are fit to the different user requirement; (5) owner's communication interface adopts non-standard high speed two-port RAM and communications protocol to realize having high data rate.
Description of drawings is as follows:
Accompanying drawing 1 system integration schematic diagram
Accompanying drawing 2 routing designators
The master and slave communication interface of accompanying drawing 3 high speeds.

Claims (3)

1. one kind is utilized the multi-purpose computer plate, card and special-purpose high speed master, constitute the integrated approach of disk array system from communication interface, it is characterized in that main at a high speed, connect with the bus of main frame (1) from communication interface (2) one ends, the other end connects with the bus (11) of slave, articulate the ROM (read-only memory) (3) of depositing Basic Input or Output System (BIOS) on the bus (11), the central processing unit of slave (4), be used to deposit the static random-access memory (5) of block data, test monitoring equipment (7), the routing designator (6) that is used for the work of console panel array, read-only optical disc (10) and a plurality of series controller (8), series controller (8) one ends connect with bus (11), other end serial connection storage device (9).
2. routing designator according to claim 1 (6), it is characterized by it is made of the scheduling of instruction decode (16), address translation (17), command queuing (18), device drives (19), Cache and preset (15) of Buffer, instruction stream (13) and data stream (14) are through instruction decode (16) and address translation (17), preset at scheduling and the Buffer of Cache under the control of (15) and carry out command queuing, drive order through device drives (19) forming device.
3. high speed master according to claim 1, from communication interface (2), it is characterized by by dual port RAM (31), GAL (34), host data impact damper (29), host address code translator (30), slave data buffer (35) and slave addresses code translator (36) constitute, host data impact damper (29) one ends connect with host bus (23), the other end connects with twoport (31), host address code translator (30) one ends connect with the low order address of host bus (23), the other end connects with twoport (31), host data impact damper and host address code translator choose high address line (25) by host bus, (26), (27), realize through (34), slave data buffer one end connects with twoport (31), the other end connects with slave bus (43), one end of slave addresses code translator (36) connects with twoport (31), the other end connects with the low order address (37) of slave bus, slave data buffer (35) and slave addresses code translator (36) choose high address line (38) by the slave bus, (39), (40), (41) finish through (34).
CN96104467A 1996-05-03 1996-05-03 Disc matrix system integrating method Expired - Fee Related CN1060872C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN96104467A CN1060872C (en) 1996-05-03 1996-05-03 Disc matrix system integrating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN96104467A CN1060872C (en) 1996-05-03 1996-05-03 Disc matrix system integrating method

Publications (2)

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CN1149159A true CN1149159A (en) 1997-05-07
CN1060872C CN1060872C (en) 2001-01-17

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CN96104467A Expired - Fee Related CN1060872C (en) 1996-05-03 1996-05-03 Disc matrix system integrating method

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100383721C (en) * 2006-05-12 2008-04-23 华中科技大学 Isomeric double-system bus objective storage controller
CN101344876B (en) * 2007-07-11 2011-05-11 台达电子工业股份有限公司 Operation method of master-slave mode extension plate system
CN105412257A (en) * 2015-12-15 2016-03-23 大连大学 Rhizoma corydalis pain-relieving particle and preparation method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5170472A (en) * 1991-03-28 1992-12-08 International Business Machines Corp. Dynamically changing a system i/o configuration definition
US5287462A (en) * 1991-12-20 1994-02-15 Ncr Corporation Bufferless SCSI to SCSI data transfer scheme for disk array applications

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100383721C (en) * 2006-05-12 2008-04-23 华中科技大学 Isomeric double-system bus objective storage controller
CN101344876B (en) * 2007-07-11 2011-05-11 台达电子工业股份有限公司 Operation method of master-slave mode extension plate system
CN105412257A (en) * 2015-12-15 2016-03-23 大连大学 Rhizoma corydalis pain-relieving particle and preparation method thereof

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CN1060872C (en) 2001-01-17

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C06 Publication
PB01 Publication
C14 Grant of patent or utility model
GR01 Patent grant
EE01 Entry into force of recordation of patent licensing contract

Assignee: Wuhan Haiheng Information Storage Co., Ltd.

Assignor: Wuhan Huazhong Science and technology large Industry Group Co Ltd

Contract fulfillment period: 2006.7.25 to 2023.8.8 contract change

Contract record no.: 2008420000001

Denomination of invention: Disc matrix system integrating method

Granted publication date: 20001125

License type: Exclusive license

Record date: 2008.5.28

LIC Patent licence contract for exploitation submitted for record

Free format text: EXCLUSIVE LICENCE; TIME LIMIT OF IMPLEMENTING CONTACT: 2006.7.25 TO 2023.8.8

Name of requester: WUHAN SEA OF INFORMATION STORAGE HENG CO.

Effective date: 20080528

C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee