CN1707404A - Universal bus interface structure and realizing method thereof - Google Patents
Universal bus interface structure and realizing method thereof Download PDFInfo
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- CN1707404A CN1707404A CN 200410025009 CN200410025009A CN1707404A CN 1707404 A CN1707404 A CN 1707404A CN 200410025009 CN200410025009 CN 200410025009 CN 200410025009 A CN200410025009 A CN 200410025009A CN 1707404 A CN1707404 A CN 1707404A
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Abstract
The present invention discloses one kind of general bus interface structure and its realizing method and is suitable for several kinds of bus standard. The general bus interface structure includes the following parts: one kernel processor; one data bus interface and one command bus interface in the same structure and connected to the kernel processor; and bus in specific standard and several pieces of bus equipment connected via data bus interface and command bus interface. Owing to the said technological scheme, the general bus interface structure and its realizing method of the present invention is suitable for several kinds of bus and bus equipment of different standards, has raised universality, and makes SOC design convenient.
Description
Technical field
The present invention relates to bus interface structure and its implementation, more particularly, relate to a kind of general character bus interface structure and its implementation.
Background technology
In the SOC design field, use multiple bus standard at present, comprising the AMBA of ARM company, the CoreConnect of IBM Corporation and the Wishbone of open standard.Owing to can not realize direct compatibility between three kinds of bus standards of person, therefore for the user, need adopt different designs for different bus standards, caused inconvenience therefrom.
In order to increase versatility, just need a kind of general character bus interface that can be applicable to multiple bus standard.
Summary of the invention
At above-mentioned defective of the prior art, the purpose of this invention is to provide a kind of general character bus interface structure and its implementation.So that this kind bus interface can be applied to various bus standard.
Basic technical scheme of the present invention be processor and adopt the bus of specific bus standard and bus apparatus between increase by a protocol layer, that this protocol layer will become from the data-switching of bus that adopts the specific bus standard and bus apparatus will be general, with the irrelevant data of concrete bus standard after transfer to processor processing again.Thus, for processor, the data of its processing will no longer the bus standard with concrete be relevant, thereby has realized the versatility for multiple bus standard.
The following technical scheme of the concrete employing of the present invention:
A kind of general character bus interface structure applicable to multiple bus standard, comprises following structure: a processor core; One data bus interface and an instruction bus interface, described data bus interface has identical structure with described instruction bus interface, and links to each other with described processor core; Adopt bus and several bus apparatus of specific criteria, link to each other with described instruction bus interface by described data bus interface with described processor core.
Described data bus interface in the described bus interface structure and instruction bus interface comprise the Memory Management Unit that is used for address translation, the interface unit that is used to preserve the buffer memory of nearest the most frequently used data or instruction and is used for the change over clock territory, wherein, described three parts are realized the bus of described processor core and described employing specific criteria and the memory access passage between several bus apparatus.
According to design proposal of the present invention, described Memory Management Unit is connected to an external memory storage, preserves address mapping table in the described external memory storage, and described address mapping table comprises physical address, access permission zone bit and buffer memory permission flag position at least; Described Memory Management Unit uses described address mapping table to carry out address mapping.Described buffer memory comprises two independently buffer memorys, and the size of each is the same with the page size of definition; The size of the row of described buffer memory is 16 words.And described interface unit is realized the conversion between memory clock territory and the microprocessor clock territory.
A kind of implementation method of general character bus interface structure, described general character bus interface is applicable to multiple bus standard, wherein, this method a processor core and adopt the bus of specific criteria and several bus apparatus between realize having a data bus interface of same structure and an instruction bus interface as the memory access passage, so that the bus of described processor core and described employing specific criteria and several bus apparatus can link to each other communicatedly by described two interfaces.
In the described implementation method, realize that data bus interface and instruction bus interface comprise that as the memory access passage realization is used for the Memory Management Unit of address translation, the interface unit that is used to preserve the buffer memory of nearest the most frequently used data or instruction and is used for the change over clock territory.
According to design proposal of the present invention, the realization Memory Management Unit comprises utilizes an address mapping table that is stored in the external memory storage to carry out the conversion of address; Wherein, described address mapping table comprises physical address, access permission zone bit and buffer memory permission flag position at least.The realization buffer memory comprises realizes two independently buffer memorys, and the size of each is the same with the page size of definition; The size of the row of the buffer memory of described realization is 16 words.Change and realize that interface unit is included between memory clock territory and the microprocessor clock territory.
Owing to adopted above-mentioned technical scheme, general character bus interface structure of the present invention and its implementation have increased versatility applicable to the bus and the bus apparatus of multiple standards, make the SOC design more convenient.
Description of drawings
Feature of the present invention, essence and advantage will be below become more obvious after in conjunction with the accompanying drawings and embodiments the description, wherein:
Fig. 1 is the block diagram of general character bus interface structure of the present invention;
Fig. 2 is the detailed diagram according to the general character bus interface of one embodiment of the present of invention;
Fig. 3 is the example according to the access cycle of general character bus interface of the present invention.
Embodiment
Further describe technical scheme of the present invention below in conjunction with accompanying drawing.
Main design philosophy of the present invention be with processor core at first be connected to two with the irrelevant summary interface of concrete bus standard, be data bus interface and instruction bus interface, be connected to bus and the bus apparatus that adopts concrete bus standard by these two interfaces more further.Thus, between processor core and bus and bus apparatus, form one deck intermediate protocol layer, this layer is used for the data conversion that meets the specific bus standard from bus is paired in the data of Unified Form the processor core, like this, angle from processor core, with regard to the difference of unnecessary consideration bus standard, like this, realized that by this interface the bus " abstract " with various various criterions is the general character bus.
According to one embodiment of the present of invention, adopt after the general character bus interface of the present invention, for processor core, its with two interfaces (data bus interface and instruction bus interface) between very simple of becoming of communicating by letter, with the data bus interface is example, only needs definition:
Be used for output signal
The request request of access
The address reference address
The output of dataout data
Bw visits granularity (1=byte, 0=word)
Rw read-write sign (1=reads, and 0=writes)
Be used for input signal
Wait waits for (the 1=data are not ready as yet, the 0=data ready)
The input of datain data
Just can realize data communication, for processor core, it needs no longer to consider whether data meet the standard of bus, therefore operation will obtain simplifying widely, design for SOC, user's direct control be processor core, therefore, the user equally no longer needs to consider the matching problem of various bus standards now, Fig. 3 is the example of an access cycle of this bus interface, and except above-mentioned various signals, clock is a clock signal, access request represents request of access, and acknowledge represents confirmation signal.
The following describes the structure and the implementation method of this bus interface.Shown in Figure 1 is according to the block diagram of the general character bus interface structure 100 of one embodiment of the present of invention, comprises following structure:
One processor core 102;
One data bus interface 104 and an instruction bus interface 106, data bus interface 104 has identical structure with instruction bus interface 106, and links to each other with processor core 102;
Adopt bus 108 and several bus apparatus 110 of specific criteria, link to each other with instruction bus interface 106 by data bus interface 104 with processor core 102; Wherein, the exchanges data between instruction bus interface 104 and the bus 108 is unidirectional, and the exchanges data between data bus interface 104 and the bus 108 is two-way.
In this embodiment, adopt the Wishbone interconnect architecture to realize interconnecting between the above-mentioned all devices.
Fig. 2 further illustrates the detailed block diagram of said structure, data bus interface 104 and instruction bus interface 106 comprise the Memory Management Unit that is used for address translation, the interface unit that is used to preserve the buffer memory of nearest the most frequently used data or instruction and is used for the change over clock territory, and these three parts are realized processor core and adopted the bus of specific criteria and the memory access passage between several bus apparatus.Among the embodiment as shown in Figure 2, processor core 102 wherein is EStarl Core, (MMU and buffer memory are illustrated as being placed in the same equipment herein for its connection data Memory Management Unit (MMU) and buffer memory 302, they also can be placed apart in different equipment), also link order MMU and buffer memory 304.By 302 and 304, processor core EStarl Core is connected to bus 310 (in this embodiment, be the Wishbone bus), as shown in Figure 2, bus 310 connects to start ROM306 and deposit controls storer (can be SRAM, SDRAM or FLASH) 308, starts ROM 306 and deposits the instruction of preserving when starting in the control storer 308 or needing in the operating process afterwards to use.It should be noted that command M MU is unidirectional with buffer memory 304 with being connected of bus 310.And data M MU is two-way with buffer memory 302 with being connected of bus 310.Among the embodiment as shown in Figure 2, bus 310 and be connected to dma controller 312.Bus 310 also is connected to bus 316 by Wishbone bridge 314, bus 316 connects a plurality of equipment, comprise interruptable controller 318, serial ports 320, LCD 322 and clock 324, they can both interrupt to processor core EStarl Core 102 requests by interruptable controller 318.
In structure shown in Figure 2, Memory Management Unit (MMU), buffer memory and interface unit have constituted storage channels jointly.Wherein, Memory Management Unit (MMU) is carried out the conversion of address, logical address is transformed to physical address, also check access permission and franchise attribute simultaneously, if current request haves no right to visit this address, it is unusual then can to produce ABT, and logical address of makeing mistakes and the reason of makeing mistakes can be saved for the ABT exception handler further inquires about.Buffer memory is deposited the most frequently used data recently, and the stand-by period when reducing the slow external memory of processor access, the control register of control buffer memory can be set in the coprocessor.Interface unit is used to carry out the conversion of clock zone, makes external memory storage can use identical clock with processor inside.
In the present invention, MMU provides map addresses and the protection mechanism for storer.This kind mechanism depends on the address mapping table work of leaving in the external memory storage, so MMU is connected to an external memory storage.In address mapping table, each list item has provided the attribute in corresponding address interval, comprising:
Physical address has provided the physics base address between the real address area of this list item correspondence.
The access permission zone bit, it points out which type of level of privilege is application program need and could visit this list item corresponding address interval.
Buffer memory permission flag position, it points out whether the interval, current address can use buffer memory (cache) and whether can use and write buffering (write buffer).
By the assistance of coprocessor, Memory Management Unit can use the address mapping table that comprises above-mentioned information to carry out address mapping.A sufficient address translation needs to visit the primary address mapping table at least, if the address in the secondary list item also needs secondary list item of extra access.In order to reduce to visit expense, the list item of normal use is buffered in this locality, and this has just produced TLB mechanism.After the address mapping changes, the part among the TLB, or even all list item all will lose efficacy, and at this moment, must the list item that lose efficacy be known by the list item mechanism of emptying TLB.On the other hand, in order to ensure key, can be kept at all the time among the TLB exigent code of real-time and data, must list item be locked among the TLB by list item mechanism, prevent that it is replaced.
Among the present invention, use two independently buffer memorys, it is included among the processor core EStarl, and they have following characteristic:
The size of each buffer memory is the same with the page size of definition, is 4KB, access cache and TLB concurrently, and needn't wait for the result of map addresses.
Use and directly hint obliquely at pattern, thereby reduce the time-delay of access cache and the complicacy of buffer memory.
Use physical address as Cache Tag, to prevent causing refreshing of unnecessary buffer memory owing to the variation of map addresses.
The size of the row of buffer memory is 16 words, and the row of relatively large buffer memory has reduced the time-delay and the complicacy of cache controller.Can utilize simultaneously the transmission mode of the high latency high bandwidth of outside SDRAM storer to greatest extent.
Use write back organizational form, have only when the row replacement takes place to be written back to external memory storage in the data that will be modified.
Interface unit among the present invention is realized the conversion between memory clock territory and the microprocessor clock territory.Because the running frequency of external memory storage is lower, well below the design dominant frequency of microprocessor.And memory controller must use the clock identical with external memory storage in use, so just need realize conversion between two clock zones.In Fig. 2, interface unit does not occur in the mode of an independent device.Those of ordinary skill in the art should be understood that the key of interface unit is that it provides a kind of mechanism of changing between clock zone.
By top description as can be known, general character interface structure of the present invention be in fact processor core and adopt the bus of certain specific criteria and bus apparatus between increase a protocol layer, the effect of this layer is to become a unified standard to offer processor core afterwards again the data on the bus of various various criterions " translation ", make processor core needn't consider the typical problem of bus thus, thereby reach general purpose.According to the present invention, above-mentioned protocol layer adopts a data bus interface and an instruction interface bus to realize.
The present invention also provides a kind of implementation method of general character bus interface structure, this general character bus interface promptly is the above-mentioned bus interface applicable to multiple bus standard, this method a processor core and adopt the bus of specific criteria and several bus apparatus between realize having a data bus interface of same structure and an instruction bus interface as the memory access passage, so that the bus of processor core and employing specific criteria and several bus apparatus can link to each other communicatedly by two interfaces; Wherein, adopt the Wishbone interconnect architecture to interconnect between the above-mentioned all devices.
It will be appreciated that, according to the general character bus interface that method of the present invention realized can be the structure that meets front embodiment described in conjunction with Figure 2, multiple variation that also can the foregoing description structure, as long as the bus interface that is realized meets following fundamental norms:
Realize data bus interface and instruction bus interface in this method as the memory access passage, comprise that the Memory Management Unit, the realization that realize being used for address translation are used to preserve the buffer memory of nearest the most frequently used data or instruction and the interface unit that realization is used for the change over clock territory.
Realization Memory Management Unit in this method comprises utilizes an address mapping table that is stored in the external memory storage to carry out the conversion of address; Wherein, address mapping table comprises physical address, access permission zone bit and buffer memory permission flag position at least.
The realization buffer memory comprises realizes two independently buffer memorys, and the size of each is the same with the page size of definition; The size of the row of the buffer memory of described realization is 16 words.
The realization interface unit is included between memory clock territory and the microprocessor clock territory to be changed.
As for the concrete means that realize, both can adopt special hardware circuit realization completely, also can be to be realized by programmable circuit, if use programmable circuit, described circuit should be configured according to rule described above, so that its principle according to the invention.
Owing to adopted above-mentioned technical scheme, general character bus interface structure of the present invention and its implementation have increased versatility applicable to the bus and the bus apparatus of multiple standards, make the SOC design more convenient.
The foregoing description provides to being familiar with the person in the art and realizes or use of the present invention; those skilled in the art can be under the situation that does not break away from invention thought of the present invention; the foregoing description is made various modifications or variation; thereby protection scope of the present invention do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.
Claims (10)
1. a general character bus interface structure applicable to multiple bus standard, is characterized in that, comprises following structure:
One processor core;
One data bus interface and an instruction bus interface, described data bus interface has identical structure with described instruction bus interface, and links to each other with described processor core;
Adopt bus and several bus apparatus of specific criteria, link to each other with described instruction bus interface by described data bus interface with described processor core.
2. bus interface structure as claimed in claim 1 is characterized in that,
Described data bus interface and instruction bus interface comprise the Memory Management Unit that is used for address translation, the interface unit that is used to preserve the buffer memory of nearest the most frequently used data or instruction and is used for the change over clock territory, wherein, described three parts are realized the bus of described processor core and described employing specific criteria and the memory access passage between several bus apparatus.
3. bus interface structure as claimed in claim 2 is characterized in that,
Described Memory Management Unit is connected to an external memory storage, preserves address mapping table in the described external memory storage, and described address mapping table comprises physical address, access permission zone bit and buffer memory permission flag position at least; Described Memory Management Unit uses described address mapping table to carry out address mapping.
4. bus interface structure as claimed in claim 2 is characterized in that,
Described buffer memory comprises two independently buffer memorys, and the size of each is the same with the page size of definition; The size of the row of described buffer memory is 16 words.
5. bus interface structure as claimed in claim 2 is characterized in that,
Described interface unit is realized the conversion between memory clock territory and the microprocessor clock territory.
6. the implementation method of a general character bus interface structure, described general character bus interface be applicable to multiple bus standard, wherein,
This method a processor core and adopt the bus of specific criteria and several bus apparatus between realize having a data bus interface of same structure and an instruction bus interface as the memory access passage, so that the bus of described processor core and described employing specific criteria and several bus apparatus can link to each other communicatedly by described two interfaces.
7. implementation method as claimed in claim 6 is characterized in that,
Realize that data bus interface and instruction bus interface comprise that as the memory access passage realization is used for the Memory Management Unit of address translation, the interface unit that is used to preserve the buffer memory of nearest the most frequently used data or instruction and is used for the change over clock territory.
8. implementation method as claimed in claim 7 is characterized in that,
The realization Memory Management Unit comprises utilizes an address mapping table that is stored in the external memory storage to carry out the conversion of address; Wherein, described address mapping table comprises physical address, access permission zone bit and buffer memory permission flag position at least.
9. implementation method as claimed in claim 7 is characterized in that,
The realization buffer memory comprises realizes two independently buffer memorys, and the size of each is the same with the page size of definition; The size of the row of the buffer memory of described realization is 16 words.
10. implementation method as claimed in claim 7 is characterized in that,
The realization interface unit is included between memory clock territory and the microprocessor clock territory to be changed.
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| CN 200410025009 CN1707404A (en) | 2004-06-09 | 2004-06-09 | Universal bus interface structure and realizing method thereof |
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| CN 200410025009 CN1707404A (en) | 2004-06-09 | 2004-06-09 | Universal bus interface structure and realizing method thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102169475A (en) * | 2010-02-08 | 2011-08-31 | 无锡中星微电子有限公司 | Processor and implementation method |
| CN102662894A (en) * | 2012-03-23 | 2012-09-12 | 中国航天科技集团公司第九研究院第七七一研究所 | General bus slave unit interface |
| CN101770442B (en) * | 2008-12-30 | 2012-10-10 | 易视芯科技(北京)有限公司 | Data interaction system with a plurality of external interfaces and method |
| CN107992439A (en) * | 2017-10-13 | 2018-05-04 | 武汉高德智感科技有限公司 | A kind of expansible data interactive method and system |
| US10198374B2 (en) | 2014-11-20 | 2019-02-05 | Sanechips Technology Co. Ltd. | Configurable on-chip interconnection system and method and apparatus for implementing same, and storage medium |
-
2004
- 2004-06-09 CN CN 200410025009 patent/CN1707404A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770442B (en) * | 2008-12-30 | 2012-10-10 | 易视芯科技(北京)有限公司 | Data interaction system with a plurality of external interfaces and method |
| CN102169475A (en) * | 2010-02-08 | 2011-08-31 | 无锡中星微电子有限公司 | Processor and implementation method |
| CN102662894A (en) * | 2012-03-23 | 2012-09-12 | 中国航天科技集团公司第九研究院第七七一研究所 | General bus slave unit interface |
| CN102662894B (en) * | 2012-03-23 | 2015-04-22 | 中国航天科技集团公司第九研究院第七七一研究所 | General bus slave unit interface |
| US10198374B2 (en) | 2014-11-20 | 2019-02-05 | Sanechips Technology Co. Ltd. | Configurable on-chip interconnection system and method and apparatus for implementing same, and storage medium |
| CN107992439A (en) * | 2017-10-13 | 2018-05-04 | 武汉高德智感科技有限公司 | A kind of expansible data interactive method and system |
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