WO2006085272A3 - Scalable universal serial bus architecture - Google Patents

Scalable universal serial bus architecture Download PDF

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Publication number
WO2006085272A3
WO2006085272A3 PCT/IB2006/050414 IB2006050414W WO2006085272A3 WO 2006085272 A3 WO2006085272 A3 WO 2006085272A3 IB 2006050414 W IB2006050414 W IB 2006050414W WO 2006085272 A3 WO2006085272 A3 WO 2006085272A3
Authority
WO
WIPO (PCT)
Prior art keywords
serial
coupled
serial bus
master scheduler
data
Prior art date
Application number
PCT/IB2006/050414
Other languages
French (fr)
Other versions
WO2006085272A2 (en
Inventor
Lee Chee Ee
Chee Yu Ng
Original Assignee
Koninkl Philips Electronics Nv
Philips Corp
Lee Chee Ee
Chee Yu Ng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Corp, Lee Chee Ee, Chee Yu Ng filed Critical Koninkl Philips Electronics Nv
Priority to JP2007553774A priority Critical patent/JP2008530650A/en
Priority to EP06727612A priority patent/EP1851640A2/en
Priority to CN2006800105331A priority patent/CN101180618B/en
Publication of WO2006085272A2 publication Critical patent/WO2006085272A2/en
Publication of WO2006085272A3 publication Critical patent/WO2006085272A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Computer And Data Communications (AREA)

Abstract

A serial bus interface circuit (100) for use in a computer comprises a master scheduler (120) configured to communicate serial data with the computer. A plurality of transfer controllers (130) are coupled to the master scheduler and configured to manage serial transactions. A router (140) has a number of ports coupled to the transfer controllers and selectively communicates serial data between selected ports. A plurality of serial interlaces (150) are coupled to the router and adapted for coupling to peripheral devices . In one embodiment, the serial bus interface circuit further comprises a transaction translator (160) coupled to a transfer controller and a serial interface, for normalizing the data speed. In another embodiment, the master scheduler (120) is coupled to a memory management unit (112) and communicates serial data with the memory management unit. Advantages of the invention include the ability to provide high-speed serial communication to multiple ports simultaneously.
PCT/IB2006/050414 2005-02-08 2006-02-08 Scalable universal serial bus architecture WO2006085272A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007553774A JP2008530650A (en) 2005-02-08 2006-02-08 Scalable universal serial bus architecture
EP06727612A EP1851640A2 (en) 2005-02-08 2006-02-08 Scalable universal serial bus architecture
CN2006800105331A CN101180618B (en) 2005-02-08 2006-02-08 Serial bus interface circuit and method for communicating with computer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US65142905P 2005-02-08 2005-02-08
US60/651,429 2005-02-08

Publications (2)

Publication Number Publication Date
WO2006085272A2 WO2006085272A2 (en) 2006-08-17
WO2006085272A3 true WO2006085272A3 (en) 2006-11-23

Family

ID=36793423

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2006/050414 WO2006085272A2 (en) 2005-02-08 2006-02-08 Scalable universal serial bus architecture

Country Status (5)

Country Link
EP (1) EP1851640A2 (en)
JP (1) JP2008530650A (en)
CN (1) CN101180618B (en)
TW (1) TW200642210A (en)
WO (1) WO2006085272A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1971923B1 (en) * 2006-01-04 2010-03-24 Freescale Semiconductor, Inc. Method for managing under-runs and a device having under-run management capabilities
CN102163180B (en) * 2011-01-20 2013-02-13 电子科技大学 I2C bus interface circuit module and control method thereof
JP2014081952A (en) * 2014-01-08 2014-05-08 Renesas Electronics Corp Host controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6199137B1 (en) * 1999-01-05 2001-03-06 Lucent Technolgies, Inc. Method and device for controlling data flow through an IO controller
US6256700B1 (en) * 1999-03-30 2001-07-03 Dell Usa, L.P. Bus/port switching system and method for a computer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6199137B1 (en) * 1999-01-05 2001-03-06 Lucent Technolgies, Inc. Method and device for controlling data flow through an IO controller
US6256700B1 (en) * 1999-03-30 2001-07-03 Dell Usa, L.P. Bus/port switching system and method for a computer

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"ISP1561 Hi-Speed USB PCI host controller, Rev. 01", 6 February 2003 (2003-02-06), pages 1 - 14, XP002397883, Retrieved from the Internet <URL:http://www.nxp.com/acrobat_download/datasheets/ISP1561-01.pdf> [retrieved on 20060906] *
USB WORKING GROUP: "Universal serial bus specification revision 2.0", UNIVERSAL SERIAL BUS SPECIFICATION, XX, XX, 27 April 2000 (2000-04-27), pages complete, XP002367214 *

Also Published As

Publication number Publication date
EP1851640A2 (en) 2007-11-07
JP2008530650A (en) 2008-08-07
CN101180618B (en) 2010-05-19
TW200642210A (en) 2006-12-01
WO2006085272A2 (en) 2006-08-17
CN101180618A (en) 2008-05-14

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