CN114913896A

CN114913896A - Phase change memory, control method and electronic device

Info

Publication number: CN114913896A
Application number: CN202110185639.1A
Authority: CN
Inventors: 陈一峰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-02-10
Filing date: 2021-02-10
Publication date: 2022-08-16

Abstract

The application discloses a phase change memory, a control method and electronic equipment, relates to the field of storage, and is used for reducing the time of writing and erasing operations of the phase change memory. The phase change memory comprises a control circuit and a memory block, wherein the memory block comprises a memory array, a word line selection circuit and a bit line selection circuit, the memory array comprises a plurality of memory cells, and each memory cell comprises a phase change material; the control circuit is used for controlling the word line selection circuit and the bit line selection circuit to select a plurality of memory cells of the memory array, and inputting a preset electric signal to the plurality of memory cells, wherein the preset electric signal enables the phase-change material of the plurality of memory cells to be in a pre-crystallization state, and the pre-crystallization state is an intermediate state between a crystallization state and an amorphous state of the phase-change material.

Description

Phase change memory, control method and electronic device

Technical Field

The present disclosure relates to the field of storage, and in particular, to a phase change memory, a control method, and an electronic device.

Background

Phase Change Memory (PCM) is a new type of semiconductor memory based on chalcogenide compounds. The principle of writing phase change memory is that the phase change material is rapidly raised above its melting temperature and quenched by applying an electrical pulse of high amplitude, short duration and rapid rising and falling edges to the phase change material, which remains in a high resistance amorphous state because microscopic atoms do not have enough time to complete crystallization. The principle of erase operation of phase change memory is that by applying a relatively low amplitude but relatively long duration electrical pulse to the phase change material, the temperature of the phase change material can be maintained above the crystallization temperature for a period of time below the melting temperature, thereby allowing sufficient time for crystallization to a low resistance polycrystalline state, and thus the erase operation (i.e., the crystallization process) is time consuming relative to the write operation.

Disclosure of Invention

The embodiment of the application provides a phase change memory, a control method and an electronic device, which are used for reducing the time of writing and erasing operations of the phase change memory.

In order to achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

in a first aspect, a phase change memory is provided, which includes a control circuit, a memory array, a signal generation circuit, a word line selection circuit, and a bit line selection circuit; each memory cell of the memory array comprises a word line gating device and a phase-change material which are coupled, wherein a word line of the memory array is coupled to a control end of the word line gating device, and a bit line of the memory array is coupled to the phase-change material; the signal generating circuit is used for generating a first signal and a second signal, wherein the first signal is smaller than a signal applied to a word line in the erasing operation and is larger than or equal to a threshold value for enabling the word line gating device to be conducted; the control circuit is to: in an electro-pre-crystallization operation before a write-erase operation is performed, a word line selection circuit is controlled to apply a first signal to a word line, and a bit line selection circuit is controlled to apply a second signal to a bit line to perform electro-pre-crystallization on a memory cell.

In the phase change memory provided by the embodiment of the application, before the write/erase operation, the control circuit selects the plurality of memory cells of the memory array by controlling the word line selection circuit and the bit line selection circuit, and inputs the preset electric signals to the plurality of memory cells, and the preset electric signals enable the phase change materials of the plurality of memory cells to be in the pre-crystallization state, so that a large number of conductive channels or crystallization nucleation centers are formed in the memory cells, and when the write/erase operation is performed subsequently, the crystallization can be realized in a short time, so that the write/erase operation can be completed more quickly, and the time of the write/erase operation of the phase change memory can be reduced.

In one possible implementation, the word line selection circuit includes a first full selection circuit, the bit line selection circuit includes a second full selection circuit, and the control circuit is used for controlling the first full selection circuit and the second full selection circuit to select a plurality of memory cells of the memory array. This embodiment provides a way of controlling how a circuit selects a plurality of memory cells of a memory array.

In a possible implementation manner, the preset electrical signal includes a first signal, the first full selection circuit includes a first switches, first ends of the a first switches are respectively coupled to a word lines of the memory array, and second ends of the a first switches are used for inputting the first signal; wherein A is a positive integer; the control circuit is specifically configured to: the a first switches are closed to apply the first signal to the a word lines. This embodiment provides a specific embodiment of how the control circuit controls the word line selection circuit to apply the first signal to the word line.

In one possible implementation, the word line selection circuit further includes a row address decoder, where a outputs of the row address decoder and first ends of the a first switches are respectively coupled to a word lines of the memory array; the control circuit is further configured to: when the a first switches are closed, the row address decoder is disabled. This embodiment enables the row address decoder output to be in a high impedance state so that the signal on the word line is not affected.

In one possible embodiment, the control circuit is further configured to: when the writing and erasing operation or the reading operation is carried out, the row address decoder is enabled, and the A first switches are disconnected. This embodiment can multiplex the circuits on the word line side to realize normal write-erase operation or read operation and electro-pre-crystallization operation.

In one possible implementation, the first signal is less than the signal applied to the word line during the erase operation and is greater than or equal to a threshold at which a word line gating device of the memory array is turned on. That is, it is sufficient to ensure that the word line gating device of the memory array is turned on.

In one possible embodiment, the preset electrical signal comprises a second signal, and the second full selection circuit comprises B second switches and B data selectors; the first ends of the B second switches are respectively coupled to the control ends of the B data selectors; the fixed ends of the B data selectors are coupled to the B bit lines of the storage array, and the first movable ends of the B data selectors are used for inputting second signals; wherein B is a positive integer; the control circuit is to: the B second switches are closed and control signals are input to second terminals of the B second switches to couple fixed terminals of the B data selectors with the first active terminals to apply second signals to the B bit lines. This embodiment provides a specific embodiment of how the control circuit controls the bitline selection circuit to apply the second signal to the bitline.

In a possible implementation manner, the bit line selection circuit further includes a column address decoder, B output terminals of the column address decoder and first terminals of the B second switches are respectively coupled to the control terminals of the B data selectors; the control circuit is further configured to: when the B second switches are closed, the column address decoder is disabled. This embodiment enables the column address decoder output to be in a high impedance state so as not to affect the signals on the address signal lines.

In one possible embodiment, the control circuit is further configured to: when the writing and erasing operation or the reading operation is carried out, the column address decoder is enabled, and the B second switches are disconnected. This embodiment can multiplex the circuitry on the bit line side to achieve normal write erase or read operations as well as electro-pre-crystallization operations.

In one possible embodiment, the start time of the first signal is earlier than the start time of the second signal, and the end time of the first signal is later than the end time of the second signal. That is, the time range of the first signal applied to the word line is greater than the time range of the second signal, ensuring that the gating device on the word line is turned on first and then applies the second signal to the bit line.

In one possible embodiment, the second signal is greater than the signal applied to the bit line for an erase operation and less than twice the signal applied to the bit line for a write operation. The magnitude of the second signal is not limited in the present application, and as long as the second signal is applied to the bit line, the memory cell performs the electro-pre-crystallization operation, and theoretically, the larger the second signal is, the faster the electro-pre-crystallization operation is completed.

In a second aspect, a method for controlling a phase change memory is provided, where the method is applied to the phase change memory according to the first aspect and any one of the embodiments thereof, and the method includes: receiving a write command and an address, and determining a storage block corresponding to the write command according to the address; performing a pre-operation on the memory block to cause the phase change material of the plurality of memory cells of the memory block to be in a pre-crystallized state, the pre-crystallized state being an intermediate state between a crystalline state and an amorphous state of the phase change material.

In one possible implementation, performing pre-operations on a memory block includes: a word line selection circuit and a bit line selection circuit which control a memory block select a plurality of memory cells, and input a preset electric signal to the plurality of memory cells, wherein the preset electric signal enables phase-change materials of the plurality of memory cells to be in a pre-crystallization state.

In one possible implementation, controlling a word line selection circuit and a bit line selection circuit of a memory block to select a plurality of memory cells includes: and controlling a first full selection circuit in the word line selection circuit and a second full selection circuit in the bit line selection circuit to select a plurality of memory cells.

In one possible embodiment, the preset electrical signal includes a first signal, and the inputting the preset electrical signal to the plurality of memory cells includes: a first switches respectively coupled to A word lines of the memory array are closed to apply first signals input by the A first switches to the A word lines.

In one possible embodiment, the row address decoder of the word line selection circuit coupled to a word lines is disabled when the a first switches are closed.

In one possible embodiment, the method further comprises: when the writing and erasing operation or the reading operation is carried out, the row address decoder is enabled, and the A first switches are disconnected.

In one possible implementation, the first signal is less than a signal applied to the word line during the erase operation and is greater than or equal to a threshold at which a word line gating device of the memory array is turned on.

In one possible embodiment, the preset electrical signal includes a second signal, and the inputting the preset electrical signal to the plurality of memory cells includes: and closing the B second switches of the second full selection circuit, and inputting a control signal to second ends of the B second switches to couple fixed ends of the B data selectors of the second full selection circuit with the first movable ends so as to apply a second signal to the B bit lines of the plurality of memory cells.

In one possible embodiment, the method further comprises: the column address decoder of the bit line selection circuit coupled to the control terminal of the data selector is disabled when the B second switches are closed.

In one possible embodiment, the method further comprises: when the writing and erasing operation or the reading operation is carried out, the column address decoder is enabled, and the B second switches are disconnected.

In one possible embodiment, the second signal is greater than the signal applied to the bit line for an erase operation and less than twice the signal applied to the bit line for a write operation.

In a third aspect, an electronic device is provided, which includes a processor and a phase change memory as described in the first aspect and any of the embodiments thereof, where the processor is coupled to the phase change memory, and the processor is configured to read and write data stored in the phase change memory.

In a fourth aspect, a computer-readable storage medium is provided, in which instructions are stored, and the instructions are executed on a phase change memory, so that the phase change memory executes the control method according to the second aspect and any one of the embodiments thereof.

In a fifth aspect, a computer program product is provided, which comprises instructions that are executed on a phase change memory, so that the phase change memory executes the control method according to the second aspect and any one of the embodiments thereof.

With regard to the technical effects of the second to fifth aspects, reference is made to the technical effects of the first aspect and any of the embodiments thereof, which are not repeated here.

Drawings

Fig. 1 is a schematic structural diagram of a non-volatile memory according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a memory array of a phase change memory according to an embodiment of the present disclosure;

FIG. 3 is a diagram illustrating an embodiment of a phase change memory device according to the present invention;

FIG. 4 is a schematic structural diagram of another nonvolatile memory according to an embodiment of the present application;

fig. 5 is a flowchart illustrating a method for controlling a phase change memory according to an embodiment of the present disclosure;

FIG. 6 is a timing diagram illustrating a write/erase operation performed without performing an electro-pre-crystallization operation and performed after performing the electro-pre-crystallization operation according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of one possible configuration of a word line select circuit and a bit line select circuit provided by an embodiment of the present application;

FIG. 8 is a schematic diagram illustrating an operation of an electro-pre-crystallization operation according to an embodiment of the present application;

fig. 9 is a schematic view of an electronic device according to an embodiment of the present application.

Detailed Description

Some concepts to which this application relates will first be described:

the phase change memory is a novel semiconductor memory based on chalcogenide compounds, and is a nonvolatile memory. Phase change technology was first introduced by Ovshinsky in the last 60 centuries, and its major technical advantages include low cost, large capacity, long life, fast speed, non-mechanical, shock-resistant, non-volatile, radiation-resistant, and integration with standard complementary metal-oxide-semiconductor (CMOS) circuits.

The memory cell of the phase change memory is generally manufactured on a silicon substrate, and includes a phase change material for storing information, a heating electrode, a gating device, a cladding material for insulation and heat preservation, and a Word Line (WL) and a Bit Line (BL) for extracting an electrical signal.

In the embodiment of the present application, the gating device (for example, the word line gating device referred to later) may be an N-type metal oxide semiconductor (NMOS) transistor or a triode.

The principle of the phase change memory for storing data is as follows: the phase-change material can be rapidly and reversibly transformed between a high-resistance amorphous state and a low-resistance polycrystalline state by applying electric pulses with different amplitudes and shapes on the phase-change material, wherein the high-resistance amorphous state is realized by write (RESET) operation, the corresponding stored data is 0, the low-resistance polycrystalline state is realized by erase (SET) operation, and the corresponding stored data is 1. Since different bits may write either a 0 or a 1 for the same write command, the write and erase operations are in parallel and may be collectively referred to as a write-erase operation. In addition, the data stored in the phase change memory may also be read by a read operation.

The electrical pulses of the write (RESET) operation are characterized by high amplitude, short duration and rapid rising and falling edges. Under the action of the electric pulse, the temperature of the phase-change material is raised rapidly above the melting temperature and quenched, and the state of the phase-change material remains in a high-resistance amorphous state because microscopic atoms do not have enough time to complete crystallization.

The electrical pulses of the wipe (SET) operation are characterized by a lower amplitude but a longer duration. Under the action of the electric pulse, the temperature of the phase-change material can be kept below the melting temperature above the crystallization temperature for a period of time, so that enough time can be provided for crystallization to a low-resistance polycrystalline state.

The principle of the read operation is that the high-low resistance state can be distinguished by applying a weak voltage signal to the phase-change material of the memory cell and measuring the current response, so as to determine the stored data; or, by applying a weak current signal to the phase change material of the memory cell, the high and low resistance states can be distinguished by measuring the voltage response, thereby determining the stored data.

One possible structure of a non-volatile memory is described below in conjunction with fig. 1.

As shown in fig. 1, an embodiment of the present application provides a nonvolatile memory, which includes a control circuit 101, a plurality of memory blocks 100, and an input/output interface circuit 108. The memory block 100 includes a memory array 102, a row address decoder 103, a column address decoder 104, a data selector (MUX) 105, a signal generation circuit 106, and a buffer circuit 107.

The nonvolatile memory related to the embodiment of the application can be a phase change memory. The storage array referred to in this application may refer to a combination of storage units that are physically adjacent, or a combination of storage units that are not physically adjacent but logically associated with merged operations.

The memory array 102 may be coupled to the row address decoder 103 through word lines WL, and the memory array 102 may be further coupled to a fixed terminal of the data selector 105 through bit lines BL. A first active terminal of the data selector 105 may be coupled to the signal generating circuit 106, and a second active terminal of the data selector 105 may be grounded or connected to a negative voltage, wherein a fixed terminal of the data selector 105 is coupled to the second active terminal in a default state, i.e., the bit line BL is grounded or connected to a negative voltage by default. The signal generating circuit 106 may be coupled to a buffer circuit 107, and the buffer circuit 107 may be coupled to an input-output interface circuit 108. An output terminal of the column address decoder 104 is coupled to a control terminal of the data selector 105 through an Address Signal Line (ASL).

The memory array 102 may include a plurality of memory cells, and for example, when the nonvolatile memory is a phase change memory, the principle of storing data and reading data in the memory cells may be described with reference to the foregoing description.

The buffer circuit 107 is used for buffering data transmitted between the memory array 102 and the input/output interface circuit 108.

The address decoder (row address decoder 103 or column address decoder 104) is a multi-input multi-output combinational logic digital circuit device, assuming that the address decoder inputs a K-bit binary address code and the output is 2 ^K An address signal. For input address code 2 ^K Variation, 2 of the output of the address decoder ^K Only one of the address signals is active (e.g., high level), all the others are inactive (e.g., low level), and the address signals corresponding to different address codes are different.

The control circuit 101 may receive an operation command and an address through the input/output interface circuit 108, where the operation command may include a read command, a write command, and the like, for example, the read command corresponds to a read operation, and the write command corresponds to a write/erase operation. The address may indicate a selected memory block and memory cells of the memory array in the memory block. The control circuit 101 selects one memory block according to the upper bits of the address, selects memory cells of the memory array in the memory block according to the lower bits of the address, and operates the selected memory cells according to the operation command.

For a memory block, the control circuit 101 may process an input address and send an address code of a word line to the row address decoder 103, and the row address decoder 103 decodes the address code to obtain a selected word line WL. The control circuit 101 may further process the input address and send an address code of the bit line to the column address decoder 104, and the column address decoder 104 decodes the address code to obtain the selected bit line BL. Specifically, the column address decoder 104 decodes the address code to obtain a selected address signal line ASL, and the selected address signal line ASL controls the data selector 105 to couple its fixed terminal to the first active terminal to select the bit line BL.

For one memory block, the control circuit 101 may also control the signal generation circuit 106 to generate an operation electrical signal (e.g., a voltage signal) to be supplied to the row address decoder 103, and the row address decoder 103 applies the operation electrical signal to a corresponding word line. The control circuit 101 may also control the signal generation circuit 106 to generate an operation electrical signal (e.g., a voltage signal, a current signal, and usually a voltage signal) supplied to the column address decoder 104, and the operation electrical signal is applied to the corresponding address signal line ASL by the column address decoder 104. The control circuit 101 may also control the signal generation circuit 106 to generate an operating electrical signal to be supplied to the bit line BL and applied to the coupled memory cell through the selected bit line BL.

It should be noted that the operating electrical signal generated by the signal generating circuit 106 is different according to the operation, which will be described later. The operation electrical signal according to the embodiment of the present application may refer to a voltage signal or a current signal, and the embodiment of the present application is described by taking the voltage signal as an example, but is not intended to be limited thereto. In addition, the signal generating circuit 106 may be a single circuit, and may also include a reading circuit, a writing pulse circuit, and an erasing pulse circuit according to the generated operating electrical signal, where the reading circuit is used to generate the operating electrical signal for reading operation; the write pulse circuit is used for generating an operation electric signal for write operation; the erasing pulse circuit is used for generating an operation electric signal for an erasing operation.

The working principle of the non-volatile memory will be described with reference to fig. 2-3 by taking the phase change memory as an example.

As shown in fig. 2, a memory cell 200 of a memory array of a phase change memory includes a word line gating device 202 and a phase change material 201 as a variable resistance coupled. The word lines WL of the memory array are coupled to control terminals (e.g., gates) of the word line gating device 202 for controlling the turning on and off of the word line gating device 202. A bit line BL of the memory array is coupled to one end of the phase change material 201, the other end of the phase change material 201 is coupled to one controlled end (e.g., drain) of the word line gating device 202, and the other controlled end (e.g., source) of the word line gating device 202 is grounded.

The memory cells of the memory array of the phase change memory are arranged repeatedly in the XY physical direction. Typically, the memory array comprises 2 in the X direction ^M The row memory cells including 2 in the Y direction ^N Column memory cells, comprising in total 2 ^M+N And a memory unit. In order to reduce the complexity of the operation and prevent mutual interference of the electric signals, a memory cell can be selected from a memory array to perform corresponding write-erase operation or read operation. If the parallelism (i.e., bit width) of the operation is to be increased, multiple memory arrays may be operated in parallel.

The word line WL refers to a signal line used for selecting a certain row of memory cells in the memory array, the bit line BL refers to a signal line used for selecting a certain column of memory cells in the memory array, and the word line WL and the bit line BL work together to select one memory cell. The number of the word lines WL or the bit lines BL according to the embodiment of the present application may be multiple or one.

The row address decoder 203 includes a signal input terminal S, an enable terminal EN, M input terminals, and 2 ^M And each output end: the enable terminal EN is controlled by the control circuit and is used for enabling or disabling the row address decoder 203; m input terminals for inputting M-bit binary addresses from the control circuitCode; 2 ^M One output terminal coupled to 2 of the memory array ^M Word lines WL for going to 2 ^M Striped word line WL output 2 ^M An address signal; the signal input terminal S is used to input an operation electric signal from the signal generating circuit, and the row address decoder 203 may apply the input operation electric signal to the selected word line WL.

The column address decoder 204 includes an input terminal S, an enable terminal EN, N input terminals, and 2 ^N And each output end: the enable terminal EN is controlled by the control circuit and is used for enabling or disabling the column address decoder 204; n input ends are used for inputting N-bit binary address codes from the control circuit; 2 ^N An output terminal coupled to 2 ^N A control terminal of the data selector 205 for turning to 2 ^N Data selector 205 output 2 ^N An address signal; the signal input terminal S is used to input an operation electric signal from the signal generating circuit, and the row address decoder 203 may apply the input operation electric signal to the selected address signal line ASL.

The read operation or the write-erase operation of the phase change memory may include four processes:

(1) the control circuit outputs an effective address signal (e.g., high level) to a selected one of the word lines WL through the row address decoding circuit to select a row of memory cells of the memory array coupled to the selected word line WL, and outputs an ineffective address signal (e.g., low level) to the remaining unselected word lines WL through the row address decoding circuit. The asserted address signal applied to the selected word line WL is used to turn on the word line gating device to which the selected word line WL is coupled, and should be large enough to ensure that the word line gating device is capable of driving the current required for this operation without affecting reliability.

For example, as shown in FIG. 3, when the row address decoder 203 inputs an M-bit binary address code, 2 is output ^M Of the word lines WL, only the selected one is set to high level, and the rest 2 are not selected ^M The-1 word lines WL are set low, so that only the word line gate tube corresponding to the selected word line WL can be turned on.

(2) The control circuit outputs an asserted address signal (e.g., high level) to a selected one of the address signal lines ASL through the column address decoding circuit to select one of the address signal lines ASL and one of the data selectors, and outputs an ineffective address signal (e.g., low level) to the remaining unselected address signal lines ASL and unselected data selectors through the column address decoding circuit. Under the action of the asserted address signal, the fixed end of the selected data selector is coupled to the first active end to select the bit line BL, i.e., the selected bit line BL is coupled to the signal generating circuit. And the fixed end of the other unselected data selectors is still coupled to the second active end under the action of the invalid address signal, so that the unselected bit line BL is still grounded or connected with a negative voltage.

For example, as shown in fig. 3, when the column address decoder 204 inputs an N-bit binary address code, 2 is output ^N Of the address signal lines ASL, only a selected one is set to high level, and the remaining unselected ones 2 ^N -1 address signal line is set to low level, so that only the fixed end of the data selector coupled with the selected address signal line is coupled to the first active end to select the corresponding bit line BL, and so that the selected bit line BL can receive the operation electric signal provided from the signal generating circuit.

An operating electric signal provided by the signal generating circuit can be applied to the phase-change material 201 of the selected memory cell through the selected word line WL and the selected bit line BL, so that a read operation or a write-erase operation on the memory cell is realized.

(3) The signal generating circuit applies an operation electrical signal corresponding to the operation to the selected bit line BL, wherein the operation electrical signal applied for the read operation, the write operation, or the erase operation may be different.

(4) The control circuit turns off the row address decoder and the column address decoder and waits for the next operation instruction.

The following is a description of the peak values of various operation electric signals applied to the word lines WL and the bit lines BL generated by the signal generation circuit in a read operation or a write-erase operation.

S1: a peak value of an operating electric signal applied to the selected word line WL in the write erase operation or the read operation. Taking the operating electrical signal as an example, S1 may be 3.3V for a memory cell with an operating voltage of 3.3V.

S2: a peak value of an operation electric signal applied to the unselected word line WL in the write erase operation or the read operation. Taking the operation electrical signal as an example voltage, S2 can be 0V (i.e. word line WL is grounded) or a negative voltage (i.e. word line WL is connected to a negative voltage) for a memory cell with an operating voltage of 3.3V.

S3: the peak value of the operating electrical signal applied to the selected bit line BL in the write operation.

S4: a peak of an operating electric signal applied to the selected bit line BL in the erase operation. The operating electrical signal may be trapezoidal or non-trapezoidal, for example in the shape of a step down.

S5: the peak of the operating electrical signal applied to the selected bit line BL in the read operation. General S3> S4> S5.

S6: a peak value of an operating electric signal applied to the unselected bit line BL in the read operation or the write erase operation. Taking the operating electrical signal as an example voltage, for a memory cell with an operating voltage of 3.3V, S6 can be 0V (i.e. the bit line BL is grounded) or a negative voltage (i.e. the bit line BL is connected to a negative voltage).

In addition, the operating electric signal has the following relationship in time: the duration of S3 is generally less than 100ns, the duration of S4 is generally greater than 500ns less than 1000ns, and the duration of S5 is generally less than 100 ns. The start times of S1 and S2 are earlier than those of S3, S4, S5, and the end times of S1 and S2 are later than those of S3, S4, S5.

The above-described operation electric signal will be described additionally.

In the case where the selected word line WL has been asserted, the non-selected word line WL applies the operation electric signal on the control terminals of the word line pass devices as S2, so that all the word line pass devices coupled to the non-selected word line WL are in an off state. Even if the memory cells coupled to these turned-off word line pass devices are coupled to the selected bit line BL, no current flows due to the operating electrical signal on the selected bit line BL. And the operating electrical signal applied by the selected word line WL to the control terminal of the word line gating device is S1, so that the maximum current flowing through the word line gating device coupled thereto is greater than the maximum current required to operate the phase change material (i.e., the write current, which is typically greater than 100 uA).

In the case where the selected bit line BL has been determined, the fixed terminal of the unselected data selector is coupled to the second active terminal, so that the operating electric signal on the bit line BL coupled to the unselected data selector is S6 (i.e., grounded or negatively charged), and the selected bit line BL applies a different operating electric signal according to a difference of the read operation, the write operation, or the erase operation (S3/S4/S5). Wherein the duration of S3 and S5 is generally less than 100 nanoseconds, and the duration of S4 is generally greater than 500 nanoseconds.

Therefore, although the read/write speed of the phase change memory is greatly improved compared to the conventional memories such as a 3D NAND memory and a magnetic disk, the phase change memory still has at least one order of magnitude behind the read/write speed (nanosecond level) of a Dynamic Random Access Memory (DRAM). The main disadvantages of phase change memories are as follows: (1) in combination with the working principle of the write-erase operation of the phase change memory, which is described above, the erase operation time (generally greater than 500 ns) is longer than the write operation time (generally less than 100 ns) due to the physical rule. Therefore, during each execution of the write and erase operation, only a small amount of time is used for the write operation, and most of the remaining time is waiting for the erase operation of the rest of the memory cells, so that the write and erase operation delay is high. (2) The read operation and the write/erase operation are not matched in time, which results in low bandwidth utilization of the data bus in practical application. (3) The number of memory cells performing the write/erase operation is large, and the required write/erase operation current is also large, i.e. the power consumption of the write/erase operation is large, so that it is not beneficial to increase the operation bit width, i.e. the number of memory cells capable of performing the write/erase operation in parallel is limited.

To this end, embodiments of the present application provide another nonvolatile memory, which may be a phase change memory. Before performing the write/erase operation, a plurality of memory cells of the memory array are selected, and a predetermined electrical signal is input to the plurality of memory cells, so that the phase-change material in the memory cells is in a pre-crystallization state (i.e., electro-pre-crystallization, which may be referred to as an electro-pre-crystallization operation or simply as a pre-operation), where the pre-crystallization state is an intermediate state between a crystalline state and an amorphous state of the phase-change material, thereby forming a large number of conductive channels or crystallization nucleation centers inside the memory cells. When the writing and erasing operation corresponding to the writing command is carried out subsequently, the erasing operation can realize crystallization in a short time, so that the erasing operation is completed more quickly, and the power consumption of the erasing operation can be reduced. In addition, the electro-pre-crystallization operation does not need to use larger current and raise the temperature of the phase-change material to be higher than the crystallization temperature, so that the power consumption of the electro-pre-crystallization is reduced, and the parallelism of the electro-pre-crystallization operation is also improved.

The principle of the electro-pre-crystallization of the phase-change material of the phase-change memory is as follows: the amorphous state of the phase-change material is a short-range disordered state, but a part of crystal grains are still included among amorphous atoms, and under the action of an external electric field, the shortest path between the crystal grains is often distributed with a local strongest electric field. If an electric field with certain intensity is applied to the phase-change material (for example, through the bit line BL), the amorphous atoms have higher energy and probability under the action of the electric field to complete the crystallization process, so that by applying the electric field to the phase-change material, fine conductive channels or nucleation crystallization centers which are randomly distributed are formed in the memory cell under the action of the micro-localized electric field, and the phase-change material can be crystallized more quickly when thermally induced crystallization is performed in subsequent erasing operation.

As shown in fig. 4, the nonvolatile memory includes a control circuit 401, a plurality of memory blocks 400, and an input-output interface circuit 407. The memory block 400 includes a memory array 402, a word line selection circuit 403, a bit line selection circuit 404, a signal generation circuit 405, and a buffer circuit 406.

The contents of the control circuit 401, the memory array 402, the signal generation circuit 405, the buffer circuit 406, and the input/output interface circuit 407 are described above, and will not be repeated here.

The nonvolatile memory may perform a control method of the phase change memory as shown in fig. 5:

s501, the control circuit 401 receives the write command and the address, and determines the storage block corresponding to the write command according to the address.

The control circuit 101 may select one of the memory blocks according to the upper bits of the address, for example, assuming that the nonvolatile memory includes 8 memory blocks, the control circuit 101 may select one of the 8 memory blocks according to the upper 3 bits of the address.

S502, the control circuit 401 performs an electro-pre-crystallization operation (pre-operation) on the memory block to make the phase change materials of the plurality of memory cells of the memory block in a pre-crystallization state.

That is, the control circuit 401 controls the word line selection circuit and the bit line selection circuit to select a plurality of memory cells in the memory array, and inputs a predetermined electric signal to the plurality of memory cells, and the predetermined electric signal causes the phase change material of the plurality of memory cells to be in a pre-crystallization state. The pre-crystallization state is described above and will not be repeated here.

The signal generating circuit 405 may generate a preset electrical signal including the first signal and the second signal, in addition to the functions described above. The first signal is smaller than a signal applied to the word line WL in the writing and erasing operation and is larger than or equal to a threshold value for enabling a word line gating device of a storage unit in the storage array to be conducted; the magnitude of the second signal is not limited in the present application, and as long as the second signal is applied to the bit line, the memory cell performs the electro-pre-crystallization, and theoretically, the larger the second signal is, the faster the electro-pre-crystallization operation is completed, for example, the second signal may be larger than the signal applied to the bit line BL during the erase operation. Alternatively, the second signal may be smaller than twice the signal applied to the bit line BL at the time of the write operation. The first signal may be a voltage signal and the second signal may be a voltage signal or a current signal.

As described above, the signal generating circuit 405 may be a single circuit, and may also include a first signal generating circuit and a second signal generating circuit according to the difference of the generated operating electrical signals, where the first signal generating circuit is used to generate a first signal; the second signal generating circuit is used for generating a second signal.

The control circuit 401 controls the word line selection circuit 403 to apply a first signal to the word line WL and controls the bit line selection circuit 404 to apply a second signal to the bit line BL in an electro-pre-crystallization operation (pre-operation) before performing the write-erase operation to electro-pre-crystallize the memory cell so that the phase change material in the memory cell is in a pre-crystallized state.

In addition to the functions described above, the control circuit 401 may control the word line selection circuit 403 to apply the first signal to the word line WL and the bit line selection circuit 404 to apply the second signal to the bit line BL in the electro-pre-crystallization operation before the write/erase operation, so as to perform the electro-pre-crystallization operation on the memory cell in the memory array.

It should be noted that, the control circuit may execute the above-mentioned electro-pre-crystallization operation according to the received electro-pre-crystallization operation command, and in order to distinguish the write/erase operation after the electro-pre-crystallization operation is executed from the write/erase operation after the electro-pre-crystallization operation is not executed, the write/erase operation after the electro-pre-crystallization operation is executed may be referred to as a fast write/erase operation, the corresponding operation command is a fast write command, the erase operation after the electro-pre-crystallization operation is not executed is referred to as a normal write/erase operation, and the corresponding operation command is a normal write command.

Since the current flowing when the word line gating device is turned on is influenced by the magnitude of the control end signal, and the first signal is smaller than the signal applied to the word line WL in the writing and erasing operation and is greater than or equal to the threshold value for turning on the word line gating device, in performing the electro-pre-crystallization operation, the word line gating device can be turned on and the current actually flowing through the bit line BL and the phase change material is very small, approximately in the range of 1uA to 20 uA. Owing to the current limiting effect, the temperature of the phase change material is lower than the crystallization temperature under the action of the second signal, so that the thermotropic crystallization is not dominant, the required current and the power consumption are lower, and the power consumption in the electro-precrystallization operation can be reduced. Therefore, the electro-pre-crystallization can be performed in parallel by a plurality of storage units, and the parallelism of the electro-pre-crystallization is improved.

In the embodiment of the present application, the word line WL to which the first signal is applied may refer to all word lines WL or a part of word lines WL of the memory array, and the bit line BL to which the second signal is applied may refer to all bit lines BL or a part of bit lines BL of the memory array. That is, all or a portion of the memory cells in the memory array may be electro-pre-crystallized.

The duration of the first signal and the duration of the second signal are not limited in this application, and may be, for example, greater than, equal to, or less than the time of the erasing operation, and may be adjusted according to the pre-crystallization characteristics of the phase change material, for example, the durations of the first signal and the second signal may be set as factory-adjustable parameters, and the durations of the first signal and the second signal may be adjusted according to the optimal pre-crystallization result measured in the factory. Specifically, the duration of the first signal may be greater than, less than, or equal to the duration of the operation electric signal applied to the selected word line WL at the time of the erase operation. The duration of the second signal may be greater than, less than, or equal to the duration of the operating electrical signal applied to the selected bit line BL at the time of the erase operation.

In addition, the start time of the first signal may be earlier than the start time of the second signal, and the end time of the first signal may be later than the end time of the second signal. That is, the time range of the first signal applied to the word line WL is greater than the time range of the second signal applied to the bit line BL, ensuring that the gating device on the word line WL is turned on first and then applies the second signal to the bit line.

After the electro-pre-crystallization operation is performed, a read operation or a write-erase operation may be performed. The peak values of various operating electric signals applied to the word lines WL and the bit lines BL generated by the signal generating circuit in the read operation or the write erase operation after the electro-pre-crystallization operation is performed will be described below.

S1': after the electro pre-crystallization operation is performed, a peak value of an operation electric signal applied to the selected word line WL in a write erase operation or a read operation. May be the same as S1 described previously.

S2': a peak value of an operating electric signal applied to the unselected word line WL in the write erase operation or the read operation after the electro-pre-crystallization operation is performed. May be the same as S2 described previously.

S3': after the electro-pre-crystallization operation is performed, the peak value of the operation electric signal applied to the selected bit line BL in the write operation. May be the same as S3 described previously.

S4': after the electro-pre-crystallization operation is performed, a peak value of an operation electric signal applied to the selected bit line BL in the erase operation. May be the same as S4 described above, or may be adjusted according to the electro-crystallization characteristic and the thermotropic crystallization characteristic of the phase change material.

S5': after the electro-pre-crystallization operation is performed, the peak value of the operation electric signal applied to the selected bit line BL in the read operation. May be the same as S5 described previously.

S6': the peak value of the operating electric signal applied to the unselected bit line BL in the read operation or the write erase operation after the electro-pre-crystallization operation is performed. May be the same as S6 described previously.

In addition, the operating electric signals have the following relationship in time: after performing the electro-pre-crystallization operation, the duration of S3 'is generally less than 100ns, and the duration of S5' is generally less than 100 ns. The start times of S1 'and S2' are earlier than those of S3 ', S4', S5 ', and the end times of S1' and S2 'are later than those of S3', S4 ', S5'.

In fig. 6, a shows the timing when the erase operation is performed without performing the electro-pre-crystallization operation, and B shows the timing when the erase operation is performed after performing the electro-pre-crystallization operation. Although B in fig. 6 additionally introduces an electro-pre-crystallization operation in the order of hundreds of nanoseconds, the total time consumption of the whole electro-pre-crystallization plus the erasing operation is greatly reduced due to the proportional decrease of the time consumption of the subsequent erasing operation performed on each memory cell.

As an example, assume that the duration t1 of the electro-precrystallization is 400 ns; when the electro-precrystallization is not carried out, the duration t2 of the wiping operation is 500 ns; after the electro-precrystallization, the duration t3 of the wiping operation is 100 ns; the size of the memory array is 1024 bits (bit). The total time consumption for performing the wiping operation after performing the electro-pre-crystallization operation is 400ns +100ns 1024 — 102.8 us; when the electro-pre-crystallization operation is not performed, the total time consumption of the erasing operation is 500ns 1024-512 us. It can be seen that the total time consumption of performing the erasing operation after the electro-pre-crystallization is reduced to about 1/5 compared with performing the erasing operation without performing the electro-pre-crystallization operation. The execution speed of the wiping operation can be greatly increased.

By reducing the time of the erasing operation, the time interval of the writing operation is also shortened, so that the bandwidth of the writing and erasing operation of the phase change memory can be improved. And the problem that the read operation and the write-erase operation of the phase change memory are not matched in time can be solved, and the bandwidth utilization rate of the data bus is improved. In addition, by reducing the time of the write-erase operation, the power consumption of the write-erase operation can be reduced, and the power consumption of the phase change memory as a whole is reduced because the current is small and the power consumption is low in the electro-pre-crystallization operation.

In summary, before the write/erase operation, the control circuit selects a plurality of memory cells of the memory array by controlling the word line selection circuit and the bit line selection circuit, and inputs a preset electrical signal to the plurality of memory cells, where the preset electrical signal makes phase change materials of the plurality of memory cells in a pre-crystallization state, so that a large number of conductive channels or crystallization nucleation centers are formed in the memory cells first, and when the write/erase operation is performed subsequently, the crystallization can be implemented in a short time, so that the write/erase operation is completed more quickly, and thus the time for the write/erase operation of the phase change memory can be reduced.

Next, referring to fig. 7, a possible structure of the word line selection circuit and the bit line selection circuit is described by taking a memory block as an example.

In one possible implementation, the word line selection circuit 403 may include a first full selection circuit 4031, the bit line selection circuit 404 may include a second full selection circuit 4041, and the control circuit 401 may control the first full selection circuit 4031 and the second full selection circuit 4041 to select a plurality of memory cells of the memory array 402.

In one possible implementation, the first full selection circuit 4031 may include a first switches 4031, first terminals of the a first switches 4031 are respectively coupled to a word lines WL of the memory array, and second terminals of the a first switches 4031 are used to input the first signal from the signal generation circuit 405(ii) a Wherein A is a positive integer, and A may be equal to 2 ^M 。

Optionally, the word line selection circuit 403 may further include a row address decoder 4032, and a first ends of the a output terminals of the row address decoder 4032 and the a first switches 40311 are respectively coupled to a word lines WL of the memory array. The functions of the row address decoder are described above and will not be repeated here.

In one possible implementation, the second full selection circuit 4041 may include B second switches 40411 and B data selectors 40412, first terminals of the B second switches 40411 being coupled to control terminals of the B data selectors 40412, respectively; the fixed ends of the B data selectors are coupled to B bit lines BL of the memory array, the first active ends of the B data selectors are also used for inputting a second signal from the signal generating circuit, and the second active ends of the B data selectors are grounded or connected with a negative voltage; wherein B is a positive integer, B may be equal to 2 ^N . The functions of the data selector are described above and will not be repeated here.

Optionally, the bit line selection circuit 404 may further include a column address decoder 4042, wherein B output terminals of the column address decoder 4042 and first terminals of the B second switches 40411 are respectively coupled to control terminals of the B data selectors 40412. The functions of the column address decoder are described above and will not be repeated here.

It should be noted that a first switches may be independent from or integrated with the row address decoder, and B second switches may be independent from or integrated with the column address decoder.

The operation principle of the electro-pre-crystallization operation of the phase change memory will be described with reference to fig. 8.

As shown in fig. 8, since the bit of the write operation or the erase operation indicated by the subsequent write command is unknown, the electro-pre-crystallization operation is performed before the write/erase operation. In the electro-pre-crystallization operation before the write-erase operation is performed, the control circuit may close the a first switches so that the first signal generated by the signal generation circuit is applied to the a word lines WL; optionally, when the a first switches are closed, the control circuit may further enable the row address decoder 4032 through the enable terminal EN of the row address decoder 4032, so that the output of the row address decoder 4032 is in a high-resistance state, and a signal on the word line WL is not affected. The control circuit may further close the B second switches and input a control signal to second terminals of the B second switches to couple fixed terminals of the B data selectors with the first movable terminals so that the second signal is applied to the B bit lines; optionally, when the B second switches are closed, the control circuit may further enable the column address decoder 4042 through the enable terminal EN of the column address decoder 4042, so that the output of the column address decoder 4042 is in a high impedance state, and the signal on the address signal line ASL is not affected.

When performing a write/erase operation or a read operation, the control circuit may enable the row address decoder 4032 through the enable terminal EN of the row address decoder 4032, so that the row address decoder 4032 normally outputs an address signal, and turn off the a first switches, so that the first signal is not applied to the word line WL. The control circuit may further enable the column address decoder 4042 through an enable terminal EN of the column address decoder 4042 so that the column address decoder 4042 normally outputs the address signal, and the control circuit may further turn off the B second switches so that the control signal is not applied to the address signal line ASL.

As shown in fig. 9, an embodiment of the present application further provides an electronic device 90, which includes a processor 901 and a non-volatile memory 902 as described above, where the processor 901 is coupled to the non-volatile memory 902, and the processor 901 can read and write data stored in the non-volatile memory 902. The nonvolatile memory may be a phase change memory. The electronic device 90 may be a communication device, a terminal device, a mobile phone, a tablet computer, a smart watch, a computer, an in-vehicle device, a virtual reality device, an augmented reality device, or the like.

The processor related to the embodiment of the application may be a chip. For example, the Field Programmable Gate Array (FPGA) may be an Application Specific Integrated Circuit (ASIC), a system on chip (SoC), a Central Processing Unit (CPU), a Network Processor (NP), a digital signal processing circuit (DSP), a Micro Controller Unit (MCU), a Programmable Logic Device (PLD) or other integrated chips.

The embodiment of the present application further provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and the instructions are executed on the phase change memory, so that the phase change memory executes the control method.

The embodiment of the application also provides a computer program product containing instructions, and the instructions are executed on the phase change memory, so that the phase change memory executes the control method.

Technical effects of the electronic device, the computer-readable storage medium, and the computer program product related to the embodiments of the present application are described with reference to the foregoing description of the nonvolatile memory and the control method, and will not be repeated here.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. The phase change memory is characterized by comprising a control circuit and a memory block, wherein the memory block comprises a memory array, a word line selection circuit and a bit line selection circuit;

the memory array includes a plurality of memory cells, each memory cell including a phase change material;

the control circuit is used for controlling the word line selection circuit and the bit line selection circuit to select the plurality of memory cells of the memory array, and inputting preset electric signals to the plurality of memory cells, wherein the preset electric signals enable the phase-change materials of the plurality of memory cells to be in a pre-crystallization state, and the pre-crystallization state is an intermediate state between a crystallization state and an amorphous state of the phase-change materials.

2. The phase change memory of claim 1, wherein the word line selection circuit comprises a first full selection circuit, wherein the bit line selection circuit comprises a second full selection circuit, and wherein the control circuit is configured to control the first full selection circuit and the second full selection circuit to select the plurality of memory cells of the memory array.

3. The phase change memory according to claim 2, wherein the predetermined electrical signal comprises a first signal, the first full selection circuit comprises a first switches, first terminals of the a first switches are respectively coupled to a word lines of the memory array, and second terminals of the a first switches are used for inputting the first signal; wherein A is a positive integer;

the control circuit is specifically configured to: the A first switches are closed to apply the first signal to the A word lines.

4. The phase-change memory of claim 3, wherein the word line selection circuit further comprises a row address decoder, wherein A outputs of the row address decoder and first ends of the A first switches are respectively coupled to A word lines of the memory array; the control circuit is further configured to:

the row address decoder is disabled when the A first switches are closed.

5. The phase change memory of claim 4, wherein the control circuit is further configured to:

and when the writing operation, the erasing operation or the reading operation is carried out, enabling the row address decoder and disconnecting the A first switches.

6. The phase change memory according to any one of claims 2 to 4, wherein the preset electrical signal comprises a second signal, and the second full selection circuit comprises B second switches and B selectors; first ends of the B second switches are respectively coupled to control ends of the B selectors; the fixed ends of the B selectors are coupled to B bit lines of the memory array, and the first movable ends of the B selectors are used for inputting the second signals; wherein B is a positive integer;

the control circuit is configured to: and closing the B second switches, and inputting a control signal to second ends of the B second switches to couple fixed ends of the B data selectors with first movable ends so as to apply the second signal to the B bit lines.

7. The phase-change memory of claim 6, wherein the bit line selection circuit further comprises a column address decoder, wherein B output terminals of the column address decoder and first terminals of the B second switches are respectively coupled to control terminals of the B data selectors; the control circuit is further configured to:

disabling the column address decoder when the B second switches are closed.

8. The phase change memory of claim 7, wherein the control circuit is further configured to:

and enabling the column address decoder and disconnecting the B second switches when writing operation, erasing operation or reading operation is carried out.

9. A method for controlling a phase change memory, applied to the phase change memory according to any one of claims 1 to 8, the method comprising:

receiving a write command and an address, and determining a storage block corresponding to the write command according to the address;

performing a pre-operation on the memory block to bring a phase change material of the plurality of memory cells of the memory block to a pre-crystallized state, the pre-crystallized state being an intermediate state between a crystalline state and an amorphous state of the phase change material;

and writing the data to be written in the write command in the storage block.

10. The method of claim 9, wherein performing the pre-operation on the memory block comprises:

and controlling a word line selection circuit and a bit line selection circuit of the memory block to select the plurality of memory cells, and inputting a preset electric signal to the plurality of memory cells, wherein the preset electric signal enables the phase-change materials of the plurality of memory cells to be in the pre-crystallization state.

11. The method according to claim 10, wherein the writing of the data to be written in the write command in the memory block comprises:

controlling the word line selection circuit and the bit line selection circuit to restore the plurality of memory cells to unselected states;

and controlling the word line selection circuit and the bit line selection circuit to select the memory cell written with the data to be written for data writing.

12. An electronic device comprising a processor and a phase change memory according to any of claims 1-8, the processor being coupled to the phase change memory, the processor being configured to read and write data stored in the phase change memory.