CN114911568A

CN114911568A - Data transmission method, device and equipment based on Linux operating system

Info

Publication number: CN114911568A
Application number: CN202110179790.4A
Authority: CN
Inventors: 王艳欢
Original assignee: Datang Mobile Communications Equipment Co Ltd
Current assignee: Datang Mobile Communications Equipment Co Ltd
Priority date: 2021-02-07
Filing date: 2021-02-07
Publication date: 2022-08-16

Abstract

The embodiment of the application provides a data transmission method, a data transmission device and data transmission equipment based on a Linux operating system, and relates to the technical field of computers. The method comprises the following steps: acquiring Serial Peripheral Interface (SPI) data to be transmitted; storing the SPI data into a virtual memory corresponding to a user mode of a Linux operating system; acquiring a user mode address corresponding to a storage space of a general purpose input/output GPIO controller; and storing the SPI data into a storage space of the GPIO controller from a virtual memory according to the user mode address. According to the embodiment of the application, after the SPI data are acquired, the SPI data are directly written into the storage space of the GPIO controller by using the user mode address corresponding to the storage space of the GPIO controller, so that the data transmission time delay can be reduced, and the transmission rate can be improved.

Description

Data transmission method, device and equipment based on Linux operating system

Technical Field

The present application relates to the field of computer technologies, and in particular, to a data transmission method, apparatus, and device based on a Linux operating system.

Background

In the prior art, a Serial Peripheral Interface (SPI) has the characteristics of simple connection and convenient use, and is increasingly used on an embedded board and is often used as a connection mode between a Central Processing Unit (CPU) and Peripheral equipment. Because the resources of the SPI controller are limited, or the multiplexing function of the CPU conflicts with a General Purpose Input/Output (GPIO) pin, in actual engineering practice, the GPIO is used more to simulate the SPI communication operation timing, so as to achieve the Purpose of data transmission through the SPI.

In a Linux operating system, when data transmission is performed through an SPI, in a typical implementation, an application program uses a message queue hooking method, and in a user mode, SPI data to be transmitted is packaged and forwarded to a kernel mode in a message queue manner, and the kernel mode completes final data transmission and sends a data transmission result to the user mode. The data transmission mode has larger data transmission delay and lower transmission rate due to the data transmission between the user mode and the kernel mode.

Disclosure of Invention

The present application aims to solve at least one of the above technical drawbacks, in particular the technical drawback of large data transmission delay.

According to one aspect of the application, a data transmission method based on a Linux operating system is provided, and the method comprises the following steps:

acquiring SPI data to be transmitted;

storing the SPI data into a virtual memory corresponding to a user mode of the Linux operating system;

acquiring a user mode address corresponding to a storage space of the GPIO controller;

and storing the SPI data into a storage space of the GPIO controller from a virtual memory according to the user mode address.

According to another aspect of the present application, there is provided a data transmission apparatus based on Linux operating system, the apparatus comprising:

the SPI data acquisition module is used for acquiring serial peripheral interface SPI data to be transmitted;

the SPI data storage module is used for storing the SPI data into a virtual memory corresponding to a user mode of the Linux operating system;

the user mode address acquisition module is used for acquiring a user mode address corresponding to the storage space of the general purpose input/output GPIO controller;

and the SPI data storage module is also used for storing the SPI data into a storage space of the GPIO controller from the virtual memory according to the user mode address.

According to yet another aspect of the present application, there is provided an electronic device comprising a processor and a memory, the memory being configured to store machine-readable instructions, which when executed by the processor, cause the processor to perform the Linux operating system based data transmission method as shown in the above aspect.

According to yet another aspect of the present application, there is provided a computer-readable storage medium on which a computer program is stored, the computer program, when executed by a processor, implementing the data transmission method based on the Linux operating system as shown in the above aspect.

The beneficial effect that technical scheme that this application provided brought is:

compared with the prior art, the data transmission method, the device and the equipment based on the Linux operating system can store SPI data into a virtual memory corresponding to a user mode of the Linux operating system, obtain a user mode address corresponding to a storage space of a GPIO controller, and store the SPI data into the storage space of the GPIO controller from the virtual memory according to the user mode address.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments of the present application will be briefly described below.

Fig. 1 is a schematic structural diagram of a data transmission system according to an embodiment of the present application;

fig. 2 is a schematic flowchart of a data transmission method based on the Linux operating system according to an embodiment of the present application;

fig. 3 is a schematic flowchart of another data transmission method based on the Linux operating system according to an embodiment of the present application;

FIG. 4A is a schematic diagram of a clock cycle according to an embodiment of the present disclosure;

FIG. 4B is a schematic diagram of another clock cycle provided by an embodiment of the present application;

fig. 5 is a schematic structural diagram of a data transmission apparatus based on the Linux operating system according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

To make the objects, technical solutions and advantages of the present application more clear, the following detailed description of the embodiments of the present application will be made with reference to the accompanying drawings. For ease of understanding and explanation of the embodiments of the present application, a data transmission system to which the present application is applicable will be described below, based on which simulation of SPI communication by a GPIO controller can be implemented.

As shown in fig. 1, fig. 1 is a schematic structural diagram of a data transmission system provided in an embodiment of the present application, where the system includes a master device and at least one slave device, and in this example, the slave device may also be referred to as an SPI external device. The master device may be a device including a System On Chip (SOC), and the SPI external device includes, but is not limited to, a Field Programmable Gate Array (FPGA).

Specifically, the software runs on the hardware, that is, the Linux operating system runs on the SOC, the Linux operating system can be structurally divided into a Linux kernel layer and a Linux application layer, a storage space in the Linux kernel layer can be referred to as a kernel space, and the kernel space can also be referred to as a kernel state; the storage space in the Linux application layer may be referred to as a user space, the user space may also be referred to as a user state, the SPI acceleration application program may be run in the user state, and the SPI acceleration application program is used to execute the SPI acceleration operation.

In the embodiment of the application, the hardware includes SOC, contain CPU on the SOC, Direct Memory Access (DMA) controller, GPIO controller and SPI external device, wherein, CPU passes through bus and DMA controller and GPIO controller communication, and DMA controller also can communicate with GPIO controller through the bus, SPI external device includes but is not limited to FPGA, include the SPI interface on the FPGA, the SPI interface can be connected with the pin hardwire of GPIO controller, so that FPGA can carry out SPI communication with the GPIO controller through the SPI interface.

It can be understood that, in the data transmission system shown in fig. 1, a Linux operating system is adopted, and the CPU may simulate the SPI interface through the pin of the GPIO controller, so as to implement communication with the SPI external device, for example, the SPI external device in fig. 1 is an FPGA, and the CPU simulates the SPI interface through the pin of the GPIO controller, so as to implement communication with the FPGA.

The operating system model of the Linux operating system is not limited, and because the Linux operating system runs on hardware and the CPU on the SOC is key hardware for controlling the Linux operating system to run, the data volume which can be processed by the CPU at one time corresponds to the operating system model.

In this embodiment of the present application, the model of the operating system is not limited, for example, the model of the operating system may be 32 bits, that is, the CPU can process a data size of 32 bits (bit) at a time, and since 1 byte is equal to 8 bits, the model of the operating system is 32 bits, which is equivalent to a data size of 4 bytes at a time.

In practical application, the model of the operating system may also be 64 bits, that is, the CPU can process 64 bits of data at a time, which is equivalent to 8 bytes of data at a time.

The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

As shown in fig. 2, fig. 2 is a schematic flowchart of a data transmission method based on the Linux operating system according to an embodiment of the present application, where the method includes steps S21-S24.

Step S21, obtaining SPI data to be transmitted.

In the embodiment of the present application, the SPI data refers to data transmitted based on an SPI communication protocol. At least one application program can be installed on a Linux application layer of the Linux operating system, data acquired by any application program and/or data generated by any application program can be used as SPI data to be transmitted, and the CPU can acquire the SPI data to be transmitted.

Step S22, storing the SPI data in the virtual memory corresponding to the user mode of the Linux operating system.

After the CPU acquires the SPI data, the CPU may allocate a virtual memory in a user mode of the Linux operating system to store the SPI data in the virtual memory.

And step S23, acquiring a user mode address corresponding to the storage space of the GPIO controller.

The GIPO controller includes a storage space, a physical address of the storage space may be mapped in a user mode of the Linux operating system, a virtual address located in the user mode and corresponding to the physical address is obtained, and the virtual address located in the user mode and corresponding to the physical address may be referred to as a user mode address.

In a possible implementation manner, the data transmission method based on the Linux operating system may further include:

configuring a user mode address; and establishing a mapping relation between a kernel mode address and a user mode address corresponding to the storage space of the GPIO controller, and storing the mapping relation.

Correspondingly, in the step S23, the obtaining of the user mode address corresponding to the storage space of the GPIO controller may specifically include:

when a Linux operating system is initialized, acquiring a kernel mode address; and determining the user mode address according to the kernel mode address and the mapping relation.

In the embodiment of the application, a user mode address can be configured for the storage space of the GPIO controller in advance, a mapping relation between a kernel mode address and the user mode address corresponding to the storage space of the GPIO controller is established, and the mapping relation is stored.

The physical address of the storage space in the GIPO controller is mapped in the kernel mode of the Linux operating system in advance, so as to obtain the virtual address located in the kernel mode and corresponding to the physical address, and the virtual address located in the kernel mode and corresponding to the physical address can be called as a kernel mode address.

In a possible implementation manner, a mapping relationship between a kernel mode address corresponding to a storage space of the GPIO controller and a user mode address corresponding to the storage space of the GPIO controller may be established in a Memory Map (MMAP) manner, so as to Map a physical address corresponding to the storage space of the GPIO controller to a user mode, thereby implementing data read-write operation on the storage space of the GPIO controller through operation on the user mode address in a Linux application layer.

As can be seen from the above, for the storage space in the GIPO controller, the physical address of the storage space is mapped in the kernel mode of the Linux operating system in advance, and when the Linux operating system is initialized, the CPU may directly obtain the kernel mode address corresponding to the storage space of the GPIO controller, and determine the user mode address corresponding to the storage space of the GPIO controller by combining the stored mapping relationship.

And step S24, storing the SPI data into the storage space of the GPIO controller from the virtual memory according to the user mode address.

The CPU can acquire a user mode address corresponding to the storage space of the GPIO controller and can perform read-write operation on the storage space of the GPIO controller by using the user mode address.

Compared with the prior art, the data transmission method based on the Linux operating system can store SPI data into a virtual memory corresponding to a user mode of the Linux operating system, obtain a user mode address corresponding to a storage space of the GPIO controller, and store the SPI data into the storage space of the GPIO controller from the virtual memory according to the user mode address.

In a possible implementation manner, in step S22, the storing the SPI data in the virtual memory corresponding to the user mode of the Linux operating system may specifically include:

mapping the SPI data into GPIO pin data corresponding to the GPIO controller according to an SPI communication mode; and storing the GPIO pin data into a virtual memory corresponding to a user mode of the Linux operating system.

In an optional implementation manner, the CPU may map the SPI data into GPIO pin data corresponding to the GPIO controller according to an SPI communication mode, and store the GPIO pin data into a virtual memory corresponding to a user mode of the Linux operating system.

In another optional implementation manner, the CPU may map the SPI data into GPIO pin data corresponding to the GPIO controller according to the SPI communication mode, and the DMA controller stores the GPIO pin data into a virtual memory corresponding to a user mode of the Linux operating system.

The SPI communication mode is a mode of SPI data transmission, and comprises SPI communication time sequence control and an SPI working mechanism, wherein the SPI communication time sequence control comprises four modes, namely rising edge data sampling and falling edge data transmission, falling edge data sampling and falling edge data transmission, rising edge data acquisition and rising edge data transmission, and falling edge data acquisition and rising edge data transmission, the SPI working mechanism is used for determining the SPI data transmission mode, the SPI data transmission mode comprises SPI data transmission from a high position to a low position, and SPI data transmission from a low position to a high position, wherein the mode from the high position to the low position is that the Most Significant Bit (Most Significant Bit, MSB) is in front, and the mode from the low position to the high position is that the least Significant Bit (Last Significant Bit, LSB) is in front.

In this embodiment, the SPI communication mode is not limited, and in one possible implementation, the SPI communication mode may be a leading MSB, rising edge data collection and rising edge data transmission mode.

In the embodiment of the application, the GPIO pins comprise a GPIO input pin and a GPIO output pin. The signals output by the SPI interface are input into the GPIO controller through the GPIO input pin, and the GPIO controller can input the signals into the SPI interface through the GPIO output pin. The number of GPIO Input pins is 1, the GPIO Input pins are Master Input/Slave Output (MISO) pins, and the MISO pins can be called as Master Input/Slave Output pins for short; the GPIO Output pins include 3 GPIO Output pins, which are a Chip Selected (CS) pin, a Slave Clock (SCK) pin, and a Master Output/Slave Input (MOSI) pin, where the CS pin may be referred to as a Chip select pin, the SCK pin may be referred to as a Clock pin, and the MOSI pin may be referred to as a Master Output/Slave Input pin.

In a possible implementation manner, the SPI data may be mapped to GPIO output pin data corresponding to the GPIO controller according to the MSB-first, rising edge data acquisition mode to write the SPI data into the SPI external device, which requires 3 GPIO output pins.

For example, 18 pins, 17 pins and 16 pins of the GPIO controller are used as CS pins, SCK pins and MOSI pins, respectively, the SPI communication mode adopts an MSB-first, rising edge data acquisition mode, the SPI data is 8bit data 0x55, and the SPI external device is an FPGA.

When 0x55 needs to be written into the FPGA, 0x55 may be mapped into GPIO output pin data corresponding to the GPIO controller according to the MSB-first, rising edge data acquisition mode, where the GPIO output pin data is a 32bit array as shown below:

{0x00000000，0x00020000，0x00010000，0x00030000，0x00000000，0x00020000，0x00010000，0x00030000，0x00000000，0x00020000，0x00010000，0x00030000，0x00000000，0x00020000，0x00010000，0x00030000}

after the GPIO pin data is obtained, the GPIO pin data can be cached in a virtual memory corresponding to a user mode of the Linux operating system. The virtual memory includes a plurality of virtual memory segments, and the plurality of virtual memory segments may be continuous or discontinuous.

In a possible implementation manner, the GPIO pin data may be cached in a continuous virtual memory segment corresponding to a user mode of the Linux operating system.

For example, for the 32-bit array, continuous 16 virtual memory segments may be allocated in the user mode of the Linux operating system, and the 32-bit array may be cached in the continuous 16 virtual memory segments.

In a possible implementation manner, in step S24, storing the SPI data from the virtual memory to the storage space of the GPIO controller according to the user mode address may specifically include:

and taking the address of the virtual memory as a source address, taking the user mode address as a destination address, and sending the source address and the destination address to the DMA controller so as to write the SPI data into a storage space of the GPIO controller through the DMA controller.

In this embodiment, the CPU may use the address of the virtual memory as a source address, use the user mode address as a destination address, and send the source address and the destination address to the DMA controller, so as to notify the DMA controller of the source address and the destination address.

The DMA is a high-speed data transmission operation, data can be directly transmitted between memories and between the memories and external equipment, the DMA operation requires a CPU to participate in the configuration of DMA rules in an early stage in a small amount, the intervention of the CPU is not required in the transmission, and the whole data transmission is completed under the operation of a DMA controller.

In the embodiment of the application, the CPU may configure the DMA rule such that the source address is incremented, the destination address is fixed, and after receiving the source address and the destination address sent by the CPU, the DMA controller may start DMA transmission, that is, the DMA controller writes SPI data from the virtual memory corresponding to the source address into the storage space of the GPIO controller corresponding to the destination address. In the SPI data writing process, DMA data transmission is completed under the operation of a DMA controller without the participation of a CPU. And after the DMA data transmission is finished, the DMA controller sends a DMA data transmission result to the CPU, which indicates that the SPI data transmission is finished. The CPU can determine whether the SPI data transmission is successful according to the DMA data transmission result, if so, the next SPI data transmission can be started, and if not, whether the SPI data needs to be retransmitted is determined.

and acquiring the operation length corresponding to the SPI data.

Sending the source address and the destination address to the DMA controller, so as to write the SPI data into the memory space of the GPIO controller through the DMA controller, which may specifically include:

and sending the operation length, the source address and the destination address to the DMA controller so as to write the SPI data into a storage space of the GPIO controller through the DMA controller according to the operation length.

In this application embodiment, the CPU may obtain the operation length corresponding to the SPI data, and send the operation length, the source address, and the destination address to the DMA controller, and the DMA controller may write the SPI data into the storage space of the GPIO controller corresponding to the destination address from the virtual memory corresponding to the source address according to the operation length.

The operation length corresponding to the SPI data refers to a data operation length (e.g., number of bytes) corresponding to the SPI data during a DMA operation, where the DMA operation refers to the DMA controller writing the SPI data into a memory space of the GPIO controller according to the operation length. Acquiring an operation length corresponding to the SPI data may specifically include:

determining the data size of the SPI data; and determining the operation length corresponding to the SPI data according to the data size of the SPI data and the operating system model of the Linux operating system.

In the embodiment of the present application, the operating system model of the Linux operating system may be 32 bits, but is not limited to 32 bits, and the operating system model of the Linux operating system in actual application may be determined according to an actual application situation, for example, the operating system model of the Linux operating system may be 64 bits.

In the embodiment of the application, SPI data can be mapped into GPIO pin data corresponding to a GPIO controller according to an SPI communication mode, the GPIO pin data is stored into a virtual memory corresponding to a user state of a Linux operating system, an address of the virtual memory is used as a source address, a user state address corresponding to a storage space of the GPIO controller is used as a destination address, and when the DMA controller writes the SPI data into the storage space of the GPIO controller according to an operation length (i.e., DMA operation), the GPIO pin data is specifically written into the storage space of the GPIO controller according to the operation length, that is, the operation length is the number of bytes corresponding to the GPIO pin data.

Taking 32 bits as an example of the operating system model of the Linux operating system, for SPI data, if the SPI data is 1 byte (i.e., 8 bits), when the SPI data is mapped into GPIO pin data corresponding to the GPIO controller according to the SPI communication mode, the GPIO pin data is 16 32 bits (i.e., 16 x 4 bytes), and the operating length is 16 x 4, at this time, the DMA controller may write the GPIO pin data into the storage space of the GPIO controller according to 16 x 4; if the SPI data is N bytes (i.e., N × 8 bits), when the SPI data is mapped to GPIO pin data corresponding to the GPIO controller according to the SPI communication mode, the GPIO pin data is N × 16 32 bits, that is, N × 16 × 4 bytes, the operation length is N × 16 × 4, and at this time, the DMA controller may write the GPIO pin data into the memory space of the GPIO controller according to N × 16 × 4, where N is a positive integer.

and transmitting the SPI data stored in the storage space of the GPIO controller to the SPI external device through the GPIO controller.

The SPI external device includes, but is not limited to, an FPGA. After the SPI data is written into the storage space of the GPIO controller, the GPIO controller may transmit the SPI data stored in the storage space of the GPIO controller to the SPI external device.

Specifically, the SPI data may be mapped to GPIO pin data corresponding to the GPIO controller, and the GPIO pin data is written into the memory space of the GPIO controller, and the GPIO controller may transmit the GPIO pin data stored in the memory space of the GPIO controller to the SPI external device.

In the process of the SPI data transmission, a CPU can acquire SPI data, maps the SPI data into GPIO pin data, stores the GPIO pin data into a virtual memory corresponding to a user state of a Linux operating system, takes an address of the virtual memory as a source address, takes a user state address corresponding to a storage space of a GPIO controller as a destination address, and sends the source address and the destination address to a DMA controller; the DMA controller carries out DMA operation, namely the DMA controller writes the GPIO pin data into the storage space of the GPIO controller and informs a CPU (Central processing Unit) of a result after the DMA operation is finished; and the GPIO controller transmits the GPIO pin data in the storage space of the GPIO controller to the SPI external device.

From above-mentioned flow can, CPU only participates in a small amount of SPI data transmission work before DMA operation begins and after finishing, has lightened CPU's burden greatly, carries out DMA operation by the DMA controller to with SPI data transmission to GPIO controller's memory space, by SPI controller with SPI data transmission to SPI external equipment in GPIO controller's memory space.

For one-time SPI data transmission, the CPU, the DMA controller and the GPIO controller all execute partial transmission work, and when at least two times of SPI data transmission is needed, the CPU, the DMA controller and the GPIO controller can synchronously work in parallel. That is to say, the CPU may participate in a small amount of SPI data transmission work before the start of this DMA operation, and when the DMA controller performs this DMA operation, the CPU may participate in SPI data transmission work before the start of the next DMA operation, so that the DMA controller may start the next DMA operation after completing this DMA operation; after the DMA controller finishes the DMA operation, the DMA controller can start the next DMA operation, and at the moment, the GPIO controller can transmit SPI data corresponding to the DMA operation to SPI external equipment.

Through the parallel synchronous work of the CPU, the DMA controller and the GPIO controller, the hardware performance of the system can be fully exerted, and the transmission rate of the SPI data is greatly improved.

The data transmission method in the embodiment of the present application is described below with reference to a specific embodiment, where the SPI communication mode is the MSB previous and rising edge data acquisition mode, and the SPI external device is an FPGA.

As shown in fig. 3, fig. 3 is a schematic flowchart of another data transmission method based on the Linux operating system according to an embodiment of the present application, where the method includes steps S31-S37.

And step S31, configuring the user mode address corresponding to the storage space of the GPIO controller, establishing the mapping relation between the kernel mode address and the user mode address corresponding to the storage space of the GPIO controller, and storing the mapping relation.

And step S32, obtaining SPI data to be transmitted, and decomposing and mapping the SPI data into GPIO pin data corresponding to the GPIO controller according to the MSB preceding and rising edge data acquisition mode.

And step S33, storing the GPIO pin data into a virtual memory corresponding to the user mode of the Linux operating system.

And step S34, acquiring the kernel mode address, and determining the user mode address according to the kernel mode address and the mapping relation.

Step S35, using the address of the virtual memory as a source address, using the user mode address as a destination address, and obtaining the operation length.

And step S36, sending the operation length, the source address and the destination address to the DMA controller, and storing the GPIO pin data into a storage space of the GPIO controller by the DMA controller.

And step S37, transmitting the SPI data stored in the storage space of the GPIO controller to the FPGA through the GPIO controller.

The relevant contents of step S31-step S37 can be seen in the relevant description of the above embodiments, and are not repeated herein.

By using the data transmission method in the embodiment of the present application, the data transmission efficiency can be significantly improved, as shown in fig. 4A and 4B, where fig. 4A is a schematic diagram of one clock cycle provided by the embodiment of the present application, fig. 4B is a schematic diagram of another clock cycle provided by the embodiment of the present application, and in fig. 4A and 4B, a vertical line indicated by a reference symbol a and a vertical line indicated by a reference symbol B form one clock cycle, which may also be referred to as a single SPI CLK cycle.

Fig. 4A is a schematic diagram of clock cycles obtained when data transmission is performed in a conventional manner, where an intersection of a vertical dotted line indicated by reference numeral c1 and a time axis may be denoted as an intersection 1, an intersection of a vertical dotted line indicated by reference numeral c2 and the time axis may be denoted as an intersection 2, and a time difference between the intersection 1 and the intersection 2 is a time unit, which is 1 microsecond, that is, 1000 nanoseconds; "a: -840 ns "indicates that the time corresponding to the intersection of the vertical line indicated by the reference character a and the time axis is-840 ns," b: -2.050 microseconds "indicates that the intersection of the vertical line indicated by reference sign b and the time axis corresponds to a time of-2.050 microseconds," Δ: 1.210 microseconds "represents the time difference between the time corresponding to the vertical line indicated by the reference numeral b and the time corresponding to the vertical line indicated by the reference numeral a, i.e., the clock cycle is 1.210 microseconds. That is to say, CPU obtains SPI data, transmits SPI data to kernel mode by user mode, and according to the kernel mode address that GPIO controller's memory space corresponds, transmits SPI data to GPIO controller's memory space in, transmits SPI data to SPI external equipment by GPIO controller. When data transmission is performed in a conventional manner, the period of a single SPI CLK is 1210 nanoseconds.

Fig. 4B is a schematic diagram of clock cycles obtained when data transmission is performed in the embodiment of the present application, where an intersection of a vertical dashed line indicated by reference numeral c1 and a time axis may be denoted as an intersection 1, an intersection of a vertical dashed line indicated by reference numeral c2 and the time axis may be denoted as an intersection 2, and a time difference between the intersection 1 and the intersection 2 is a time unit, where the time unit is 0.4 microseconds, that is, 400 nanoseconds; "a: 663 ns "indicates that the time corresponding to the intersection of the vertical line indicated by reference numeral a and the time axis is 663 ns," b: 1.518 microseconds "indicates that the time corresponding to the intersection of the vertical line indicated by the reference character b and the time axis is 1.518 microseconds," Δ: 855 ns "denotes a time difference between a time corresponding to the vertical line indicated by the reference character b and a time corresponding to the vertical line indicated by the reference character a, i.e., a clock period of 855 ns. That is to say, CPU obtains SPI data, by DMA controller according to the user mode address that GPIO controller's memory space corresponds, transmits SPI data to GPIO controller's memory space in, transmits SPI data to SPI external equipment by GPIO controller. When the mode in the embodiment of the application is adopted for data transmission, the period of a single SPI CLK is 855 nanosecond.

As can be seen from fig. 4A and 4B, the SPI CLK rate is improved by about 30% by reducing the single SPI CLK period from 1210 ns to 855 ns.

In practical application, when SPI communication is performed by GPIO control, 32 megabytes (abbreviated: M) of data are written into the FPGA, and data transmission is performed in a conventional manner, time consumed for writing 32 megabytes of data is about 7 minutes, and when data transmission is performed in the manner in the embodiment of the present application, time consumed for writing 32 megabytes of data is less than 5 minutes, and an actual speed increase is about 30%, which is consistent with a result calculated according to fig. 4A and 4B.

Therefore, compared with the traditional data transmission method, the data transmission method based on the Linux operating system in the embodiment of the application is simple and quick to implement, and the SPI communication rate is remarkably improved.

An embodiment of the present application provides a data transmission apparatus based on a Linux operating system, and as shown in fig. 5, the data transmission apparatus 50 based on the Linux operating system may include: the system comprises an SPI data acquisition module 501, an SPI data storage module 502, and a user mode address acquisition module 503, wherein the SPI data acquisition module 501 is configured to acquire SPI data.

The SPI data storage module 502 is configured to store the SPI data in a virtual memory corresponding to a user mode of the Linux operating system.

And a user mode address obtaining module 503, configured to obtain a user mode address corresponding to the storage space of the GPIO controller.

The SPI data storage module 502 is further configured to store the SPI data from the virtual memory into a storage space of the GPIO controller according to the user mode address.

In a possible implementation manner, the data transmission apparatus 50 based on the Linux operating system further includes:

the mapping relation establishing module is used for configuring a user mode address; and establishing a mapping relation between the kernel mode address and the user mode address corresponding to the storage space of the GPIO controller, and storing the mapping relation.

The user mode address obtaining module 503 is specifically configured to:

In a possible implementation manner, when the SPI data is stored in the virtual memory corresponding to the user state of the Linux operating system, the SPI data storage module 502 is specifically configured to:

In a possible implementation manner, when the SPI data is stored in the storage space of the GPIO controller from the virtual memory according to the user mode address, the SPI data storage module 502 is specifically configured to:

the operation length acquisition module is used for acquiring the operation length corresponding to the SPI data;

the SPI data storage module 502 is specifically configured to, when sending the source address and the destination address to the DMA controller to write the SPI data into the storage space of the GPIO controller through the DMA controller:

and sending the operation length, the source address and the destination address to the DMA controller so as to write the SPI data into a storage space of the GPIO controller according to the operation length through the DMA controller.

In a possible implementation manner, the operation length obtaining module is specifically configured to:

In a possible implementation manner, the SPI data storage module 502 is further configured to transmit the SPI data stored in the storage space of the GPIO controller to the SPI external device through the GPIO controller.

The data transmission apparatus 50 based on the Linux operating system of the present embodiment can execute the data transmission method based on the Linux operating system shown in the previous embodiments of the present application, and the implementation principles thereof are similar, and are not described herein again.

Compared with the prior art, the data transmission device based on the Linux operating system can store SPI data into a virtual memory corresponding to a user mode of the Linux operating system, obtains a user mode address corresponding to a storage space of the GPIO controller, stores the SPI data into the storage space of the GPIO controller from the virtual memory according to the user mode address, achieves the purpose that after the SPI data are obtained by the user mode, the user mode address corresponding to the storage space of the GPIO controller is utilized, the SPI data are directly written into the storage space of the GPIO controller, the SPI data do not need to be transmitted to a kernel mode from the user mode, saves data transmission between the user mode and the kernel mode, reduces data transmission delay, and improves transmission rate.

An embodiment of the present application provides an electronic device, which includes a processor and a memory, where the memory is configured to store machine-readable instructions, and when the instructions are executed by the processor, the processor executes the data transmission method based on the Linux operating system as shown in the above aspect.

In an alternative embodiment, an electronic device is provided, as shown in fig. 6, the electronic device 4000 shown in fig. 6 comprising: a processor 4001 and a memory 4003. Processor 4001 is coupled to memory 4003, such as via bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, and the transceiver 4004 may be used for data interaction between the electronic device and other electronic devices, such as transmission of data and/or reception of data. In addition, the transceiver 4004 is not limited to one in practical applications, and the structure of the electronic device 4000 is not limited to the embodiment of the present application.

The Processor 4001 may be a CPU (Central Processing Unit), a general-purpose Processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other Programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. The processor 4001 may also be a combination that performs a computational function, including, for example, a combination of one or more microprocessors, a combination of a DSP and a microprocessor, or the like.

Bus 4002 may include a path that carries information between the aforementioned components. The bus 4002 may be a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The bus 4002 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 6, but that does not indicate only one bus or one type of bus.

The Memory 4003 may be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical Disc storage, optical Disc storage (including Compact Disc, laser Disc, optical Disc, digital versatile Disc, blu-ray Disc, etc.), a magnetic Disc storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.

The memory 4003 is used for storing application program codes (computer programs) for executing the present scheme, and is controlled by the processor 4001 to execute. Processor 4001 is configured to execute application code stored in memory 4003 to implement what is shown in the foregoing method embodiments.

The present application provides a computer-readable storage medium, on which a computer program is stored, which, when running on a computer, enables the computer to execute the corresponding content in the foregoing method embodiments.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless otherwise indicated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

The foregoing is only a partial embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and embellishments can be made without departing from the principle of the present invention, and these should also be construed as the scope of the present invention.

Claims

1. A data transmission method based on a Linux operating system is characterized by comprising the following steps:

acquiring Serial Peripheral Interface (SPI) data to be transmitted;

acquiring a user mode address corresponding to a storage space of a general purpose input/output GPIO controller;

and storing the SPI data into a storage space of the GPIO controller from the virtual memory according to the user mode address.

2. The method of claim 1, further comprising:

configuring the user mode address;

establishing a mapping relation between a kernel mode address corresponding to a storage space of the GPIO controller and the user mode address, and storing the mapping relation;

the acquiring of the user mode address corresponding to the storage space of the GPIO controller comprises the following steps:

when the Linux operating system is initialized, acquiring the kernel mode address;

and determining the user mode address according to the kernel mode address and the mapping relation.

3. The method according to claim 1 or 2, wherein the storing the SPI data in a virtual memory corresponding to a user mode of the Linux operating system comprises:

mapping the SPI data into GPIO pin data corresponding to the GPIO controller according to an SPI communication mode;

and storing the GPIO pin data into a virtual memory corresponding to the user mode of the Linux operating system.

4. The method according to claim 1 or 2, wherein the storing the SPI data from the virtual memory into a storage space of the GPIO controller according to the user-mode address comprises:

and taking the address of the virtual memory as a source address, taking the user mode address as a destination address, and sending the source address and the destination address to a Direct Memory Access (DMA) controller so as to write the SPI data into a storage space of the GPIO controller through the DMA controller.

5. The method of claim 4, further comprising:

acquiring an operation length corresponding to the SPI data;

the sending the source address and the destination address to a DMA controller so as to write the SPI data into a storage space of the GPIO controller through the DMA controller comprises the following steps:

and sending the operation length, the source address and the destination address to a DMA controller so as to write the SPI data into a storage space of the GPIO controller according to the operation length through the DMA controller.

6. The method according to claim 5, wherein the obtaining the operation length corresponding to the SPI data comprises:

determining the data size of the SPI data;

and determining the operation length corresponding to the SPI data according to the data size of the SPI data and the operating system model of the Linux operating system.

7. The method of claim 1 or 2, further comprising:

and transmitting the SPI data stored in the storage space of the GPIO controller to an SPI external device through the GPIO controller.

8. A data transmission device based on a Linux operating system is characterized by comprising:

the SPI data storage module is further used for storing the SPI data into a storage space of the GPIO controller from the virtual memory according to the user mode address.

9. An electronic device, comprising a processor and a memory configured to store machine-readable instructions that, when executed by the processor, cause the processor to perform the method of any of claims 1-7.

10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method of any one of claims 1 to 7.