CN114900030B - Half-bridge driving circuit with adjustable dead time - Google Patents

Half-bridge driving circuit with adjustable dead time Download PDF

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Publication number
CN114900030B
CN114900030B CN202210464485.4A CN202210464485A CN114900030B CN 114900030 B CN114900030 B CN 114900030B CN 202210464485 A CN202210464485 A CN 202210464485A CN 114900030 B CN114900030 B CN 114900030B
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signal
output
voltage
driving signal
bridge
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CN114900030A (en
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高本峰
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Dongke Semiconductor Anhui Co ltd
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Dongke Semiconductor Anhui Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

The embodiment of the invention relates to a half-bridge driving circuit with adjustable dead time, which comprises the following components: a complementary driving signal generating circuit and a dead time generating circuit; the complementary driving signal generating circuit comprises a first voltage dividing circuit; the dead time generation circuit includes a second voltage division circuit; the complementary driving signal generating circuit outputs a first driving signal and a second driving signal which form complementary pulse width modulation signals and serve as logic control signals of the dead time generating circuit, so that the dead time generating circuit outputs a first half-bridge output signal and a second half-bridge output signal; the low level output of the first/second half-bridge output signal responds simultaneously with the signal inversion of the first/second driving signal, and the high level output of the first/second half-bridge output signal responds with the signal inversion delay of the first/second driving signal; the first voltage dividing circuit is used for controlling the turnover period of the first/second driving signals; the second voltage dividing circuit is used for controlling the time of the delay response, namely the dead time of the half-bridge driving circuit.

Description

Half-bridge driving circuit with adjustable dead time
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a half-bridge driving circuit with adjustable dead time.
Background
Along with the popularization of high-power density and high-efficiency switching power supplies, the half-bridge circuit is widely applied to a quick charging power supply with medium and small power, the dead time of the traditional half-bridge circuit is generally fixed and not adjustable, the power efficiency cannot be further improved due to the fact that the dead time is too large for different half-bridge driving power supply systems, the reliability cannot be guaranteed due to the fact that the dead time is too small, and therefore the dead time generating circuit capable of being flexibly arranged has important significance for compatibility with different power supply systems.
Disclosure of Invention
The invention aims to provide a half-bridge driving circuit with adjustable dead time, which can be widely applied to different power supply systems, improves the reliability of a power supply and simultaneously improves the overall efficiency of the power supply.
To this end, an embodiment of the present invention provides a dead time adjustable half-bridge driving circuit, including: a complementary driving signal generating circuit and a dead time generating circuit;
the complementary driving signal generating circuit comprises a first voltage dividing circuit; the dead time generation circuit includes a second voltage division circuit;
the complementary driving signal generating circuit outputs a first driving signal through a first driving signal output node and outputs a second driving signal through a second driving signal output node, and the first driving signal and the second driving signal form a complementary pulse width modulation signal PWM;
the first driving signal and the second driving signal are used as control signals and logic signals of a dead time generating circuit, so that two output ends of the dead time generating circuit respectively output a first half-bridge output signal and a second half-bridge output signal;
the low level output of the first half-bridge output signal responds simultaneously along with the signal inversion of the first driving signal, and the high level output of the first half-bridge output signal responds in a delayed manner along with the signal inversion of the first driving signal; the low level output of the second half-bridge output signal responds simultaneously along with the signal inversion of the second driving signal, and the high level output of the second half-bridge output signal responds in a delayed manner along with the signal inversion of the second driving signal;
the first voltage dividing circuit is used for controlling the turnover period of the first driving signal and the second driving signal; the second voltage dividing circuit is used for controlling the time of the delay response, namely the dead time of the half-bridge driving circuit.
Preferably, the complementary driving signal generating circuit includes: the switching circuit comprises a first double operational amplifier, an RS trigger, an inverter, a switching tube S1, a switching tube S2, a first capacitor, a first voltage dividing resistor and a second voltage dividing resistor;
the first double-operation amplifier comprises a power supply input pin, a ground pin, a first in-phase input end, a first reverse-phase input end, a first output end, a second in-phase input end, a second reverse-phase input end and a second output end;
the power supply input pin and the second inverting input end are respectively connected with power supply voltage, and the first voltage dividing resistor and the second voltage dividing resistor are connected in series between the power supply input pin and the ground; the first voltage division resistor is connected with the first voltage division resistor, the first voltage division resistor is connected with the first non-inverting input end, and the first inverting input end and the second non-inverting input end are respectively connected with the first capacitor in series and grounded; the first output end is connected with an S pin of the RS trigger, the second output end is connected with an R pin of the RS trigger, a Q pin of the RS trigger is connected with a second driving signal output node, the Q pin of the RS trigger is connected with the input end of the inverter, and the output end of the inverter is connected with a first driving signal output node; the switching tube S1 and the switching tube S2 are connected in series between a power supply and the ground, and a second potential point between the switching tube S1 and the switching tube S2 is respectively connected with a first inverting input end and the first capacitor; the Q pin of the RS trigger is also connected with the control input of the switching tube S1, and the QN pin of the RS trigger is connected with the control input of the switching tube S2.
Further preferably, the complementary driving signal generating circuit further includes:
the first pull-up resistor is arranged between the power supply and the switching tube S1;
and a first pull-down resistor arranged between the power supply and the switching tube S2.
Further preferably, in the initial state, the complementary driving signal generating circuit divides the power supply voltage by a first voltage dividing resistor and a second voltage dividing resistor, and the potential of the first potential point makes the first signal output end of the first dual operational amplifier output a high level signal; the second driving signal output node outputs a high level signal, and the first driving signal output node outputs a low level signal;
the high-level signal of the first signal output end is connected to the switching tube S1 to be conducted, the low-level signal of the second signal output end is connected to the switching tube S2 to be turned off, and the power supply charges the first capacitor through the first pull-up resistor; when the voltage of the first capacitor exceeds the voltage division on the first voltage dividing resistor, the voltage of the first non-inverting input end is lower than the voltage of the first inverting input end, and the first signal output end outputs a low-level signal; as the charging time is prolonged, the voltage of the first capacitor continues to rise, when the voltage of the first capacitor reaches the power supply voltage, the voltage of the second non-inverting input end is no longer lower than the voltage of the second inverting input end, and the second signal output end outputs a high-level signal; the second driving signal output node outputs a low-level signal, and the first driving signal output node outputs a high-level signal;
the low-level signal of the first signal output end is connected to the switching tube S1 to turn off the switching tube S1, the high-level signal of the second signal output end is connected to the switching tube S2 to turn on the switching tube S2, and the first capacitor discharges through the first pull-down resistor; when the voltage of the first capacitor is reduced to the voltage division on the first voltage dividing resistor, the voltage of the first non-inverting input end is not lower than the voltage of the first inverting input end, and the first signal output end outputs a high-level signal; the second driving signal output node outputs a high level signal again, and the first driving signal output node outputs a low level signal again.
Preferably, the dead time generation circuit includes: the second double-operation amplifier, the first AND gate, the second AND gate, the switching tube S3, the switching tube S4, the switching tube S5, the switching tube S6, the second capacitor, the third voltage dividing resistor and the fourth voltage dividing resistor;
the second double-operation amplifier comprises a power supply input pin, a ground pin, a first in-phase input end, a first reverse-phase input end, a first output end, a second in-phase input end, a second reverse-phase input end and a second output end;
the power supply input pin is connected with power supply voltage, and the third voltage dividing resistor and the fourth voltage dividing resistor are connected in series between the power supply input pin and the ground; the first potential point of the third voltage dividing resistor and the fourth voltage dividing resistor are connected with a first inverting input end and a second inverting input end respectively, and the first non-inverting input end is connected with a second potential point in series and the second capacitor is grounded; the second non-inverting input end is connected with a third potential point in series and the third capacitor is grounded; the switching tube S3 is connected in series between the power supply and the third potential point, and the switching tube S5 is connected in series between the third potential point and the ground; the switch tube S6 is connected in series between the power supply and the second potential point, and the switch tube S4 is connected in series between the second potential point and the ground; the control signals of the switching tube S3 and the switching tube S4 are connected with a first driving signal, and the control signals of the switching tube S5 and the switching tube S6 are connected with a second driving signal; the first drive signal and the second drive signal form a complementary pulse width modulation signal PWM;
the second driving signal and the first output end are connected to the first AND gate, the output end of the first AND gate outputs a second half-bridge output signal, the first driving signal and the second output end are connected to the second AND gate, and the output end of the second AND gate outputs the first half-bridge output signal;
the dead time between the first half-bridge output signal and the second half-bridge output signal has a correlation with the ratio of the third voltage dividing resistor and the fourth voltage dividing resistor.
Further preferably, the dead time between the first half-bridge output signal and the second half-bridge output signal is positively correlated with the ratio of the third voltage dividing resistor to the fourth voltage dividing resistor.
Further preferably, the dead time generation circuit further includes a second pull-up resistor provided between the power supply and a second potential point;
the dead time generation circuit further comprises a second pull-down resistor and a third pull-down resistor, wherein the second pull-down resistor is arranged between the output end of the first AND gate and the ground, and the third pull-down resistor is arranged between the output end of the second AND gate and the ground.
Further preferably, the dead time generation circuit is configured such that in an initial state, the first driving signal is at a low level and the second driving signal is at a high level;
the switch tube S3 is turned off, the switch tube S5 is turned on, the second non-inverting input end is grounded, the second output end outputs a low-level signal, and the output end of the second AND gate outputs a first half-bridge output signal with a low level;
the switching tube S4 is turned off, the switching tube S6 is turned on, and the power supply charges the second capacitor through the pull-up resistor; when the voltage of the second capacitor reaches the voltage division on the third voltage dividing resistor, the voltage of the first non-inverting input end reaches the voltage of the first inverting input end, and the first output end outputs a high-level signal; the output end of the first AND gate outputs a second half-bridge output signal with a high level;
after the first time, the driving signal is turned over, the first driving signal becomes high level, and the second driving signal becomes low level;
the switch tube S4 is turned on, the switch tube S6 is turned off, the second capacitor discharges to the ground, the first in-phase input end is grounded, the first output end outputs a low-level signal, and the output end of the first AND gate outputs a low-level second half-bridge output signal;
the switching tube S3 is conducted, the switching tube S5 is turned off, and the power supply charges the third capacitor through the pull-up resistor; when the voltage of the third capacitor reaches the voltage division on the third voltage dividing resistor, the voltage of the second non-inverting input end is no longer lower than the voltage of the second inverting input end, and the second output end outputs a high-level signal; the output end of the second AND gate outputs a first half-bridge output signal with a high level;
after the first time, the driving signal is turned over again, the first driving signal is changed into a low level again, and the second driving signal is changed into a high level again;
the switch tube S3 is turned on, the switch tube S5 is turned off, the third capacitor discharges to the ground, the second non-inverting input end is grounded, the second output end outputs a low-level signal, and the output end of the second AND gate outputs a first half-bridge output signal with a low level;
the switching tube S4 is conducted, the switching tube S6 is turned off, and the power supply charges the second capacitor through the pull-up resistor; when the voltage of the second capacitor reaches the voltage division on the third voltage dividing resistor, the voltage of the first non-inverting input end is no longer lower than the voltage of the first inverting input end, and the first output end outputs a high-level signal; the output end of the first AND gate outputs a second half-bridge output signal with a high level;
the output of any low-level half-bridge output signal is turned over along with the driving signal and responds at the same time, and the output of any high-level half-bridge output signal is turned over along with the driving signal and responds in a delayed mode.
Further preferably, the second capacitor and the third capacitor have equal capacitance values;
the dead time is the time between the signal falling edge of the first half-bridge output signal and the signal rising edge of the second half-bridge output signal, and
the time between the signal falling edge of the second half-bridge output signal and the signal rising edge of the first half-bridge output signal.
Preferably, the first dual operational amplifier and the second dual operational amplifier are specifically LM358 dual operational amplifiers.
According to the half-bridge driving circuit with adjustable dead time, the first driving signal and the second driving signal which form the complementary pulse width modulation signal are output through the complementary driving signal generating circuit and serve as logic control signals of the dead time generating circuit, so that the first half-bridge output signal and the second half-bridge output signal are output by the dead time generating circuit; the low level output of the first/second half-bridge output signal responds simultaneously with the signal inversion of the first/second driving signal, and the high level output of the first/second half-bridge output signal responds with the signal inversion delay of the first/second driving signal; controlling a flip period of the first/second driving signal by the first voltage dividing circuit; the time of the delay response, i.e. the dead time of the half-bridge driving circuit, is controlled by the second voltage divider circuit. The circuit has the advantages of simple structure, easy realization, low cost, reliable control mode and stable output signal, can be widely applied to different power supply systems, and can improve the reliability of the power supply and the overall efficiency of the power supply.
Drawings
FIG. 1 is a circuit diagram of a dead time adjustable half-bridge drive circuit provided by an embodiment;
fig. 2 is a schematic waveform diagram of an input signal of a dead time generation circuit according to an embodiment;
FIG. 3 is a schematic waveform diagram of a dead time generation circuit according to an embodiment of the present invention;
FIG. 4 is a second schematic waveform diagram of a dead time generation circuit according to an embodiment of the present invention;
FIG. 5 is a third waveform diagram of a dead time generation circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an output waveform of a dead time generation circuit according to an embodiment of the present invention;
fig. 7 is a second schematic diagram of an output waveform of the dead time generation circuit according to the embodiment of the present invention.
Detailed Description
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
An embodiment of the present invention provides a half-bridge driving circuit with adjustable dead time, as shown in fig. 1, including: a complementary drive signal generation circuit 1 and a dead time generation circuit 2.
The complementary driving signal generating circuit 1 includes: the first double-operation amplifier U1, the RS trigger U3, the inverter U4, the switching tube S1, the switching tube S2, the first capacitor C1, the first voltage dividing resistor R13 and the second voltage dividing resistor R14;
in the implementation of the present invention, an LM358 dual op amp is specifically employed. The first dual operational amplifier U1 comprises a power supply input pin V+, a ground pin V-, a first IN-phase input terminal In1+, a first OUT-of-phase input terminal IN1-, a first OUT-of-output terminal OUT1, a second IN-phase input terminal In2+, a second IN-of-phase input terminal IN2-, and a second OUT-of-output terminal OUT2;
the power supply input pin V+ and the second inverting input end IN 2-are respectively connected with a power supply voltage of 5V, and the first voltage dividing resistor R13 and the second voltage dividing resistor R14 are connected IN series between the power supply input pin and the ground; the first potential point O1 where the first voltage dividing resistor R13 and the second voltage dividing resistor R14 are connected is connected with a first IN-phase input end In1+, and a first out-phase input end IN 1-and a second IN-phase input end In2+ are respectively connected IN series with a first capacitor C1 to be grounded; the first output end OUT1 is connected with an S pin of the RS trigger U3, the second output end OUT2 is connected with an R pin of the RS trigger U3, a Q pin of the RS trigger U3 is connected with a second driving signal output node VGLp, a Q pin of the RS trigger U3 is connected with an input end of the inverter U4, and an output end of the inverter U4 is connected with a first driving signal output node VGLp; the switching tube S1 and the switching tube S2 are connected IN series between a power supply and the ground, and a second potential point O2 between the switching tube S1 and the switching tube S2 is connected with a first inverting input end IN 1-and a first capacitor C1;
the Q pin of the RS trigger U3 is also connected with the control input of the switching tube S1, and the QN pin of the RS trigger U3 is connected with the control input of the switching tube S2.
The complementary driving signal generating circuit 1 further includes a first pull-up resistor R10 and a first pull-down resistor R11, the first pull-up resistor R10 being disposed between the power supply and the switching tube S1, and the first pull-down resistor R11 being disposed between the power supply and the switching tube S2.
IN an initial state, the complementary driving signal generating circuit 1 divides a power supply voltage by a first voltage dividing resistor R13 and a second voltage dividing resistor R14, the potential of the first potential point O1 makes the voltage of the first IN-phase input terminal in1+ of the first dual operational amplifier U1 higher than the voltage of the first inverting input terminal IN1-, and the first signal output terminal OUT1 outputs a high level signal; the second driving signal output node VgLp outputs a high level signal, and the first driving signal output node VgHp outputs a low level signal;
the high-level signal of the first signal output end OUT1 is connected to the switching tube S1 to be conducted, the low-level signal of the second signal output end OUT2 is connected to the switching tube S2 to be turned off, and the power supply charges the first capacitor C1 through the first pull-up resistor R10; when the voltage of the first capacitor C1 exceeds the voltage division on the first voltage division resistor R13, the voltage of the first IN-phase input end In1+ is lower than the voltage of the first reverse-phase input end IN1-, and the first signal output end OUT1 outputs a low-level signal; along with the extension of the charging time, the voltage of the first capacitor C1 continuously rises, when the voltage of the first capacitor C1 reaches the power supply voltage, the voltage of the second non-inverting input end IN < 2+ > is no longer lower than the voltage of the second inverting input end IN < 2 >, and the second signal output end OUT < 2 > outputs a high-level signal; the second driving signal output node VgLp outputs a low level signal, and the first driving signal output node VgHp outputs a high level signal;
the low-level signal of the first signal output end OUT1 is connected to the switching tube S1 to be turned off, the high-level signal of the second signal output end OUT2 is connected to the switching tube S2 to be turned on, and the first capacitor C1 is discharged through the first pull-down resistor R11; when the voltage of the first capacitor C1 is reduced to the voltage division of the first voltage dividing resistor R13, the voltage of the first non-inverting input terminal IN1+ is not lower than the voltage of the first inverting input terminal IN1-, and the first signal output terminal OUT1 outputs a high-level signal; the second driving signal output node VgLp outputs the high level signal again, and the first driving signal output node VgHp outputs the low level signal again.
This is repeated.
Thus, the second driving signal (also referred to as VgLp in the figure) output from the second driving signal output node VgLp and the first driving signal (also referred to as VgHp in the figure) output from the first driving signal output node VgHp constitute the complementary pulse width modulation signal PWM, and the signal waveforms are as shown in fig. 2.
In this example, the resistance values of the first voltage dividing resistor R13 and the second voltage dividing resistor R14 are set to 10:1. in a specific application, the signal conversion period of the complementary driving signal can be changed by changing the voltage division ratio of the voltage division circuit.
In the complementary driving signal generating circuit, the node voltage of the power supply voltage and the node voltage of the voltage dividing circuit are respectively used as two potential references, the switching circuit controls the on/off of the switch by using the output signal of the first double operational amplifier so as to control the charge and discharge of the first capacitor, and the voltage of the first capacitor is compared with the voltage of the potential references to be used as the output control of the first double operational amplifier. The signal conversion period of the complementary driving signal can be changed by changing the voltage division ratio of the voltage division circuit.
The dead time generation circuit 2 includes: the second double-operation amplifier U2, the first AND gate U7, the second AND gate U8, the switching tube S3, the switching tube S4, the switching tube S5, the switching tube S6, the second capacitor C2, the third capacitor C3, the third voltage dividing resistor R15 and the fourth voltage dividing resistor R16;
in the implementation of the present invention, the second dual operational amplifier U2 also specifically employs an LM358 dual operational amplifier. The second double operational amplifier U2 comprises a power supply input pin V+, a ground pin V-, a first IN-phase input terminal In1+, a first OUT-of-phase input terminal IN1-, a first OUT-of-output terminal OUT1, a second IN-phase input terminal In2+, a second IN-of-phase input terminal IN2-, and a second OUT-of-output terminal OUT2;
the power supply input pin V+ is connected with the power supply voltage 5V, and the third voltage dividing resistor R15 and the fourth voltage dividing resistor R16 are connected in series between the power supply input pin V+ and the ground; the first potential point O3 connected with the third voltage dividing resistor R15 and the fourth voltage dividing resistor R16 is respectively connected with the first inverting input end IN 1-and the second inverting input end IN2-, and the first non-inverting input end In1+ is connected with the second potential point O4 IN series with the second capacitor C2 to be grounded; the second non-inverting input end In2+ is connected with a third potential point O5 IN series with a third capacitor C3 to be grounded; the switching tube S3 is connected in series between the power supply and the third potential point O5, and the switching tube S5 is connected in series between the third potential point O5 and the ground; the switch tube S6 is connected in series between the power supply and the second potential point O4, and the switch tube S4 is connected in series between the second potential point O4 and the ground; the control signals of the switching tube S3 and the switching tube S4 are connected with a first driving signal VgHp output by the half-bridge driving circuit 1, and the control signals of the switching tube S5 and the switching tube S6 are connected with a second driving signal VgLp output by the half-bridge driving circuit 1; the first driving signal VgHp and the second driving signal VgLp constitute a complementary pulse width modulation signal (PWM); the circuit further comprises a second pull-up resistor R2, wherein the second pull-up resistor R2 is arranged between the power supply and the second potential point O4.
The second driving signal VgLp and the first output end OUT1 are connected to the first and gate U7, the output end of the first and gate U7 outputs a second half-bridge output signal VgL, the first driving signal VgHp and the second output end OUT2 are connected to the second and gate U8, and the output end of the second and gate U8 outputs a first half-bridge output signal VgH; the circuit further comprises a second pull-down resistor R1 and a third pull-down resistor R2, wherein the second pull-down resistor R1 is arranged between the output end of the first AND gate U7 and the ground, and the third pull-down resistor R2 is arranged between the output end of the second AND gate U8 and the ground.
In the initial state of the circuit, the first driving signal VgHp is low level, and the second driving signal VgLp is high level;
the switch tube S3 is turned off, the switch tube S5 is turned on, the second IN-phase input end In2+ is grounded, the second output end OUT2 outputs a low-level signal, and the output end of the second AND gate U8 outputs a first half-bridge output signal VgH with a low level;
the switching tube S4 is turned off, the switching tube S6 is turned on, and the power supply charges the second capacitor C2 through the second pull-up resistor R2; when the voltage of the second capacitor C2 reaches the voltage division on the third voltage division resistor R15, the voltage of the first non-inverting input end IN1+ reaches the voltage of the first inverting input end IN1-, and the first output end OUT1 outputs a high-level signal; since the second driving signal VgLp is at a high level, the output terminal of the first and gate U7 outputs the second half-bridge output signal VgL at a high level;
after the first time, a driving signal inversion occurs, the first driving signal VgHp becomes a high level, and the second driving signal VgLp becomes a low level; the first time is the signal inversion time of the first driving signal and the second driving signal;
the switch tube S4 is turned on, the switch tube S6 is turned off, the second capacitor C2 discharges to the ground, the first IN-phase input end In1+ is grounded, the first output end OUT1 outputs a low-level signal, and the output end of the first AND gate U7 outputs a low-level second half-bridge output signal Vgl;
the switching tube S3 is turned on, the switching tube S5 is turned off, and the power supply charges the third capacitor C3 through the second pull-up resistor R2; when the voltage of the third capacitor C3 reaches the voltage division of the third voltage dividing resistor R15, the voltage of the second non-inverting input terminal IN < 2+ > is no longer lower than the voltage of the second inverting input terminal IN < 2 > -, and the second output terminal OUT < 2 > outputs a high-level signal; since the first driving signal VgHp is also at a high level, the output terminal of the second and gate U8 outputs the first half-bridge output signal VgH at a high level;
after the first time, the driving signal is turned over again, the first driving signal VgHp becomes low level again, and the second driving signal VgLp becomes high level again;
the switching tube S3 is turned on, the switching tube S5 is turned off, the third capacitor C3 discharges to the ground, the second IN-phase input end In2+ is grounded, the second output end OUT2 outputs a low-level signal, and the output end of the second AND gate U8 outputs a first half-bridge output signal VgH with a low level;
the switching tube S4 is turned on, the switching tube S6 is turned off, and the power supply charges the second capacitor C2 through the second pull-up resistor R2; when the voltage of the second capacitor C2 reaches the voltage division on the third voltage division resistor R15, the voltage of the first non-inverting input end IN1+ is no longer lower than the voltage of the first inverting input end IN1-, and the first output end OUT1 outputs a high-level signal; the second driving signal VgLp is also at a high level, and the output end of the first and gate U7 outputs a second half-bridge output signal VgL at a high level;
this is repeated.
Fig. 3, fig. 4, and fig. 5 are schematic waveforms of nodes of the dead time generation circuit according to the embodiment of the present invention. The waveform relationship of the output signal of the first half bridge is taken as an example in each figure.
It can be seen that in this process, the output of any low level half-bridge output signal responds simultaneously with the inversion of the drive signal, and the output of any high level half-bridge output signal responds with the inversion of the drive signal with a delay. That is, the low level output of the first half-bridge output signal responds simultaneously with the signal inversion of the first driving signal, and the high level output of the first half-bridge output signal responds with the signal inversion delay of the first driving signal; the low level output of the second half-bridge output signal responds simultaneously with the signal inversion of the second drive signal, and the high level output of the second half-bridge output signal responds with the signal inversion delay of the second drive signal. As shown in fig. 5, the first half-bridge output signal VgH is inverted after the inversion of the first driving signal VgHp to the high level signal, and the first half-bridge output signal VgH is inverted at the same time when the inversion of the first driving signal VgHp to the low level signal.
The dead time t_dt between the first half-bridge output signal and the second half-bridge output signal has a correlation with the ratio of the third voltage dividing resistor R15 and the fourth voltage dividing resistor R16. Specifically, the dead time between the first half-bridge output signal and the second half-bridge output signal is positively correlated with the ratio of the third voltage dividing resistor R15 and the fourth voltage dividing resistor R16. Still further, the dead time between the first half-bridge output signal and the second half-bridge output signal is directly proportional to the ratio of the third voltage dividing resistor R15 and the fourth voltage dividing resistor R16.
The formula is charged by the capacitor: uc=u× [1-exp (-t/RC) ], where U is the supply voltage, 5V. In the actual circuit, the capacitance values of the second capacitor C2 and the third capacitor C3 are equal, and the first output terminal OUT 1/the second output terminal OUT2 are determined to be output as a high level signal or a low level signal by comparing the voltage division across the third voltage dividing resistor R15 with the capacitor voltage as a comparison reference. Therefore, the delay time for turning the low-level signal to the high-level signal can be correspondingly adjusted by adjusting the voltage division ratio of the third voltage division resistor R15 and the fourth voltage division resistor R16.
In one circuit we actually implement, R15/R16 is 0.04, R15 is 0.2V, and dead time t=68ns, as shown in fig. 6.
In another circuit we actually implement, R15/R16 is 0.08, R15 is 0.4V, and dead time t=136 ns, as shown in fig. 7.
The dead time generating circuit of the invention takes the node voltage of the voltage dividing circuit as two potential references respectively, the switching circuit controls the on/off of the output signal of the second double-operation amplifier so as to control the charge and discharge of the two paths of capacitors, the voltage of the two paths of capacitors is compared with the voltage of the potential references respectively to be used as the output control of the second double-operation amplifier, and the output of the half-bridge driving signal is realized through AND logic. The dead time can be flexibly set by adjusting the voltage division ratio of the voltage division circuit.
The model, capacitance, resistance, etc. of each component shown in fig. 1 are examples of practical implementation of the present invention, and are not intended to limit the present invention to only those components with such specifications, i.e., to limit the protection scope of the circuit implementing the present invention.
According to the half-bridge driving circuit with adjustable dead time, the first driving signal and the second driving signal which form the complementary pulse width modulation signal are output through the complementary driving signal generating circuit and serve as logic control signals of the dead time generating circuit, so that the first half-bridge output signal and the second half-bridge output signal are output by the dead time generating circuit; the low level output of the first/second half-bridge output signal responds simultaneously with the signal inversion of the first/second driving signal, and the high level output of the first/second half-bridge output signal responds with the signal inversion delay of the first/second driving signal; controlling a flip period of the first/second driving signal by the first voltage dividing circuit; the time of the delay response, i.e. the dead time of the half-bridge driving circuit, is controlled by the second voltage divider circuit. The circuit has the advantages of simple structure, easy realization, low cost, reliable control mode and stable output signal, can be widely applied to different power supply systems, and can improve the reliability of the power supply and the overall efficiency of the power supply.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of function in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims (9)

1. A half-bridge drive circuit with adjustable dead time, the half-bridge drive circuit comprising: a complementary driving signal generating circuit and a dead time generating circuit;
the complementary driving signal generating circuit comprises a first voltage dividing circuit; the dead time generation circuit includes a second voltage division circuit;
the complementary driving signal generating circuit outputs a first driving signal through a first driving signal output node and outputs a second driving signal through a second driving signal output node, and the first driving signal and the second driving signal form a complementary pulse width modulation signal PWM;
the first driving signal and the second driving signal are used as control signals and logic signals of a dead time generating circuit, so that two output ends of the dead time generating circuit respectively output a first half-bridge output signal and a second half-bridge output signal;
the low level output of the first half-bridge output signal responds simultaneously along with the signal inversion of the first driving signal, and the high level output of the first half-bridge output signal responds in a delayed manner along with the signal inversion of the first driving signal; the low level output of the second half-bridge output signal responds simultaneously along with the signal inversion of the second driving signal, and the high level output of the second half-bridge output signal responds in a delayed manner along with the signal inversion of the second driving signal;
the first voltage dividing circuit is used for controlling the turnover period of the first driving signal and the second driving signal; the second voltage dividing circuit is used for controlling the time of the delay response, namely the dead time of the half-bridge driving circuit;
the complementary driving signal generating circuit includes: the switching circuit comprises a first double operational amplifier, an RS trigger, an inverter, a switching tube S1, a switching tube S2, a first capacitor, a first voltage dividing resistor and a second voltage dividing resistor;
the first double-operation amplifier comprises a power supply input pin, a ground pin, a first in-phase input end, a first reverse-phase input end, a first output end, a second in-phase input end, a second reverse-phase input end and a second output end;
the power supply input pin and the second inverting input end are respectively connected with power supply voltage, and the first voltage dividing resistor and the second voltage dividing resistor are connected in series between the power supply input pin and the ground; the first voltage division resistor is connected with the first voltage division resistor, the first voltage division resistor is connected with the first non-inverting input end, and the first inverting input end and the second non-inverting input end are respectively connected with the first capacitor in series and grounded; the first output end is connected with an S pin of the RS trigger, the second output end is connected with an R pin of the RS trigger, a Q pin of the RS trigger is connected with a second driving signal output node, the Q pin of the RS trigger is connected with the input end of the inverter, and the output end of the inverter is connected with a first driving signal output node; the switching tube S1 and the switching tube S2 are connected in series between a power supply and the ground, and a second potential point between the switching tube S1 and the switching tube S2 is respectively connected with a first inverting input end and the first capacitor; the Q pin of the RS trigger is also connected with the control input of the switching tube S1, and the QN pin of the RS trigger is connected with the control input of the switching tube S2.
2. The half-bridge drive circuit of claim 1, wherein the complementary drive signal generation circuit further comprises:
the first pull-up resistor is arranged between the power supply and the switching tube S1;
and a first pull-down resistor arranged between the power supply and the switching tube S2.
3. The half-bridge driving circuit according to claim 1, wherein the complementary driving signal generating circuit is configured such that in an initial state, a power supply voltage is divided by a first voltage dividing resistor and a second voltage dividing resistor, and a potential of the first potential point is such that the first output terminal of the first dual operational amplifier outputs a high level signal; the second driving signal output node outputs a high level signal, and the first driving signal output node outputs a low level signal;
the high-level signal of the first output end is connected to the switching tube S1 to be conducted, the low-level signal of the second output end is connected to the switching tube S2 to be turned off, and the power supply charges the first capacitor through the first pull-up resistor; when the voltage of the first capacitor exceeds the voltage division on the first voltage dividing resistor, the voltage of the first non-inverting input end is lower than the voltage of the first inverting input end, and the first output end outputs a low-level signal; as the charging time is prolonged, the voltage of the first capacitor continues to rise, when the voltage of the first capacitor reaches the power supply voltage, the voltage of the second non-inverting input end is no longer lower than the voltage of the second inverting input end, and the second output end outputs a high-level signal; the second driving signal output node outputs a low-level signal, and the first driving signal output node outputs a high-level signal;
the low-level signal of the first output end is connected to the switching tube S1 to turn off the switching tube S1, the high-level signal of the second output end is connected to the switching tube S2 to turn on the switching tube S2, and the first capacitor discharges through the first pull-down resistor; when the voltage of the first capacitor is reduced to the voltage division on the first voltage dividing resistor, the voltage of the first non-inverting input end is not lower than the voltage of the first inverting input end, and the first output end outputs a high-level signal; the second driving signal output node outputs a high level signal again, and the first driving signal output node outputs a low level signal again.
4. The half-bridge driving circuit according to claim 1, wherein the dead time generation circuit includes: the second double-operation amplifier, the first AND gate, the second AND gate, the switching tube S3, the switching tube S4, the switching tube S5, the switching tube S6, the second capacitor, the third voltage dividing resistor and the fourth voltage dividing resistor;
the second double-operation amplifier comprises a power supply input pin, a ground pin, a first in-phase input end, a first reverse-phase input end, a first output end, a second in-phase input end, a second reverse-phase input end and a second output end;
the power supply input pin is connected with power supply voltage, and the third voltage dividing resistor and the fourth voltage dividing resistor are connected in series between the power supply input pin and the ground; the first potential point of the third voltage dividing resistor and the fourth voltage dividing resistor are connected with a first inverting input end and a second inverting input end respectively, and the first non-inverting input end is connected with a second potential point in series and the second capacitor is grounded; the second non-inverting input end is connected with a third potential point in series and the third capacitor is grounded; the switching tube S3 is connected in series between the power supply and the third potential point, and the switching tube S5 is connected in series between the third potential point and the ground; the switch tube S6 is connected in series between the power supply and the second potential point, and the switch tube S4 is connected in series between the second potential point and the ground; the control signals of the switching tube S3 and the switching tube S4 are connected with a first driving signal, and the control signals of the switching tube S5 and the switching tube S6 are connected with a second driving signal; the first drive signal and the second drive signal form a complementary pulse width modulation signal PWM;
the second driving signal and the first output end are connected to the first AND gate, the output end of the first AND gate outputs a second half-bridge output signal, the first driving signal and the second output end are connected to the second AND gate, and the output end of the second AND gate outputs the first half-bridge output signal;
the dead time between the first half-bridge output signal and the second half-bridge output signal has a correlation with the ratio of the third voltage dividing resistor and the fourth voltage dividing resistor.
5. The half-bridge drive circuit of claim 4, wherein a dead time between the first half-bridge output signal and the second half-bridge output signal is positively correlated with a ratio of the third voltage dividing resistor to the fourth voltage dividing resistor.
6. The half-bridge drive circuit according to claim 4, wherein the dead time generation circuit further includes a second pull-up resistor, the second pull-up resistor being provided between a power supply and a second potential point;
the dead time generation circuit further comprises a second pull-down resistor and a third pull-down resistor, wherein the second pull-down resistor is arranged between the output end of the first AND gate and the ground, and the third pull-down resistor is arranged between the output end of the second AND gate and the ground.
7. The half-bridge driving circuit according to claim 4, wherein the dead time generation circuit is in an initial state, the first driving signal is at a low level, and the second driving signal is at a high level;
the switch tube S3 is turned off, the switch tube S5 is turned on, the second non-inverting input end is grounded, the second output end outputs a low-level signal, and the output end of the second AND gate outputs a first half-bridge output signal with a low level;
the switching tube S4 is turned off, the switching tube S6 is turned on, and the power supply charges the second capacitor through the pull-up resistor; when the voltage of the second capacitor reaches the voltage division on the third voltage dividing resistor, the voltage of the first non-inverting input end reaches the voltage of the first inverting input end, and the first output end outputs a high-level signal; the output end of the first AND gate outputs a second half-bridge output signal with a high level;
after the first time, the driving signal is turned over, the first driving signal becomes high level, and the second driving signal becomes low level;
the switch tube S4 is turned on, the switch tube S6 is turned off, the second capacitor discharges to the ground, the first in-phase input end is grounded, the first output end outputs a low-level signal, and the output end of the first AND gate outputs a low-level second half-bridge output signal;
the switching tube S3 is conducted, the switching tube S5 is turned off, and the power supply charges the third capacitor through the pull-up resistor; when the voltage of the third capacitor reaches the voltage division on the third voltage dividing resistor, the voltage of the second non-inverting input end is no longer lower than the voltage of the second inverting input end, and the second output end outputs a high-level signal; the output end of the second AND gate outputs a first half-bridge output signal with a high level;
after the first time, the driving signal is turned over again, the first driving signal is changed into a low level again, and the second driving signal is changed into a high level again;
the switch tube S3 is turned on, the switch tube S5 is turned off, the third capacitor discharges to the ground, the second non-inverting input end is grounded, the second output end outputs a low-level signal, and the output end of the second AND gate outputs a first half-bridge output signal with a low level;
the switching tube S4 is conducted, the switching tube S6 is turned off, and the power supply charges the second capacitor through the pull-up resistor; when the voltage of the second capacitor reaches the voltage division on the third voltage dividing resistor, the voltage of the first non-inverting input end is no longer lower than the voltage of the first inverting input end, and the first output end outputs a high-level signal; the output end of the first AND gate outputs a second half-bridge output signal with a high level;
the output of any low-level half-bridge output signal is turned over along with the driving signal and responds at the same time, and the output of any high-level half-bridge output signal is turned over along with the driving signal and responds in a delayed mode.
8. The half-bridge driving circuit according to claim 4, wherein the second capacitor and the third capacitor have equal capacitance values;
the dead time is the time between the signal falling edge of the first half-bridge output signal and the signal rising edge of the second half-bridge output signal, and
the time between the signal falling edge of the second half-bridge output signal and the signal rising edge of the first half-bridge output signal.
9. The half-bridge driving circuit according to claim 1, wherein the first and second dual operational amplifiers are in particular LM358 dual operational amplifiers.
CN202210464485.4A 2022-04-29 2022-04-29 Half-bridge driving circuit with adjustable dead time Active CN114900030B (en)

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CN102256425A (en) * 2011-06-23 2011-11-23 西安电子科技大学 Self-adaptive dead-zone time control circuit in half-bridge driver chip of electronic ballast
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CN113300576A (en) * 2021-06-30 2021-08-24 芜湖麦可威电磁科技有限公司 System for generating phase-shift driving signal

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CN102256425A (en) * 2011-06-23 2011-11-23 西安电子科技大学 Self-adaptive dead-zone time control circuit in half-bridge driver chip of electronic ballast
CN203233336U (en) * 2013-04-08 2013-10-09 东南大学 A pulse width modulation wave converting circuit for adjusting dead time, high level, and low level
CN103560728A (en) * 2013-11-13 2014-02-05 中国兵器工业集团第二一四研究所苏州研发中心 Motor drive circuit with dead band time delay
CN112737286A (en) * 2021-01-04 2021-04-30 惠州市天宝创能科技有限公司 Single-end-to-double-end driving circuit and adjusting method
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