CN114899230A - III-nitride epitaxial structure and active device thereof and integrated manufacturing method thereof - Google Patents

III-nitride epitaxial structure and active device thereof and integrated manufacturing method thereof Download PDF

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CN114899230A
CN114899230A CN202210369355.2A CN202210369355A CN114899230A CN 114899230 A CN114899230 A CN 114899230A CN 202210369355 A CN202210369355 A CN 202210369355A CN 114899230 A CN114899230 A CN 114899230A
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metal
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fluorine ion
aluminum
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黄知澍
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Abstract

The invention relates to a III-nitride epitaxial structure, an active element thereof and a manufacturing method thereof. Includes a substrate; a high resistance layer of gallium nitride on the substrate; a GaN-Al buffer layer on the GaN high-resistance layer; a gallium nitride channel layer on the gallium aluminum nitride buffer layer; a GaN Al barrier layer on the GaN channel layer; a fluorine ion structure located in the GaN-Al barrier layer; and a first gate insulating dielectric layer on the fluorine ion structure. The gallium aluminum nitride buffer layer is used for preventing electrons with the defects of the buffer layer from entering the channel layer so as to reduce the current collapse effect; the structure is used for manufacturing the gallium nitride enhanced type gallium nitride aluminum/gallium nitride high-speed electron mobility transistor, the mixed type Schottky barrier diode or the mixed type component enhanced type gallium nitride aluminum/gallium nitride high-speed electron mobility transistor.

Description

III-nitride epitaxial structure and active device thereof and integrated manufacturing method thereof
The present application is a divisional application, original parent application No. 2017104184188, application date 2017-06-06, entitled group III/nitride epitaxial structure and active device and integrated manufacturing method thereof.
Technical Field
The invention relates to an epitaxial structure, in particular to an epitaxial structure grown by III group/nitride semiconductor series, which has the advantages that an aluminum gallium nitride barrier layer (i-AlGaN barrier layer) has less defects under the growth environment with an aluminum gallium nitride buffer layer (i-AlGaN buffer layer) so as to reduce the surface defects (surface traces) of the aluminum gallium nitride barrier layer (i-AlGaN barrier layer). As for the gallium aluminum nitride buffer layer (i-AlGaN buffer layer), it can just prevent the electrons of the buffer layer defect (buffer trap) from entering the channel layer (channel layer) and further reduce the problem of Current Collapse effect (Current Collapse).
Background
In the prior art, the most common way to achieve enhanced GaN aluminum/GaN (AlGaN/GaN) HEMT with an epitaxial structure is 1. gallium-Face (Ga-Face) P-GaN Gate (P-GaN Gate) enhanced (E-Mode) HEMT structure (hemtstructure), 2. GaN aluminum Gate (al (x) GaN Gate) enhanced (E-Mode) HEMT structure (hemtstructure), but as the names of the two components indicate, only the Gate (Gate) region will remain P-GaN (P-GaN) or GaN aluminum (al (x) GaN).
The most common process is to additionally grow a P-type gallium nitride (P-GaN) layer on the epitaxial structure of the conventional depletion-Mode (D-Mode) GaN/GaN high-speed electron mobility transistor (AlGaN/GaN HEMT), then dry etch the P-type gallium nitride (P-GaN) outside the Gate (Gate) region, and maintain the integrity of the thickness of the next GaN (AlGaN) epitaxial layer as much as possible, because the next aluminum gallium nitride (AlGaN) epitaxial layer is etched too much, which may cause the formation of two-dimensional electron gas (2-DEG) at the gallium aluminum nitride/gallium nitride (AlGaN/GaN) interface of the gallium-cleaved-plane (Ga-Face) P-type gallium nitride Gate (P-GaN Gate) enhanced high-speed electron mobility transistor (E-Mode HEMT structure) structure. Therefore, the difficulty of dry etching is high because 1, the etching depth is difficult to control, and 2, the thickness of each epitaxial layer on the epitaxial wafer is still uneven; in addition, the problems of Current Collapse (Current collepse) of the epitaxial structure and the general depletion Mode (D-Mode) GaN aluminum/GaN high-speed electron mobility transistor (AlGaN/GaN HEMT) epitaxial structure must be solved, for example: buffer traces and Surface defects (Surface traces).
In view of the above-mentioned drawbacks, the present invention provides a novel III-nitride epitaxial structure and an active device formed by using the epitaxial structure and an integrated manufacturing method thereof.
Disclosure of Invention
The main objective of the present invention is to provide a novel III-nitride epitaxial structure, an active device formed by using the same, and an integrated manufacturing method thereof, so as to solve the process bottleneck encountered by the epitaxial structure in the high-speed electron mobility transistor, and the III-nitride epitaxial structure of the present invention can form a plurality of active devices capable of operating at high voltage and high speed at one time after the process.
Another objective of the present invention is to make the two-dimensional electron gas (2-DEG) of the gallium nitride Channel layer (i-GaN Channel) exhibit a depletion state in the fluorine ion structure by means of a fluorine ion structure, thereby fabricating a GaN-enhanced GaN aluminum/GaN (AlGaN/GaN) hemt, a hybrid schottky barrier diode or a hybrid device.
To achieve the above objective, the present invention provides an aluminum gallium nitride/gallium nitride (AlGaN/GaN) epitaxial structure, which includes a substrate; a gallium nitride high resistance layer (carbon doped) (i-GaN) on the substrate; an aluminum gallium nitride buffer layer (i-AlGaN buffer layer) on the gallium nitride high resistance layer (carbon doped) (i-GaN); a gallium nitride Channel layer (i-GaN Channel) on the gallium aluminum nitride buffer layer (i-AlGaN buffer layer); an aluminum gallium nitride barrier layer (i-AlGaN barrier layer) on the gallium nitride Channel layer (i-GaN Channel); a fluorine ion structure in the GaN aluminum barrier layer (i-AlGaN barrier layer); and a first gate insulating dielectric layer on the fluorine ion structure.
The present invention further provides a plurality of high-speed electron mobility transistors and Schottky barrier diode components with fluorine ion structures, which are manufactured by using the gallium aluminum nitride/gallium nitride (AlGaN/GaN) epitaxial structure, and integrated manufacturing methods thereof.
Drawings
FIG. 1A is a first structure diagram of an epitaxial structure of an AlGaN/GaN high-speed electron mobility transistor (AlGaN/GaN HEMT) designed according to the present invention;
FIG. 1B is a second block diagram of an epitaxial structure of an AlGaN/GaN high-speed electron mobility transistor (AlGaN/GaN HEMT) according to the present invention;
FIG. 2A is a diagram of a first structure of an AlGaN/GaN Schottky barrier diode according to the present invention;
FIG. 2B is a second structural diagram of an AlGaN/GaN Schottky barrier diode according to the present invention;
FIG. 2C is a top view of an AlGaN/GaN (AlGaN/GaN) Schottky barrier diode according to the present invention;
fig. 3A is a schematic view of a first structure of a fluorine ion implantation enhanced gallium aluminum nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor according to the present invention;
fig. 3B is a schematic diagram illustrating a second structure of the fluorine ion implantation enhanced type aluminum gallium nitride/gallium nitride (AlGaN/GaN) high speed electron mobility transistor according to the present invention;
FIG. 3C is a top view of a fluorine ion implantation enhanced gallium aluminum nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor of the present invention;
FIG. 4A is a schematic diagram of forming a source ohmic contact electrode and a drain ohmic contact electrode on an AlGaN/GaN (AlGaN/GaN) epitaxial structure according to the present invention;
FIG. 4B-1, which is a schematic view of a device isolation process according to a first embodiment of the present invention;
FIG. 4B-2, which is a schematic view of a second embodiment of the device isolation process of the present invention;
FIG. 4C-1, which is a schematic illustration of the formation of fluoride ion structures on the structure of FIG. 4B-1;
FIG. 4C-2, which is a schematic illustration of the formation of fluoride ion structures on the structure of FIG. 4B-2;
FIG. 4D-1, which is a schematic view of a first gate insulating dielectric layer formed on the structure of FIG. 4C-1;
FIG. 4D-2, which is a schematic view of a first gate insulating dielectric layer formed on the structure of FIG. 4C-2;
FIG. 4E-1, which is a schematic view of the structure of FIG. 4D-1 with the first gate electrode metal, the source connecting metal and the drain connecting metal formed thereon;
FIG. 4E-2, which is a schematic view of the first gate electrode metal, the source connecting metal and the drain connecting metal formed on the structure of FIG. 4D-2;
fig. 5A is a first structural diagram of the fluoride ion implanted enhanced gallium aluminum nitride/gallium nitride (AlGaN/GaN) high speed electron mobility transistor of the present invention serially connected with a depleted hybrid enhanced gallium aluminum nitride/gallium nitride (AlGaN/GaN) high speed electron mobility transistor without a gate insulating dielectric layer;
FIG. 5B is a second structural diagram of a hybrid enhanced GaN aluminum/gallium nitride (AlGaN/GaN) HEMT of the present invention with a depleted GaN aluminum/gallium nitride (AlGaN/GaN) HEMT in series without a gate insulating dielectric layer;
FIG. 5C is the top view of the fluorine ion implantation enhanced GaN-Al/GaN (AlGaN/GaN) HEMT of the present invention serially connected to a depletion type hybrid enhanced GaN-Al/GaN (AlGaN/GaN) HEMT without a gate insulating dielectric layer GaN-Al/GaN (AlGaN/GaN) HEMT;
FIG. 5D: which is an equivalent circuit diagram of the second embodiment of the present invention;
fig. 6A is a schematic view illustrating a source ohmic contact electrode and a drain ohmic contact electrode formed on an aluminum gallium nitride/gallium nitride (AlGaN/GaN) epitaxial structure according to the present invention;
FIG. 6B-1, which is a schematic view of a device isolation process according to a first embodiment of the present invention;
FIG. 6B-2, which is a schematic view of a device isolation process according to a second embodiment of the present invention;
FIG. 6C-1, which is a schematic illustration of the structure of FIG. 6B-1 forming a fluoride ion structure in accordance with the present invention;
FIG. 6C-2, which is a schematic illustration of the structure of FIG. 6B-2 forming a fluoride ion structure in accordance with the present invention;
FIG. 6D-1, which is a schematic diagram illustrating the formation of a gate oxide layer in the structure of FIG. 6C-1 according to the present invention;
FIG. 6D-2 is a schematic view of gate oxide layer formation in the structure of FIG. 6C-2 according to the present invention;
FIG. 6E-1, which is a schematic view of the structure of FIG. 6D-1 forming a gate electrode metal and a connecting metal in accordance with the present invention;
FIG. 6E-2, which is a schematic view of the structure of FIG. 6D-2 forming a gate electrode metal and a connecting metal in accordance with the present invention;
FIG. 7A is a first structural diagram of a hybrid enhanced gallium aluminum nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor of the present invention in which a fluoride ion implanted enhanced gallium aluminum nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor is serially connected to a depletion type gallium aluminum nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor having a gate insulating dielectric layer;
FIG. 7B is a second schematic diagram of a hybrid enhanced GaN-Al/GaN (AlGaN/GaN) HEMT of the present invention with a gate insulating dielectric layer, in which the enhanced GaN-Al/GaN (AlGaN/GaN) HEMT is serially connected to a depletion type HEMT;
FIG. 7C is the top view of the fluoride ion implanted enhanced GaN-Al/GaN (AlGaN/GaN) HEMT of the present invention serially connected to a depleted hybrid enhanced GaN-Al/GaN (AlGaN/GaN) HEMT with a gate insulating dielectric layer GaN-Al/GaN (AlGaN/GaN) HEMT;
FIG. 7D: which is an equivalent circuit diagram of the third embodiment;
fig. 8A is a schematic view illustrating a source ohmic contact electrode and a drain ohmic contact electrode formed on an aluminum gallium nitride/gallium nitride (AlGaN/GaN) epitaxial structure according to the present invention;
FIG. 8A-1, which is a schematic view of a device isolation process according to a first embodiment of the present invention;
FIG. 8A-2, which is a schematic view of a device isolation process according to a second embodiment of the present invention;
FIG. 8B-1, which is a schematic view illustrating the formation of a fluorine ion structure and a gate oxide layer in the structure of FIG. 8A-1 according to the present invention;
FIG. 8B-2 is a schematic view illustrating formation of a fluorine ion structure and a gate oxide layer on the structure of FIG. 8A-2 according to the present invention;
FIG. 8C-1, which is a schematic view of the structure of FIG. 8B-1 forming a gate electrode metal and a connecting metal in accordance with the present invention;
FIG. 8C-2, which is a schematic view of the structure of FIG. 8B-2 forming a gate electrode metal and a connecting metal in accordance with the present invention;
FIG. 9A-1 is a first diagram of a hybrid Schottky barrier diode having a fluorine ion implantation enhanced gallium aluminum nitride/gallium nitride (AlGaN/GaN) HEMT of the present invention connected in series with a gallium aluminum nitride/gallium nitride (AlGaN/GaN) Schottky barrier diode;
FIG. 9A-2 is a second schematic diagram of a hybrid Schottky barrier diode having a fluorine ion implantation enhanced gallium aluminum nitride/gallium nitride (AlGaN/GaN) HEMT in series with a gallium aluminum nitride/gallium nitride (AlGaN/GaN) Schottky barrier diode according to the present invention;
FIG. 9B is the top view of a hybrid Schottky barrier diode having a GaN/AlGaN (AlGaN/GaN) Schottky barrier diode in series with a fluorine ion implantation enhanced GaN/AlGaN (GaN/GaN) HEMT according to the present invention.
FIG. 9C is the equivalent circuit diagram of a hybrid Schottky barrier diode in which a fluorine ion implantation enhanced gallium aluminum nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor of the present invention is serially connected to a gallium aluminum nitride/gallium nitride (AlGaN/GaN) Schottky barrier diode.
FIG. 10A-1 is a first diagram of a depletion mode AlGaN/GaN (AlGaN/GaN) HEMT of the present invention connected in series with a GaN aluminum/GaN (AlGaN/GaN) Schottky barrier diode (Schottky barrier diode) hybrid Schottky barrier diode;
FIG. 10A-2 is a second block diagram of a depletion mode AlGaN/GaN (AlGaN/GaN) HEMT of the present invention connected in series with a GaN aluminum/GaN (AlGaN/GaN) Schottky barrier diode (Schottky barrier diode) hybrid Schottky barrier diode;
FIG. 10B is a schematic circuit diagram of the depletion mode GaN-Al/GaN (AlGaN/GaN) HEMT of the present invention serially connected to a GaN-Al/GaN (AlGaN/GaN) Schottky barrier diode (Schottky barrier diode) hybrid Schottky barrier diode.
[ brief description of the drawings ]
1 epitaxial structure
11 silicon substrate
12 high resistance buffer layer of gallium nitride (carbon doped)
13 gallium nitride high resistance layer (carbon doped)
14 gan aluminum buffer layer
15 gallium nitride channel layer
150 two-dimensional electron gas
16 gan aluminum barrier layer
160 fluoride ion structure
2 epitaxial structure
21 gallium aluminum nitride buffer layer (aluminum content gradually changed to the same as layer 14)
30 first source electrode metal
31 first drain electrode metal
32 second source electrode metal
33 second drain electrode metal
34 cathode electrode metal
40 ion implantation
41 ion implantation
42 dry etching
43 Dry etching
44 ion implantation
45 ion implantation
46 dry etching
47 dry etching
50 first gate insulating dielectric layer
51 lateral capacitance
52 lateral capacitance
53 second gate insulating dielectric layer
60 first gate electrode metal
601 gate electrode connecting metal
61 first source electrode connection metal
62 first drain electrode connection metal
63 second gate electrode metal
64 second source electrode connecting metal
65 second drain electrode connection metal
66 cathode electrode connecting metal
67 first gate electrode connecting metal
68 first anode electrode
681 first anode electrode (68) connecting metal
682 first anode electrode routing area
70 insulating protective dielectric layer
80 first gate electrode wire bonding area
81 cathode electrode bonding region
82 source electrode routing area
83 drain electrode bonding region
90 anode (with anode electrode metal)
901 anode electrode metal
91 cathode
92 anode field plate insulating dielectric layer
93 cathode metal
AA' section line
D drain electrode
G gate
Left region of L1
Region to the right of R1
S source electrode
Detailed Description
In order to provide a further understanding and appreciation for the structural features and advantages achieved by the present invention, the following detailed description of the presently preferred embodiments is provided:
fig. 1A is a first structural diagram of an epitaxial structure 1 of a GaN aluminum/GaN high-speed electron mobility transistor (AlGaN/GaN HEMT) according to the present invention. The epitaxial structure 1 sequentially comprises a Silicon Substrate (Silicon Substrate)11, a gallium nitride high resistance Buffer layer (carbon-doped) 12, a gallium nitride high resistance layer (carbon-doped) 13, an aluminum gallium nitride Buffer layer (i-AlGaN Buffer layer)14, a gallium nitride channel layer (gan channel layer)15, and an aluminum gallium nitride barrier layer (i-AlGaN barrier layer)16, wherein the aluminum gallium nitride Buffer layer (i-AlGaN Buffer layer)14 mainly functions to prevent electrons of Buffer layer defects (Buffer traps) from entering the gallium nitride channel layer (gan channel layer)15 and further reduce the phenomenon of component Current Collapse (Current Collapse). As shown in fig. 1B, a second structural diagram of the epitaxial structure 2 of the GaN aluminum/GaN high-speed electron mobility transistor (AlGaN/GaN HEMT) designed by the present invention mainly considers that an aluminum gallium nitride Buffer Layer (i-AlGaN Buffer Layer)14 directly grows on a GaN high resistance Layer (carbon doped) (i-GaN Layer (C-doped)13 and has an excessive lattice mismatch problem, so that an aluminum gallium nitride Buffer Layer (aluminum content gradually changes to be the same as that of the 14 th Layer) (i-AlGaN Grading Buffer Layer)21 is added.
Please refer to fig. 2A, which is a first structural diagram of a fluorine ion implanted gallium aluminum nitride/gallium nitride (AlGaN/GaN) schottky barrier diode according to the present invention. As shown, the present invention utilizes fluorine (F-) implantation to grow a "fluorine structure 160" on the AlGaN/GaN (AlGaN/GaN) epitaxial structure 1 of FIG. 1A (or FIG. 1B). Because the two-dimensional electron gas (2-DEG)150 under the region with the grown fluorine ion structure 160 is depleted, the depleted two-dimensional electron gas (2-DEG) can be used to reduce the reverse leakage current generated when reverse bias is applied in circuit applications and increase the reverse breakdown voltage. Please refer to fig. 2B, which is a second structural diagram of a fluorine ion implanted gallium aluminum nitride/gallium nitride (AlGaN/GaN) schottky barrier diode according to the present invention. Fig. 2B is different from fig. 2A in that fig. 2A shows that multiple energy-destructive Ion implantations (Ion-implantations) 40 and 41 are used to complete Device Isolation (Device Isolation) of the Schottky Barrier Diode (SBD), fig. 2B shows that Dry etching 42 and 43 are used to etch the gallium aluminum nitride barrier layer (i-AlGaN barrier layer)16, the gallium nitride Channel layer (i-GaN Channel)15, the gallium aluminum nitride buffer layer (i-AlGaN barrier layer)14, and a portion of the gallium nitride high resistance buffer layer (carbon-doped) (i-GaN (C-doped) layer 13 of the gallium aluminum nitride/gallium nitride (AlGaN/GaN) epitaxial structure 1 to complete Device Isolation (Device Isolation) of the Schottky Barrier Diode (SBD).
FIG. 2C is a top view of a fluorine ion implanted GaN-Al/GaN (AlGaN/GaN) Schottky barrier diode according to the present invention. As shown, FIG. 2C depicts only the insulating protective dielectric layer 70 above the first gate electrode metal (which may be referred to as the anode electrode metal in a Schottky barrier diode) 68. Furthermore, in a top view, when fabricating the Schottky barrier diode, the first anode electrode (68) connecting metal 681 (having the first anode electrode bonding region 682) and the cathode electrode connecting metal 66 having the cathode electrode bonding region 81) are fabricated at the same time.
The structures of fig. 1A and 1B may be further used to fabricate a high-speed electron mobility transistor of the first embodiment, i.e., GaN/AlGaN/GaN.
Fig. 3A is a schematic diagram of a first structure of a fluorine ion implantation enhanced type gallium aluminum nitride (AlGaN/GaN) high-speed electron mobility transistor formed in an i-AlGaN barrier layer 16 according to the present invention. As shown in the figure, the enhanced GaN aluminum/GaN (AlGaN/GaN) high-speed electron mobility transistor of the present invention is characterized by comprising a GaN aluminum/GaN (AlGaN/GaN) epitaxial structure 1 (or 2) designed by the present invention; and a fluorine ion structure 160 located in the gan aluminum barrier layer (i-AlGaN barrier layer)16, wherein the two-dimensional electron gas (2-DEG)150 is formed in the gan channel layer (gan channel layer)15 at the junction of the gan aluminum barrier layer (i-AlGaN barrier layer) 16/gan channel layer (gan channel layer)15, but the two-dimensional electron gas (2-DEG)150 located in the gan channel layer (gan channel layer)15 is in a depletion state below the fluorine ion structure 160 due to the presence of the fluorine ion structure 160.
The structure of enhanced GaN aluminum/GaN (AlGaN/GaN) high-speed electron mobility transistor of the present invention is formed by forming a first source ohmic contact electrode (i.e. a first source electrode metal) 30 and a first drain ohmic contact electrode (i.e. a first drain electrode metal) 31 on a GaN aluminum/GaN (AlGaN/GaN) epitaxial structure 1, and separately disposing on the surface of an i-AlGaN barrier layer 16 of the GaN aluminum/GaN (AlGaN/GaN) epitaxial structure 1, and then forming a fluorine ion structure 160 by fluorine ion implantation, thereby forming a first gate insulating dielectric layer 50 on the fluorine ion structure 160, and forming a first gate metal 60 thereon, and simultaneously forming a source electrode connecting metal 61 connected to the first source ohmic contact electrode 30 and the first drain ohmic contact electrode 31, Drain electrode connecting metal 62 and gate electrode connecting metal 601, etc., wherein the figures 61, 62, 601 all belong to the same metal layer as figure 60, but for convenience of illustration, different figures 61, 62, 601 represent the connecting metal of each electrode, then an insulating protective dielectric layer 70 is covered on the whole surface of the epitaxial chip, and finally, source, drain and gate bonding regions and scribe lines between components on the epitaxial chip are etched on the insulating protective dielectric layer 70. Fig. 3B is a schematic diagram of a second structure of the fluorine Ion implantation enhanced type GaN/aln (AlGaN/GaN) hemt of the present invention, which is different from fig. 3A in that multiple energy-destructive Ion implants (Ion-implants) 40 and 41 are used or Dry etching (Dry etching)42 and 43 are used.
Referring to fig. 3C, a top view of the fluorine ion implantation enhanced type GaN aluminum/GaN (AlGaN/GaN) high speed electron mobility transistor of the present invention is shown. As shown, fig. 3C is different from fig. 2C in that one is a high-speed electron mobility transistor and the other is a schottky barrier diode, so that fig. 3C has a first gate electrode bonding region 80, a source electrode bonding region 82 and a drain electrode bonding region 83, and the first gate electrode bonding region 80 and the cathode electrode bonding region 81 of fig. 2C. In addition, fig. 3C also shows the positions of the gan aluminum barrier layer (i-AlGaN barrier layer)16, the first source electrode metal 30, the first drain electrode metal 31, the first gate insulating dielectric layer 50, the first gate electrode metal 60, the first source electrode connecting metal 61, and the first drain electrode connecting metal 62.
The following is a manufacturing method of the first embodiment, but the present embodiment is not limited to this, and the metal circuit layout is the same.
Please refer to fig. 4A, which is a schematic diagram illustrating a source ohmic contact electrode and a drain ohmic contact electrode formed on a gallium aluminum nitride/gallium nitride (AlGaN/GaN) epitaxial structure according to the present invention. In step S11, the source ohmic contact electrode 30 and the drain ohmic contact electrode 31 are formed. In this step, a metal layer, such as a metal layer generally composed of titanium/aluminum/titanium/gold (Ti/Al/Ti/Au) or titanium/aluminum/nickel/gold (Ti/Al/Ni/Au), is plated on the gallium nitride aluminum/gallium nitride (AlGaN/GaN) epitaxial structure 1 by using a metal evaporation method, and the plated metal layer is patterned into a set pattern by using a metal lift-off method to form a first source electrode metal 30 and a first drain electrode metal 31 on the epitaxial chip (gallium nitride aluminum/gallium nitride (AlGaN/GaN) epitaxial structure 1), and then the first source electrode metal 30 and the first drain electrode metal 31 are subjected to a heat treatment at 700 to 900 ℃ for 30 seconds, so that the first source electrode metal 30 and the first drain electrode metal 31 become ohmic contact electrodes.
Please refer to fig. 4B-1, which is a diagram illustrating a device isolation process according to a first embodiment of the present invention. In step S12, a device isolation process is performed. This step utilizes multiple energy-destructive Ion implants (Ion-implants) 40, 41, typically using heavy atoms such as Boron or Oxygen (Boron or Oxygen), to isolate the device from the device, or as shown in FIG. 4B-2, which is a schematic diagram of a second embodiment of the device isolation process of the present invention. Dry etching (Dry etching)42 and 43 is used to etch the gallium aluminum nitride barrier layer (i-AlGaN barrier layer)16, the gallium nitride Channel layer (i-GaN Channel)15, and the gallium aluminum nitride buffer layer (i-AlGaN buffer layer)14 of the gallium aluminum nitride/gallium nitride (AlGaN/GaN) epitaxial structure 1 to a high resistance gallium nitride (carbon doped) layer (GaN layer) 13, so as to isolate the device from the device.
Please refer to fig. 4C-1, which is a diagram illustrating a fluorine ion structure formed on the structure of fig. 4B-1. In step S13, a fluorine ion implantation process is performed. In this step, F-implantation is performed in the lower gan aluminum nitride barrier Layer (i-AlGaN barrier Layer)16 at the position where the first gate electrode metal 60 (as shown in fig. 4E-1) is to be formed, so that the gan Channel Layer (iggan) 15 in the lower region thereof cannot form the two-dimensional electron gas (2-DEG)150, and then the fluorine ion structure 160 stably occupies the space in the gan aluminum barrier Layer (i-AlGaN barrier Layer)16 after heat treatment at 425 ℃ for 600 seconds.
Furthermore, the fluorine ion implantation process further includes defining a fluorine ion implantation region of the gan aluminum barrier layer (i-AlGaN barrier layer)16 by photolithography exposure and development, generating a fluorine ion plasma in a dry etching system or an ion implanter system by CF4, implanting fluorine ions (F-) into the gan aluminum barrier layer (i-AlGaN barrier layer)16 under a specific electric field (or a specific voltage), and then performing a heat treatment at 425 ℃ for 600 seconds to make the fluorine ion structure 160 stably occupy the space in the gan aluminum barrier layer (i-AlGaN barrier layer) 16. In addition, FIG. 4C-2 is a schematic diagram of the structure of FIG. 4B-2 in which fluorine ions are formed, and is the same as FIG. 4C-1, and therefore, the description thereof is omitted.
Please refer to fig. 4D-1, which is a diagram illustrating a first gate insulating dielectric layer formed on the structure of fig. 4C-1. Step 14: a gate insulation dielectric layer process. Depositing an insulating dielectric layer, which may be silicon oxide, silicon oxynitride (SiOx, SiOxNy) or silicon nitride (SiNx), by Plasma Enhanced Chemical Vapor Deposition (PECVD) to form the first gate insulating dielectric layer 50 with a thickness of 10 to 100nm, and defining the region of the first gate insulating dielectric layer 50 by exposing and developing a photoresist (Photo Resist); finally, the insulating dielectric layer outside the first gate insulating dielectric layer 50 is etched by using a wet etching method using a buffered Oxide etchant (boe) to only leave the region where the first gate insulating dielectric layer 50 is to be formed, and then the photoresist is etched by using a photoresist removing solution. In addition, FIG. 4D-2 is a schematic view of a first gate insulating dielectric layer formed on the structure of FIG. 4C-2, which is the same as FIG. 4D-1 and therefore will not be repeated.
Please refer to fig. 4E-1, which is a diagram illustrating a first gate electrode metal, a source connecting metal and a drain connecting metal formed on the structure of fig. 4D-1. Step S15, metal circuit layout process. This step includes performing metal plating, and patterning the metal layer made of nickel/gold (Ni/Au) by using a metal evaporation and metal lift-off method to form a first gate electrode metal 60, a gate electrode connecting metal 601 (including the first gate electrode Bonding area (Bonding Pad)80 formed in fig. 3C), a source electrode connecting metal (including the source electrode Bonding area (Bonding Pad)82)61, and a drain electrode connecting metal 62 (including the drain electrode Bonding area (Bonding Pad) 83). On the metal layout, for example, the first gate electrode metal 60 on the fluoride ion structure 160 and the first gate insulating dielectric layer 50 is connected to the first gate electrode bonding region 80. In addition, FIG. 4E-2 is a schematic diagram of the first gate electrode metal, the source connecting metal and the drain connecting metal formed on the structure of FIG. 4D-2, which is the same as FIG. 4E-1 and therefore will not be repeated.
Next, in step S16, a dielectric layer is deposited and patterned. This step is to grow an insulating protection dielectric layer 70 by Plasma Enhanced Chemical Vapor Deposition (PECVD), which can be made of silicon oxide, silicon oxynitride (SiOx, SiOxNy) or silicon nitride (SiNx). Finally, the insulating protection dielectric layer 70 is patterned to expose the wire Bonding regions 82 and 83 (the first gate electrode wire Bonding Region 80 shown in fig. 3C), for example, the wire Bonding Region (Bonding Pad Region) is etched by Wet Etching (Wet Etching) using an Oxide buffered Etching solution (boe) (buffered Oxide etch) to form a post wire Bonding Region. After this step is completed, the transistor with fluorine ion implantation enhanced gallium aluminum nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility as shown in fig. 3A and 3B is formed.
In addition, a capacitor having a lateral direction is formed at the position surrounded by the dotted lines in fig. 4E-1 and 4E-2, the lateral capacitors 51 and 52 form a Field Plate Effect (Field Plate Effect), which mainly functions to uniformly disperse the high-density electric Field under the first gate electrode metal 60 by the electric Field of the lateral capacitors 51 and 52, and to use the breakdown voltage (Vds) from the drain to the source of the high-speed Electron mobility transistor, and also to suppress the Electron trapping Effect (Electron trapping Effect) under the first gate electrode metal 60, thereby reducing the Current Collapse Effect (Current colleps) of the high-speed Electron mobility transistor (HEMT) during operation.
In the second embodiment, as shown in fig. 5A and 5B, a first structure diagram and a second structure diagram of a fluorine ion implantation enhanced type gallium aluminum nitride/gallium nitride (AlGaN/GaN) high speed electron mobility transistor are shown, wherein the fluorine ion implantation enhanced type gallium aluminum nitride/gallium nitride (AlGaN/GaN) high speed electron mobility transistor is formed by serially connecting a depletion type gallium aluminum nitride/gallium nitride (AlGaN/GaN) high speed electron mobility transistor without a gate insulating dielectric layer. As shown in fig. 5A and 5B, fluorine ions (F-) are implanted into the GaN aluminum barrier layer (i-AlGaN barrier layer)16 under the first Gate electrode metal 60 to form an enhanced GaN aluminum/GaN (AlGaN/GaN) high speed electron mobility transistor, which is connected in series with a depletion type aluminum/GaN (AlGaN/GaN) high speed electron mobility transistor without a Gate insulating Dielectric layer (Gate Dielectric) to form a "fluorine ion implanted hybrid enhanced GaN aluminum/GaN (AlGaN/GaN) high speed electron mobility transistor".
The fluorine ion implantation hybrid enhanced gallium aluminum nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor can solve the problem that the common gallium aluminum nitride/gallium nitride enhanced high-speed electron mobility transistor (AlGaN/GaN E-Mode HEMT) usually has, namely, the phenomenon that when the component is operated in a saturation region (gate voltage (Vg) is fixed), the on-state current (Ids) is increased along with the increase of drain-source voltage (Vds) is mainly caused by that the depletion region is not cut off (Pinch-off) and the whole Channel (gallium nitride Channel Layer (iGaN Channel Layer)15) is removed, so that the saturation current of the enhanced high-speed electron mobility transistor (E-Mode HEMT) can be just solved by connecting (HEMT) in series to form a depletion type high-speed electron mobility transistor (D-Mode HEMT) and limiting the saturation current of the depletion type high-speed electron mobility transistor (D-Mode) by using the saturation current of the depletion type high-speed electron mobility transistor (D-Mode) This problem is solved.
As shown in fig. 5A and 5B, the hybrid type enhanced GaN-aln/GaN (AlGaN/GaN) hemt of the second embodiment includes a device structure diagram after the GaN-aln/GaN (AlGaN/GaN) epitaxial structure designed by the present invention, which is divided into a left region L1 and a right region R1. The left region L1 is formed with a GaN-enhanced GaN aluminum/GaN (AlGaN/GaN) hemt including a fluorine ion structure 160, wherein the two-dimensional electron gas (2-DEG)150 is formed in the GaN channel layer (GaN channel layer)15 at the interface of the GaN aluminum barrier layer (i-AlGaN barrier layer) 16/GaN channel layer (GaN channel layer)15, but due to the presence of the fluorine ion structure 160, the two-dimensional electron gas (2-DEG)150 in the GaN channel layer (GaN channel layer)15 is in a vacant state below the fluorine ion structure 160. The right region R1 is formed with a depletion type high-speed electron mobility transistor without gate insulating dielectric layer of gallium aluminum nitride/gallium nitride (AlGaN/GaN).
Please refer to fig. 5C, which is a top view of the serial connection of the fluorine ion implantation enhanced type GaN aluminum/GaN (AlGaN/GaN) hemt of the present invention with a depleted type fluorine ion implantation hybrid enhanced type GaN aluminum/GaN (AlGaN/GaN) hemt without a gate insulating dielectric layer. As shown in the figure, a source electrode connecting metal 61 is formed on a first source electrode metal 30 of the fluorine ion implantation enhanced type gallium aluminum nitride/gallium nitride (AlGaN/GaN) high speed electron mobility transistor, and the first source electrode metal 30 is connected with a second gate electrode metal 63 of the depletion type gallium aluminum nitride/gallium nitride (AlGaN/GaN) high speed electron mobility transistor without a gate insulating dielectric layer through the source electrode connecting metal 61, and the first drain electrode connecting metal is electrically connected with the second source electrode connecting metal. In the hybrid enhanced GaN/GaN (AlGaN/GaN) hemt, S in fig. 5C is a source, G is a gate, and D is a drain.
In the manufacturing method of this embodiment, first, as shown in fig. 6A, a source ohmic contact electrode and a drain ohmic contact electrode are formed on a gallium aluminum nitride/gallium nitride (AlGaN/GaN) epitaxial structure according to the present invention. The present invention provides an epitaxial structure of gallium aluminum nitride/gallium nitride (AlGaN/GaN), wherein the left region L1 is set to be used for fabricating a fluorine ion implantation enhanced type gallium aluminum nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor, and the right region R1 is set to be used for fabricating a depletion type gallium aluminum nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor without a gate insulating dielectric layer. It is needless to say that the settings of the left and right side regions L1 and R1 may be changed as needed.
Next, as with the manufacturing method of step 11, a first source electrode metal 30, a first drain electrode metal 31, a second source electrode metal 32 and a second drain electrode metal 33 are formed on the gallium aluminum nitride/gallium nitride (AlGaN/GaN) epitaxial structure of the present invention by using a metal evaporation method in combination with a metal lift-off method, and then the first source electrode metal 30, the first drain electrode metal 31, the second source electrode metal 32 and the second drain electrode metal 33 are subjected to a heat treatment at 700 to 900 ℃ for about 30 seconds, so that the first source electrode metal 30, the first drain electrode metal 31, the second source electrode metal 32 and the second drain electrode metal 33 become a first source ohmic contact electrode 30, a first drain ohmic contact electrode 31, a second source ohmic contact electrode 32 and a second drain ohmic contact electrode 33.
Please refer to fig. 6B-1, which is a diagram illustrating a device isolation process according to a first embodiment of the present invention. Isolation between the device (transistor in the left region L1) and the device (transistor in the right region R1) is performed by performing destructive ion implantation 40, 41, 44, 45 as shown in fig. 6B-1 or dry etching the GaN aluminum/GaN (AlGaN/GaN) epitaxial structure 42, 43, 46, 47 to the high resistance GaN layer (carbon doped)13 as shown in fig. 6B-2. FIG. 6B-2 is a schematic diagram of a device isolation process according to a second embodiment of the present invention, which is similar to the process shown in FIG. 6B-1 and will not be described again.
Please refer to fig. 6C-1, which is a diagram illustrating the formation of a fluoride ion structure in the structure of fig. 6B-1 according to the present invention. As shown in the figure, F-implantation is performed to form a two-dimensional electron gas (2-DEG)150 in the lower gan aluminum nitride barrier Layer (i-AlGaN barrier Layer)16 at the position where the first gate metal 60 is to be formed, so that the gan Channel Layer (iggan Channel Layer)15 in the lower region cannot be formed, and then after heat treatment at 425 ℃ for 600 seconds, the fluorine ion structure stably occupies the space in the gan aluminum Layer (i-AlGaN Layer). FIG. 6C-2 is a schematic diagram of the structure of FIG. 6B-2 forming a fluoride ion structure according to the present invention, which is similar to FIG. 6C-1 and will not be repeated herein.
Refer to FIG. 6D-1, which is a diagram illustrating the formation of a gate insulating dielectric layer 50 in the structure of FIG. 6C-1 according to the present invention. As shown in the figure, a layer of insulating dielectric layer, which may be silicon oxide, silicon oxynitride (SiOx, SiOxNy) or silicon nitride (SiNx), is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) to form the first gate insulating dielectric layer 50 with a thickness of 10 to 100nm, and then a photoresist (Photo Resist) is used to define the region of the first gate insulating dielectric layer by exposure and development; finally, the insulating dielectric layer outside the first gate insulating dielectric layer 50 is etched by using a wet etching method using a buffered Oxide etchant (boe) to only leave the region where the first gate insulating dielectric layer 50 is to be formed, and then the photoresist is etched by using a photoresist removing solution. FIG. 6D-2 is a schematic diagram of the structure of FIG. 6C-2 forming a gate insulating dielectric layer 50 according to the present invention, which is similar to that of FIG. 6C-1 and will not be repeated herein.
Please refer to fig. 6E-1, which is a diagram illustrating the gate electrode metal and the connecting metal formed in the structure of fig. 6D-1 according to the present invention. As shown in the figure, a first gate electrode metal 60, a first source electrode connecting metal (having a source electrode bonding region 82 as shown in fig. 5C) 61, a first drain electrode connecting metal 62, a second gate electrode metal 63, a second source electrode connecting metal 64, and a second drain electrode connecting metal (having a drain electrode bonding region 83 as shown in fig. 5C) 65 are formed by using a metal vapor deposition combined with metal lift-off. Of course, a first gate electrode connecting metal 67 (having a first gate electrode bonding region 80 as shown in fig. 5C) electrically connected to the first gate electrode metal layer 60 may be formed at the same time, and the first gate electrode metal 60, the first source electrode connecting metal 61, the first drain electrode connecting metal 62, the second gate electrode metal 63, the second source electrode connecting metal 64 and the second drain electrode connecting metal 65 are all completed by one-time metal plating, wherein the first source electrode connecting metal 61 is electrically connected to the second gate electrode metal 63, and the first drain electrode connecting metal 62 is electrically connected to the second source electrode connecting metal 64. FIG. 6E-2 is a schematic diagram of the structure of FIG. 6D-2 forming a gate electrode metal and a connecting metal, similar to FIG. 6E-1 and not repeated herein.
Similarly, a layer of insulating protective Dielectric layer (Passivation Dielectric)70 is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD), and finally, the insulating protective Dielectric layer 70 is patterned to expose the wire bonding regions 80, 82, 83 of fig. 5C to complete the structure of fig. 5A, 5B.
As shown in fig. 5A, similarly, a capacitor having a lateral direction is formed at the virtual line, the lateral capacitors 51 and 52 form a Field Plate Effect (Field Plate Effect), and the main function is to uniformly disperse the high-density electric Field under the first gate electrode metal 60 by the electric Field of the lateral capacitors 51 and 52, which is used to increase the drain-to-source breakdown voltage (Vds) of the high-speed Electron mobility transistor and also to suppress the Electron trapping Effect (Electron trapping Effect) under the first gate electrode metal 60 so as to reduce the Current Collapse Effect (Current colleps) of the high-speed Electron mobility transistor during operation.
Please refer to fig. 7A and 7B, which are a first structural diagram and a second structural diagram of a hybrid enhanced GaN aluminum/GaN (AlGaN/GaN) high-speed electron mobility transistor of the present invention, in which a fluoride ion implantation enhanced GaN aluminum/GaN (AlGaN/GaN) high-speed electron mobility transistor is serially connected to a depletion type GaN aluminum/GaN (AlGaN/GaN) high-speed electron mobility transistor having a gate insulating dielectric layer (50). In the third embodiment of the present invention, F-implantation is performed to form an enhanced GaAlxNxNxNxNxNxNxNxNxNxNxNxNxNxNxNxNxNxNxNxNxNxNyNyNyNyNyNxNyNyNyNyNyNyNyNyNyNyTyNyNyNyNyTyNyNyNyNyTyNyNyNyNyNyNyNyNyTyNyNyNyNyTyNyNyNyNyTyNyNyNyNyNyTyNyNyNyNyNyNyNyTyNyNyNyNyNyTyNyNyNyNyNyNyNy under the first Gate electrode 60 (i-AlGaN barrier layer)16 to form a-AlGaN-xNyNyNyNyNyNyNyNyNy-60.
As shown in fig. 7A and 7B, the hybrid enhanced GaN-aln/GaN (AlGaN/GaN) hemt of the third embodiment includes an aluminum gallium nitride/gallium nitride (AlGaN/GaN) epitaxial structure according to the present invention, which is divided into a left region L1 and a right region R1. The left region L1 is formed with a fluorine ion implantation enhanced type GaN aluminum/GaN (AlGaN/GaN) hemt including a fluorine ion structure 160, wherein the two-dimensional electron gas (2-DEG)150 is formed in the GaN channel layer 15 at the junction of the GaN aluminum barrier layer (i-AlGaN barrier layer) 16/GaN channel layer (GaN channel layer)15, but due to the presence of the fluorine ion structure 160, the two-dimensional electron gas (2-DEG)150 in the GaN channel layer 15 is in a depletion state below the fluorine ion structure 160. The right region R1 is formed with a depletion type high-speed electron mobility transistor having a gate insulating dielectric layer of AlGaN/GaN with a second gate insulating dielectric layer 53.
Please refer to fig. 7C, which is a top view of the serial connection of the fluoride ion implantation enhanced type GaN aluminum/GaN (AlGaN/GaN) hemt of the present invention with a depleted type GaN aluminum/GaN (AlGaN/GaN) hemt having a gate insulating dielectric layer. As shown, the depletion-type high-speed electron mobility transistor with a gate insulating dielectric layer of gallium aluminum nitride/gallium nitride (AlGaN/GaN) has a second gate insulating dielectric layer 53, similar to that shown in fig. 5C, which is not repeated.
Please refer to fig. 8A, which is a schematic diagram illustrating a source ohmic contact electrode and a drain ohmic contact electrode formed on a gallium aluminum nitride/gallium nitride (AlGaN/GaN) epitaxial structure according to the present invention. As shown in the figure, an aluminum gallium nitride/gallium nitride (AlGaN/GaN) epitaxial structure of the present invention is provided, and the left region L1 is set to be a fluorine ion implantation enhanced type aluminum gallium nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor, and the right region R1 is set to be a depletion type aluminum gallium nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor with a gate insulating dielectric layer. It is needless to say that the settings of the left and right side regions L1 and R1 may be changed as needed.
Please refer to fig. 8A-1, which is a diagram illustrating a device isolation process according to a first embodiment of the present invention. In the processing method of this embodiment, first, as shown in the second step, a GaN/GaN (AlGaN/GaN) epitaxial structure of the invention is provided, and the left region L1 is set to be a fluorine ion implantation enhanced GaN/GaN (AlGaN/GaN) hemt, and the right region R1 is set to be a depletion type GaN/GaN (AlGaN/GaN) hemt with a gate insulating dielectric layer. Next, as with the above-mentioned fabrication method, a first source electrode metal 30, a first drain electrode metal 31, a second source electrode metal 32 and a second drain electrode metal 33 are formed on the gallium aluminum nitride/gallium nitride (AlGaN/GaN) epitaxial structure of the present invention, and then a device-to-device isolation process is performed. Furthermore, FIG. 8A-2 is a schematic diagram of a device isolation process according to a second embodiment of the present invention, which is similar to FIG. 8A-1 and will not be repeated.
FIG. 8B-1 is a schematic view of forming a fluorine ion structure and a gate insulating dielectric layer on the structure of FIG. 8A-1 according to the present invention. Then, the first gate insulating dielectric layer 50 of the enhanced high-speed electron mobility transistor (E-Mode HEMT) in the left region L1 and the second gate insulating dielectric layer 53 of the depletion type high-speed electron mobility transistor (D-Mode HEMT) in the right region are manufactured, the steps include depositing an insulating dielectric layer made of silicon Oxide, silicon oxynitride (SiOx, SiOxNy) or silicon nitride (SiNx) with a thickness of 10-100 nm by Plasma Enhanced Chemical Vapor Deposition (PECVD), defining the region of the first gate insulating dielectric layer 50 of the enhanced high-speed electron mobility transistor (E-Mode HEMT) and the region of the second gate insulating dielectric layer 53 of the depletion type high-speed electron mobility transistor (D-Mode HEMT) by exposure and development by using a photoresist (Photo Resist), and finally etching the first gate insulating dielectric layer by using a wet etching method using a Buffered Oxide (BOE) (buffered Oxide etch solution) The insulating dielectric layer is etched away from the region 50 and the region 53 except the region 50, and only the region 50 of the first gate insulating dielectric layer of the enhanced high-speed electron mobility transistor (E-Mode HEMT) and the region 53 of the second gate insulating dielectric layer of the depletion type high-speed electron mobility transistor (D-Mode HEMT) are remained, and then the photoresist is etched away by using a photoresist removing solution. Further, FIG. 8B-2 is a schematic view of the structure of FIG. 8A-2 forming a fluorine ion structure and a gate insulating dielectric layer according to the present invention, which is similar to FIG. 8B-1 and will not be repeated.
Please refer to fig. 8C-1, which is a diagram illustrating the formation of gate electrode metal and connecting metal in the structure of fig. 8B-1 according to the present invention. As shown in the figure, a first gate electrode metal 60, a first source electrode connecting metal 61, a first drain electrode connecting metal 62, a second gate electrode metal 63, a second source electrode connecting metal 64 and a second drain electrode connecting metal 65 are formed by metal evaporation (typically nickel/gold (Ni/Au)) + metal lift-off. At this time, a wiring metal portion required for device operation, such as the first gate electrode bonding region 80 connected to the first gate electrode metal 60, may also be formed. The scope of the claims should not be limited by the above description of the drawings. Furthermore, fig. 8C-2 is a schematic diagram of the gate electrode metal and the connecting metal formed in the structure of fig. 8B-2 according to the present invention, which is similar to that of fig. 8C-1 and will not be repeated.
Next, a Passivation Dielectric (Passivation Dielectric) layer 70 is deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD), the material of which may be selected from silicon oxide, silicon oxynitride (SiOx, SiOxNy) or silicon nitride (SiNx), and finally, the Passivation Dielectric layer 70 is patterned to expose the wire bonding regions by etching, thereby forming the structure shown in fig. 7A and 7B.
Similarly, since the first gate electrode metal 60 and the first gate insulating dielectric layer 50 form the lateral capacitors 51 and 52, the lateral capacitors 51 and 52 form a Field Plate Effect (Field Plate Effect), and the electric Field of the lateral capacitors 51 and 52 is used to uniformly disperse the high-density electric Field under the first gate electrode metal 60 and the second gate electrode metal 63, which is used to increase the drain-to-source breakdown voltage (Vds) of the high-speed Electron mobility transistor, and also to suppress the Electron trapping Effect (Electron trapping Effect) under the first gate electrode metal 60 and the second gate electrode metal 63, thereby reducing the Current Collapse Effect (Current colleps) of the high-speed Electron mobility transistor during operation.
Please refer to fig. 9A-1, which is a first structure diagram of a fluorine ion implantation enhanced type GaN aluminum/GaN (AlGaN/GaN) hemt of the present invention serially connected to a GaN aluminum/GaN (AlGaN/GaN) Schottky Barrier Diode (SBD) of a fluorine ion implantation hybrid GaN aluminum/GaN (AlGaN/GaN) schottky barrier diode. In the fourth embodiment of the present invention, a fluorine ion implantation enhanced type gallium aluminum nitride/gallium nitride (AlGaN/GaN) HEMT is connected in series with a gallium aluminum nitride/gallium nitride (AlGaN/GaN) Schottky Barrier Diode (SBD) to form a fluorine ion implantation hybrid Schottky barrier diode. Wherein the Anode (Anode)90 and the first Gate of the Schottky Barrier Diode (SBD) are electrically connected by the first Gate electrode metal (Gate)60, wherein the first Gate electrode metal 60, the Anode electrode metal 901, the cathode metal 93 and the cathode electrode connecting metal 66 therebetween can be simultaneously completed. When a positive voltage is applied to the Anode (Anode)90 of the aluminum gallium nitride/gallium nitride (AlGaN/GaN) Schottky Barrier Diode (SBD), in addition to the conduction of the Schottky Barrier Diode (SBD), the Anode (Anode)90 also applies a positive voltage to the first Gate electrode metal (Gate)60, so that the fluorine ion implantation enhanced aluminum gallium nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor is in a fully conducting state, and thus the current can be smoothly sent to the Cathode (Cathode) 91. When a positive voltage is applied to the cathode 91 (cathode metal 93), the gate voltage (Vgs) of the enhanced GaN aluminum/GaN (AlGaN/GaN) hemt is "negative" so that the GaN enhanced GaN aluminum/GaN (AlGaN/GaN) hemt is in an off state, thereby protecting the GaN aluminum/GaN schottky barrier diode ((AlGaN/GaN) SBD) from breakdown at the reverse voltage. In addition, the fluorine ion implantation enhanced gallium aluminum nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor is a component with a current negative temperature coefficient, and the gallium aluminum nitride/gallium nitride Schottky barrier diode ((AlGaN/GaN) SBD) is a component with a current positive temperature coefficient, so that the two components are mutually connected in series and then have complementary action, so that when the mixed component works at a fixed voltage, the current of the mixed component is not easily influenced by the temperature to change.
The fluorine ion implantation hybrid AlGaN/GaN Schottky barrier diode is characterized in that the two-dimensional electron gas (2-DEG)150 cannot exist under the first gate electrode metal 60 as described above, and the two-dimensional electron gas (2-DEG)150 cannot be recovered unless a positive voltage is applied. Therefore, the cathode 91 can effectively increase the reverse breakdown voltage and suppress the reverse leakage current when it is subjected to the reverse voltage.
As shown in fig. 9A-1 and 9A-2, the fourth embodiment of the fluorine ion implantation hybrid GaN-aln/GaN (AlGaN/GaN) schottky barrier diode mainly includes an GaN-aln/GaN (AlGaN/GaN) epitaxial structure according to the present invention, which is divided into a left region L1 and a right region R1. The left region L1 is formed with a fluorine ion implantation enhanced type GaN aluminum/GaN (AlGaN/GaN) hemt including a fluorine ion structure 160, wherein the two-dimensional electron gas (2-DEG) is formed in the GaN channel layer 15 at the junction of the GaN aluminum barrier layer (i-AlGaN barrier layer) 16/GaN channel layer (GaN channel layer)15, but due to the presence of the fluorine ion structure 160, the two-dimensional electron gas (2-DEG)150 in the GaN channel layer 15 is in a depletion state below the fluorine ion structure 160. The right region R1 is formed with an anode field plate aluminum gallium nitride/gallium nitride (AlGaN/GaN) schottky barrier diode.
In the fourth embodiment, after performing a fluorine ion implantation process on the gallium aluminum nitride/gallium nitride (AlGaN/GaN) epitaxial structure, a first source ohmic contact electrode 30 and a first drain ohmic contact electrode 31 are formed in the left region L1, and a cathode ohmic contact electrode (cathode metal) 34 of the Schottky Barrier Diode (SBD) is formed in synchronization with the right region R1. An anode field plate insulating dielectric 92 is formed on the right region R1, and a first gate insulating dielectric 50 is also formed on the left region L1.
Subsequently, as described previously, the first gate electrode metal 60 and the respective connection metals are formed, for example: a patterned insulating protection dielectric layer 70 is formed on the epitaxial layer (gallium aluminum nitride/gallium nitride (AlGaN/GaN) epitaxial structure) to expose a portion of the insulating dielectric layer, which is formed as the top view shown in fig. 9B, of the first gate electrode connecting metal, the first source electrode connecting metal, and the anode electrode connecting metal of the GaN aluminum/gallium nitride schottky barrier diode ((AlGaN/GaN) SBD), and the related circuit layout metal lead portion of the hybrid GaN aluminum/gallium nitride schottky barrier diode.
FIG. 9B is a top view of a fluorine ion implantation hybrid AlGaN/GaN (AlGaN/GaN) Schottky barrier diode in which the fluorine ion implantation enhanced AlGaN/GaN (AlGaN/GaN) high-speed electron mobility transistor of the present invention is serially connected to a GaN aluminum/GaN (AlGaN/GaN) Schottky Barrier Diode (SBD). As shown, the anode electrode of the fluorine ion implanted hybrid aluminum gallium nitride/gallium nitride (AlGaN/GaN) Schottky Barrier Diode (SBD) and the first gate electrode metal 60 are electrically connected (located under the insulating protection dielectric layer 70) with the first gate electrode metal 60 as a connecting metal. Furthermore, the anode electrode connecting metal of the hybrid aluminum gallium nitride/gallium nitride (AlGaN/GaN) Schottky Barrier Diode (SBD) has an anode electrode bonding region 83, and the cathode electrode metal 93 has a source electrode bonding region 82.
As shown in fig. 10A-1 and 10A-2, the hybrid aluminum gallium nitride/gallium nitride (AlGaN/GaN) schottky barrier diode of the fourth embodiment mainly includes an aluminum gallium nitride/gallium nitride (AlGaN/GaN) epitaxial structure of the present invention, which is divided into a left region L1 and a right region R1. The left region L1 is formed with a depletion type aluminum gallium nitride/gallium nitride (AlGaN/GaN) high-speed electron mobility transistor. The right region R1 is formed with an anode field plate aluminum gallium nitride/gallium nitride (AlGaN/GaN) schottky barrier diode.
When the cathode 91 is given a positive voltage, the gate voltage (Vgs) of the GaN depletion type high-speed electron mobility transistor (D-Mode HEMT) is "negative", so that the GaN depletion type high-speed electron mobility transistor (D-Mode HEMT) is in an off state, thereby protecting the GaN schottky barrier diode ((AlGaN/GaN) SBD) from breakdown at the reverse voltage.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, which is defined by the appended claims.

Claims (21)

1. An AlN/GaN epitaxial structure, comprising:
a substrate;
a GaN high-resistance buffer layer (carbon-doped) on the substrate;
a GaN high resistance layer (carbon doped) on the GaN high resistance buffer layer (carbon doped);
a GaN-Al buffer layer on the GaN high-resistance layer;
a GaN channel layer on the GaN-Al buffer layer;
a GaN-Al barrier layer on the GaN channel layer, the GaN-Al barrier layer including a fluorine ion implantation region therein;
a fluorine ion structure in the fluorine ion implantation region within the gan-al barrier layer; and
a first gate insulating dielectric layer on the fluorine ion implantation region.
2. The structure of claim 1, wherein a gan aluminum buffer layer is further disposed between the gan high resistivity layer and the gan aluminum buffer layer.
3. The structure of claim 1, wherein a two-dimensional electron gas in the GaN channel layer is depleted below the fluoride structure, the two-dimensional electron gas being at a junction of the GaN channel layer and the AlGaN buffer layer.
4. A method of fabricating a fluorine ion implanted enhanced aluminum gallium nitride/gallium nitride high speed electron mobility transistor using the epitaxial structure of claim 1, comprising the steps of:
implanting fluorine ions into the GaN-Al barrier layer under a specific electric field or a specific voltage by using fluorine ion plasma, and then performing heat treatment at 425 ℃ for 600 seconds to form the fluorine ion structure, wherein the fluorine ion structure stably occupies the space of the fluorine ion implantation area in the GaN-Al barrier layer; and
fabricating the first gate insulating dielectric layer on the fluorine ion implantation region.
5. The method of claim 4, wherein the step of forming the fluoride ion structure in the GaN Al barrier layer further comprises:
defining the fluorine ion implanted area of the GaN-Al barrier layer by yellow light exposure and development; and
generating a fluorine ion plasma in a dry etch system or an ion implanter system using CF 4;
implanting fluorine ions into the GaN-Al barrier layer under a specific electric field;
after 425 ℃ and 600 seconds of heat treatment, the fluorine ion structure is stable to occupy the space in the GaN-Al barrier layer.
6. The method of claim 5, wherein the step of forming the first gate insulating dielectric further comprises:
the GaN Al/GaN epitaxial structure; and
defining a region of the first gate insulating dielectric layer by exposing and developing the photoresist;
etching the insulating dielectric layer except the region by using an oxide buffer etching solution in a wet etching mode, and only reserving the region of the first gate insulating dielectric layer; and
the photoresist is etched away with a photoresist removing solution.
7. A method of fabricating a fluorine ion implanted hybrid enhanced gan aluminum/gan high speed electron mobility transistor using the epitaxial structure of claim 1, comprising the steps of:
using destructive ion implantation or dry etching to perform a device isolation process to divide the GaN AlGaN/GaN epitaxial structure into a left region and a right region;
injecting fluorine ions into the GaN-Al barrier layer in the left region under a specific electric field or a specific voltage by using fluorine ion plasma, and then passing through 425 o C. After 600 seconds of heat treatment, the fluorine ion structure is formed and stably occupied in the gallium aluminum nitride barrier layer;
forming the first gate insulating dielectric layer in the left region;
forming a fluorine ion implantation enhanced type gallium aluminum nitride/gallium nitride high-speed electron mobility transistor in the left side area; and
forming a depletion type GaN AlxN/GaN HEMT without gate insulating dielectric layer in the right region.
8. The method of claim 7 for fabricating a hybrid enhanced gan aluminum/gan high-speed electron mobility transistor with implanted fluorine, comprising the steps of:
forming a first source electrode metal and a first drain electrode metal in the left region and a second source electrode metal and a second drain electrode metal in the right region by metal evaporation and metal lift-off; and
performing a heat treatment at 700-900 ℃ for 30 seconds to make the first source electrode metal, the first drain electrode metal, the second source electrode metal and the second drain electrode metal become ohmic contact electrodes.
9. The method of claim 8 for fabricating a hybrid enhanced gan aluminum/gan high-speed electron mobility transistor with implanted fluorine, comprising the steps of:
multiple energy destructive ion implantation is used to isolate the fluorine ion implanted enhanced GaN/GaN HEMT from the fluorine ion implanted depleted GaN/GaN HEMT without gate insulating dielectric layer.
10. The method of claim 8 for fabricating a hybrid enhanced gan aluminum/gan high-speed electron mobility transistor with implanted fluorine, comprising the steps of:
dry etching the GaN-Al barrier layer, the GaN channel layer and the GaN-Al buffer layer to expose part of the GaN high resistance layer for isolating the fluorine ion implantation enhanced GaN-Al/GaN high-speed electron mobility transistor from the fluorine ion implantation depletion type GaN-Al/GaN high-speed electron mobility transistor without gate insulating dielectric layer.
11. The method of claim 8 for fabricating a hybrid enhanced gan aluminum/gan high-speed electron mobility transistor with implanted fluorine, comprising the steps of:
forming a first gate electrode metal, a first source electrode connecting metal, a first drain electrode connecting metal, a second source electrode connecting metal, a second drain electrode connecting metal and a second gate electrode metal by using metal evaporation and metal lift-off methods;
the first gate electrode metal is located on the first gate insulating dielectric layer, the source electrode connecting metal is located on the first source electrode metal, the second gate electrode metal is located in the right side region on the gallium nitride aluminum/gallium nitride epitaxial structure, and the second drain electrode connecting metal is located on the second drain electrode metal.
12. The method of claim 7, wherein the fluoride ion implantation enhanced GaAlN/GaN HEMT and the depletion type GaAlN/GaN HEMT without gate insulating dielectric layer are performed in one step.
13. A method of fabricating a fluoride ion implanted hybrid enhanced gan aluminum/gan high speed electron mobility transistor using the structure of claim 1, comprising the steps of:
using destructive ion implantation or dry etching to perform a device isolation process to divide the GaN AlGaN/GaN epitaxial structure into a left region and a right region;
implanting fluorine ions into the GaN-Al barrier layer in the left region under a specific electric field or a specific voltage by using fluorine ion plasma, and then passing through 425 o C. After 600 seconds of heat treatment, the fluorine ion structure is formed and stably occupies the barrier of the gallium aluminum nitride barrier layer;
making the first gate insulation dielectric layer on the left side region and a second gate insulation dielectric layer on the right side region;
forming a fluorine ion implantation enhanced type gallium aluminum nitride/gallium nitride high-speed electron mobility transistor in the left side area, wherein the fluorine ion implantation enhanced type gallium aluminum nitride/gallium nitride high-speed electron mobility transistor comprises the fluorine ion structure so as to control two-dimensional electron gas below the fluorine ion structure to be in a depletion state; and
forming a depletion type GaN AlxGaN/GaN HEMT with gate insulating dielectric layer in the right region.
14. The method of claim 13, wherein the method comprises the steps of:
forming a first source electrode metal and a first drain electrode metal in the left region and a second source electrode metal and a second drain electrode metal in the right region by metal evaporation and metal lift-off; and
performing a heat treatment at 700-900 ℃ for 30 seconds to make the first source electrode metal, the first drain electrode metal, the second source electrode metal and the second drain electrode metal become ohmic contact electrodes.
15. The method of claim 14 for fabricating a hybrid enhanced gan aluminum/gan high-speed electron mobility transistor with implanted fluorine, comprising the steps of:
forming a first gate electrode metal, a first source electrode connecting metal, a first drain electrode connecting metal, a second source electrode connecting metal, a second drain electrode connecting metal and a second gate electrode metal by using metal evaporation and metal lift-off methods;
the first gate electrode metal is located on the first gate insulating dielectric layer, the first source electrode connecting metal is located on the first source electrode metal, the second gate electrode metal is located on the second gate insulating dielectric layer, and the second drain electrode connecting metal is located on the second drain electrode metal.
16. A method of fabricating a hybrid aluminum gallium nitride/gallium nitride schottky barrier diode using the structure of claim 1, comprising the steps of:
using destructive ion implantation or dry etching to perform a device isolation process to divide the GaN AlGaN/GaN epitaxial structure into a left region and a right region;
implanting fluorine ions into the GaN-Al barrier layer in the left region under a specific electric field or a specific voltage by using fluorine ion plasma, and performing heat treatment at 425 ℃ for 600 seconds to form the fluorine ion structure, wherein the fluorine ion structure is stably occupied in the GaN-Al barrier layer;
making the first gate insulating dielectric layer on the left side region and an anode field plate insulating dielectric layer on the right side region;
forming a fluorine ion implantation enhanced type gallium aluminum nitride/gallium nitride high-speed electron mobility transistor in the left side area, wherein the fluorine ion implantation enhanced type gallium aluminum nitride/gallium nitride high-speed electron mobility transistor comprises the fluorine ion structure so as to control the two-dimensional electron gas to be in a depletion state below the fluorine ion structure; and
forming a GaN/GaN Schottky barrier diode with the anode field plate insulating dielectric layer in the right region.
17. The method of claim 16, wherein the method comprises the steps of:
forming a first source electrode metal and a first drain electrode metal in the left region and a cathode electrode metal in the right region by metal evaporation and metal lift-off; and
heat treatment is performed at 700-900 ℃ for 30 seconds to make the first source electrode metal, the first drain electrode metal and the cathode electrode metal become ohmic contact electrodes.
18. The method of claim 17, wherein the method comprises the steps of:
forming a first gate electrode metal, a first source electrode connecting metal, a first drain electrode connecting metal, a cathode electrode connecting metal and an anode electrode connecting metal simultaneously by using metal evaporation and metal lift-off modes;
the first gate electrode metal is located on the first gate insulating dielectric layer, the first source electrode connecting metal is located on the first source electrode metal, and the anode electrode connecting metal is formed on the anode field plate insulating dielectric layer.
19. A method of fabricating a hybrid aluminum gallium nitride/gallium nitride schottky barrier diode using the structure of claim 1, comprising the steps of:
using destructive ion implantation or dry etching to perform a device isolation process to divide the GaN AlGaN/GaN epitaxial structure into a left region and a right region;
making the first gate insulating dielectric layer on the left side region and an anode field plate insulating dielectric layer on the right side region;
forming a depletion type aluminum gallium nitride/gallium nitride high-speed electron mobility transistor with a gate insulation dielectric layer in the left area; and
forming an AlGaN/GaN Schottky barrier diode with the anode field plate insulating dielectric layer in the right region.
20. The method of claim 19, wherein the method comprises the steps of:
forming a first source electrode metal and a first drain electrode metal in the left region and a cathode electrode metal in the right region by metal evaporation and metal lift-off; and
heat treatment is performed at 700-900 ℃ for 30 seconds to make the first source electrode metal, the first drain electrode metal and the cathode electrode metal become ohmic contact electrodes.
21. The method of claim 20, wherein the method comprises the steps of:
forming a first gate electrode metal, a first source electrode connecting metal, a first drain electrode connecting metal, a cathode electrode connecting metal and an anode electrode connecting metal simultaneously by using metal evaporation and metal lift-off modes;
the first gate electrode metal is located on the first gate insulating dielectric layer, the first source electrode connecting metal is located on the first source electrode metal, and the anode electrode connecting metal is formed on the anode field plate insulating dielectric layer.
CN202210369355.2A 2017-06-06 2017-06-06 III-nitride epitaxial structure and active device thereof and integrated manufacturing method thereof Pending CN114899230A (en)

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