CN114899112A - Chip packaging method - Google Patents

Chip packaging method Download PDF

Info

Publication number
CN114899112A
CN114899112A CN202210486006.9A CN202210486006A CN114899112A CN 114899112 A CN114899112 A CN 114899112A CN 202210486006 A CN202210486006 A CN 202210486006A CN 114899112 A CN114899112 A CN 114899112A
Authority
CN
China
Prior art keywords
chip
layer
semi
metal support
finished
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN202210486006.9A
Other languages
Chinese (zh)
Inventor
王仁群
李清德
李海霞
涂杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing Polytechnic Institute
Original Assignee
Nanjing Polytechnic Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing Polytechnic Institute filed Critical Nanjing Polytechnic Institute
Priority to CN202210486006.9A priority Critical patent/CN114899112A/en
Publication of CN114899112A publication Critical patent/CN114899112A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation

Abstract

The invention provides a chip packaging method, which comprises the following steps: firstly, mounting a chip on the upper surface of a metal support; the second step is that: sputtering a layer of graphene on the lower surface of the metal support of the semi-finished chip; the third step: connecting the semi-finished chip and the lead respectively through a bonding wire; the fourth step: packaging and curing: and processing the bottom of the semi-finished chip structure by using a laser punching or plasma cleaning mode to expose the protruding points of the chip, and performing the processes of pattern passivation, rewiring, lower metal layer deposition and ball grid array embedding by etching to obtain the chip packaging structure. The invention provides a chip packaging method which reduces the phenomena of drifting and warping of a chip, and a layer of graphene is sputtered on the back surface of a metal support of the chip to improve the heat dissipation effect of the chip.

Description

Chip packaging method
Technical Field
The invention belongs to the technical field of integrated circuit packaging, and relates to a chip packaging method.
Background
The chip is a carrier for bearing an integrated circuit, has the advantages of small volume, strong function and the like, and is widely applied to other electronic equipment such as computers and the like. . However, in the existing chip packaging process, due to the difference of thermal expansion coefficients of materials such as plastic, silicon and metal, the internal stress of the chip packaging structure is not uniform, two basic problems of packaging, namely chip drifting and warping, are brought, and in the injection molding stage, if the temporary bonding glue is connected with the chip too loosely, the chip drifting is caused. If the temporary bonding glue is bonded with the chip too tightly, the subsequent process of removing the temporary bonding glue and the glass plate is difficult, and higher internal stress is caused, so that the chip generates a warping phenomenon. Moreover, as chips are continuously developed towards the directions of lightness, thinness, intelligence and exquisiteness, integrated circuits carried on the chips are more and more complex. The power of the chip inevitably becomes larger and larger, and the chip generates excessive heat during operation.
Disclosure of Invention
1. The technical problem to be solved is as follows:
the existing packaging process has the phenomena of chip drifting and warping, and the chip can generate excessive heat in the working process.
2. The technical scheme is as follows:
in order to solve the above problems, the present invention provides a chip packaging method, including the following steps: firstly, mounting a chip on the upper surface of a metal support; the second step is that: sputtering a layer of graphene on the lower surface of the metal support of the semi-finished chip; the third step: connecting the semi-finished chip and the lead respectively through a bonding wire; the fourth step: packaging and curing: and processing the bottom of the semi-finished chip structure by using a laser drilling or plasma cleaning mode to expose the salient points of the chip, and performing pattern passivation, rewiring, metal layer deposition and ball grid array etching embedding processes to obtain the chip packaging structure.
The manufacturing method of the semi-finished chip comprises the following steps: coating a layer of polytetrafluoroethylene or polyvinyl chloride on the upper surface of the glass plate; pressing and arranging an ABF material layer on the spacing layer; under the environment of the temperature of 10-50 ℃, the chip is hot pressed into the ABF material layer according to the orientation of face down, so that the salient points at the bottom of the chip are not fused with the ABF material layer; keeping the environment of the layer 10-layer 50 ℃, performing injection molding to ensure that the chip and the ABF material layer are filled and covered by injection molding materials, and cooling and solidifying to obtain a solidified chip structure; and removing the glass plate and the polytetrafluoroethylene or polyvinyl chloride layer to obtain a semi-finished chip.
In the second step, a layer of graphene is sputtered on the lower surface of the metal support by a chemical vapor deposition method or a physical vapor deposition method.
In the second step, the graphene layer thickness is layer-4 microns.
In a third step, the chip, the bonding wires, the metal support, the graphene layer and a part of the leads are encapsulated by resin.
3. Has the advantages that:
the invention provides a chip packaging method, which can quickly complete the injection molding and curing process after the chip is directly hot-pressed like a material layer, thereby reducing the packaging process and the drift of the chip; in addition, according to the chip packaging method, the polytetrafluoroethylene or polyvinyl chloride is additionally arranged between the glass plate and the ABF material layer, so that the internal stress of the chip packaging structure can be reduced, and the warping phenomenon can be avoided. According to the invention, the graphene layer is sputtered on the back surface of the metal support of the chip to improve the heat dissipation effect of the chip, and heat generated by the chip in the working process can be dissipated through the metal support.
Drawings
FIG. 1 is a flow chart of the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, in an embodiment, a chip packaging method is provided, where the chip packaging method includes the following steps: the first step is as follows: chip mounting: and mounting the semi-finished chip on the upper surface of the metal support. The semi-finished chip mounting is that a semi-finished chip is mounted on the upper surface of the metal support through a conductive adhesive mounting method, a chip bonding agent comprising epoxy resin, polyimide, siloxane polyimide and the like is used for mounting the chip on the upper surface of the metal support in the conductive adhesive mounting method, and silver particles or silver sheets are filled in the chip bonding agent to improve the conductivity of the chip bonding agent. The specific silver particles or silver flakes are present in the die bond in an amount of 75% to 80%.
In another embodiment, the semi-finished chip mounting is to mount a chip on the upper surface of the metal support by an eutectic bonding method. In one embodiment, the die attach is performed by attaching a die to the upper surface of the metal support by a solder attach method. In one embodiment, the chip mounting is to mount the chip on the upper surface of the metal support by a glass cement method.
Secondly, the method comprises the following steps: and sputtering the graphene layer. Specifically, a layer of graphene is sputtered on the lower surface of the metal support. On one hand, the metal support plays a role in supporting and bearing the chip. On the other hand, the metal support plays a role in heat dissipation for the chip, and in this embodiment, the metal support is made of copper. In other embodiments, the metal bracket is made of aluminum alloy. In addition, the metal support is also used for signal transmission between the outside and the chip. Graphene is a single-carbon-atom sheet material exfoliated from graphite materials, consisting of a series of carbon atoms arranged in a honeycomb lattice. This particular structure allows graphene to have superior conductivity to copper. That is to say, graphene does not influence the signal transmission between the outside and the chip. And secondly, the graphene has excellent thermal conductivity which is as high as 5300W/m.k, and has better thermal conductivity than diamond and lower cost.
And (3) wire bonding: connecting the chip and the lead by a bonding wire respectively; in one embodiment, the bonding wire is a thin copper wire, one end of the bonding wire is welded on a bonding pad of the chip, and the other end of the bonding wire is connected with a lead on the glass plate, so that electric appliance interconnection between the chip and the glass plate and information intercommunication between the chips are realized. Under ideal control conditions, electron sharing or atomic interdiffusion can occur between the bonding wire and the glass plate, so that atomic-scale bonding between the two metals is realized. In this embodiment, thermocompression wire bonding is used to connect the bonding wire with the chip and the lead. In other embodiments, wedge ultrasonic wire bonding is used to join the wire bond to the chip and to the wire. In another embodiment, thermosonic wire bonding is used to join the bond wire to the chip and to the wire.
The fourth step: packaging and curing: and processing the bottom of the semi-finished chip structure by using a laser punching or plasma cleaning mode to expose the protruding points of the chip, and performing the processes of pattern passivation, rewiring, lower metal layer deposition and ball grid array embedding by etching to obtain the chip packaging structure. In one embodiment, after pressing the ABF material layer, the protruding points are contacted with the polytetrafluoroethylene or polyvinyl chloride layer, and then the bottom of the semi-finished chip structure is subjected to plasma cleaning, so that the protruding points of the chip are exposed; after the chip is pressed into the ABF material layer, the protruding point is not contacted with the polytetrafluoroethylene or polyvinyl chloride layer, and laser drilling is carried out on the bottom of the semi-finished chip structure, so that the protruding point of the chip is exposed; and then carrying out patterned passivation, rewiring, depositing an under-ball metal layer, etching and embedding into the ball grid array to obtain the chip packaging structure.
Wherein the processes of pattern passivation, rewiring, deposition of a lower metal layer, and etching of an embedded ball grid array are well established process operations in the prior art.
According to the chip packaging method, the heat dissipation effect of the chip is improved by sputtering a layer of graphene on the back surface of the metal support for bearing the semi-finished chip, heat generated in the working process of the semi-finished chip can be dissipated through the metal support, and the graphene layer on the back surface of the metal support can greatly improve the heat dissipation performance of the metal frame. And packaging the semi-finished chip, the bonding wires, the metal support, the graphene layer and part of the leads. On one hand, the chip, the bonding wires, the metal bracket frame, the graphene layer and part of the leads are prevented from contacting with the outside, and the semi-finished chip, the metal bracket, the bonding wires and part of the leads are prevented from being corroded to prolong the service life of the chip. On the other hand, the connection of the semi-finished chip, the bonding wire, the metal support, the graphene layer and part of the leads is further stabilized.
In one embodiment, the manufacturing method of the semi-finished chip comprises the following steps: a) coating a layer of polytetrafluoroethylene or polyvinyl chloride on the upper surface of a glass plate; pressing and arranging an ABF material layer on the isolation layer; pressing the chip 4 into the ABF material layer in a face-down hot pressing mode under a high-temperature environment of 130-00 ℃ to ensure that the protruding points at the bottom of the chip are not fused with the ABF material layer, judging whether the protruding points of the chip in the solidified chip structure are in contact with the polytetrafluoroethylene or polyvinyl chloride layer or not, and recording a judgment result; keeping a high-temperature environment of 130-00 ℃ for injection molding, filling and covering the chip and the ABF material layer by injection molding materials, and cooling and solidifying to obtain a solidified chip structure; and removing the glass plate and the polytetrafluoroethylene or polyvinyl chloride to obtain a semi-finished chip structure.
The invention provides a semi-finished chip packaging structure, the chip packaging method is not suitable for temporary bonding glue, an ABF material layer is directly arranged above glass, and a chip can quickly complete an injection molding solidification process after being directly hot-pressed like the ABF material layer, so that the packaging process is reduced, and the drift of the chip is reduced; in addition, according to the chip packaging method, the polytetrafluoroethylene or polyvinyl chloride is additionally arranged between the glass plate and the ABF material layer, so that the subsequent separation of the glass plate from the solidified chip structure is facilitated, and meanwhile, because the binding force between the ABF material layer and the polytetrafluoroethylene or polyvinyl chloride is not high, the ABF material layer and the chip packaging structure above the ABF material layer can be flexibly solidified and packaged during packaging and solidification, the phenomenon of uneven internal stress cannot occur, the internal stress of the chip packaging structure can be reduced, and the phenomenon of warping is also facilitated to be avoided.

Claims (5)

1. A packaging method of a chip comprises the following steps: firstly, mounting a semi-finished chip on the upper surface of a metal support; the second step is that: sputtering a layer of graphene on the lower surface of the metal support of the semi-finished chip; the third step: connecting the semi-finished chip and the lead respectively through a bonding wire; the fourth step: packaging and curing: and processing the bottom of the semi-finished chip structure by using a laser punching or plasma cleaning mode to expose the salient points of the chip, and performing the processes of pattern passivation, rewiring, lower metal layer deposition and ball grid array embedding etching to obtain the chip packaging structure.
2. The method of claim 1, wherein; the manufacturing method of the semi-finished chip comprises the following steps: coating a layer of polytetrafluoroethylene or polyvinyl chloride on the upper surface of the glass plate; pressing and arranging an ABF material layer on the spacing layer; hot-pressing a chip into the ABF material layer in a face-down orientation at 210-250 ℃ so that the salient points at the bottom of the chip are not fused with the ABF material layer; keeping the temperature of 210-250 ℃, performing injection molding to ensure that the chip and the ABF material layer are filled and covered by injection molding materials, and cooling and solidifying to obtain a solidified chip structure; and removing the glass plate and the polytetrafluoroethylene or polyvinyl chloride layer to obtain a semi-finished chip.
3. The method of claim 1 or 2, wherein: in the second step, a layer of graphene is sputtered on the lower surface of the metal support by a chemical vapor deposition method or a physical vapor deposition method.
4. The method of claim 1 or 2, wherein: in the second step, the graphene layer is 2-4 microns thick.
5. The method of claim 1 or 2, wherein: in a third step, the chip, the bonding wires, the metal support, the graphene layer, and a portion of the leads are encapsulated by resin.
CN202210486006.9A 2022-05-06 2022-05-06 Chip packaging method Withdrawn CN114899112A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210486006.9A CN114899112A (en) 2022-05-06 2022-05-06 Chip packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210486006.9A CN114899112A (en) 2022-05-06 2022-05-06 Chip packaging method

Publications (1)

Publication Number Publication Date
CN114899112A true CN114899112A (en) 2022-08-12

Family

ID=82718957

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210486006.9A Withdrawn CN114899112A (en) 2022-05-06 2022-05-06 Chip packaging method

Country Status (1)

Country Link
CN (1) CN114899112A (en)

Similar Documents

Publication Publication Date Title
TWI719600B (en) Chip packaging method and chip packaging structure
US8987876B2 (en) Power overlay structure and method of making same
CN110178215B (en) Method for manufacturing electronic power modules by additive manufacturing and related substrates and modules
US10269688B2 (en) Power overlay structure and method of making same
CN101273451A (en) Microelectronic package having direct contact heat spreader and method of manufacturing same
CN103855122B (en) Encapsulation vertical power device and its manufacture method including compression stress
TWI829392B (en) Chip packaging method and chip structure
JP2008258547A (en) Semiconductor device, and manufacturing method thereof
JP2001196495A (en) Circuit board for resin molding and electronic package
KR100883807B1 (en) Semiconductor Device Package and Method of Fabricating the Same
CN114899112A (en) Chip packaging method
CN1172369C (en) Semiconductor package with heat radiator
US10269583B2 (en) Semiconductor die attachment with embedded stud bumps in attachment material
CN108573933A (en) Semiconductor device and its manufacturing method
JP4247323B2 (en) Method for bonding a semiconductor device to a conductive plate
JP4249366B2 (en) Metal base circuit board and electronic module manufacturing method
CN111211101A (en) Chip packaging method, structure, circuit board and computer equipment
JP2009043882A (en) High-temperature circuit module and its manufacturing method
CN117542740A (en) Preparation method of semiconductor packaging structure
CN117672871A (en) Preparation method of semiconductor packaging structure
CN117153698A (en) Fan-out type packaging structure of high-density wiring and manufacturing method thereof
TWM620388U (en) Semiconductor device having high heat dissipation efficiency
CN117476479A (en) Preparation method of semiconductor packaging structure
CN117747556A (en) Packaging structure with adhesive layer and packaging method thereof
CN117542822A (en) Semiconductor packaging structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WW01 Invention patent application withdrawn after publication
WW01 Invention patent application withdrawn after publication

Application publication date: 20220812