CN117476479A - Preparation method of semiconductor packaging structure - Google Patents
Preparation method of semiconductor packaging structure Download PDFInfo
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- CN117476479A CN117476479A CN202311408889.2A CN202311408889A CN117476479A CN 117476479 A CN117476479 A CN 117476479A CN 202311408889 A CN202311408889 A CN 202311408889A CN 117476479 A CN117476479 A CN 117476479A
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- chip
- lead frame
- semiconductor package
- functional surface
- column
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 33
- 238000002360 preparation method Methods 0.000 title abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 43
- 239000003292 glue Substances 0.000 claims description 38
- 230000017525 heat dissipation Effects 0.000 claims description 26
- 238000010438 heat treatment Methods 0.000 claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 238000003825 pressing Methods 0.000 claims description 10
- 238000011049 filling Methods 0.000 claims description 6
- 229920001967 Metal rubber Polymers 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 10
- 238000007747 plating Methods 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011068 loading method Methods 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16153—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/16175—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The application provides a preparation method of a semiconductor packaging structure, which comprises the following steps: providing a lead frame and a packaged chip, wherein the packaged chip comprises a packaging structure and a chip, the packaging structure covers the area except the functional surface of the chip, and the functional surface of the chip is provided with a connecting part; and attaching the chip to the lead frame, wherein the functional surface of the chip faces the lead frame, and the lead frame is connected with the bonding pad on the functional surface of the chip through the connecting part. The method is easy to realize, and the semiconductor packaging structure prepared by the method can meet the use requirement of a high-power device.
Description
Technical Field
The application belongs to the field of semiconductors, and particularly relates to a preparation method of a semiconductor packaging structure.
Background
The lead frame is used as a chip carrier of an integrated circuit, is a key structural member for realizing the electric connection between an internal circuit lead-out end of the chip and an external lead by means of bonding materials (gold wires, aluminum wires and copper wires) to form an electric loop, and plays a role of a bridge connected with an external lead, and the lead frame is needed to be used in most of semiconductor integrated blocks, and is an important basic material in the electronic information industry.
However, the matching of the lead frame, the bond and the material cannot meet the use requirement of the high-power device.
Disclosure of Invention
The application provides a preparation method of a semiconductor packaging structure, and the semiconductor packaging structure prepared by the method can meet the use requirement of a high-power device.
In order to solve the technical problems, one technical scheme adopted by the application is as follows: the application provides a preparation method of a semiconductor packaging structure, which comprises the following steps: providing a lead frame and a packaged chip, wherein the packaged chip comprises a packaging structure and a chip, the packaging structure covers the area except the functional surface of the chip, and the functional surface of the chip is provided with a connecting part; the chip is attached to the lead frame with the functional surface of the chip facing the lead frame, and the lead frame is connected with the bonding pads on the functional surface of the chip through the connecting parts.
Wherein the step of providing a packaged chip comprises: forming a metal glue column in a bonding pad area of a functional surface of the chip; and (5) solidifying the metal glue column to obtain the connecting part.
Wherein, solidifying the metal glue column to obtain the step of connecting part, including: and pressing the lead frame on the functional surface of the chip, heating while pressing, and solidifying the metal glue column to form a connecting part for connecting the lead frame and the chip.
Wherein, before pressing the lead frame on the functional surface of the chip, the method comprises the following steps: and forming a supporting pad on the packaged chip, wherein the supporting pad is smaller than the metal glue column in height, so that the supporting pad supports the lead frame during pressing.
Wherein, the step of solidifying the metal glue column to obtain the connecting part comprises the following steps: and heating the metal gel column to obtain the connecting part, wherein the heating temperature is 100-200 ℃.
Preferably, the metal glue column comprises a nano copper glue column, and the connecting part comprises a copper column.
Wherein, the gap of the lead frame, the gap between the functional surface of the chip and the lead frame, and the gap between the packaging structure and the lead frame are filled with the filling material.
Wherein providing the packaged chip includes: providing a temporary carrier plate, and attaching the functional surface of the chip to the temporary carrier plate; forming a packaging structure, wherein the packaging structure covers the back surface and the side surface of the chip; and stripping the temporary carrier plate.
The heat dissipation structure is formed on the back surface of the chip, and the package structure does not cover the heat dissipation structure.
Forming a second heat conduction structure on the back of the chip; and forming a heat dissipation structure on one side of the second heat conduction structure, which is away from the chip.
Wherein the second heat conduction structure comprises heat conduction glue and/or heat conduction metal.
The beneficial effects of this application are: through design connecting portion and chip above the loading area of lead frame, lead frame and bonding pad are connected to connecting portion for high-power current can pass through connecting portion and transmit between chip and lead frame, and make this semiconductor packaging structure can be applicable to high-power device, has the advantage that the integrated level is high, and application scope is wide.
Drawings
For a clearer description of the technical solutions in the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a flow chart of one embodiment of a method for fabricating a semiconductor package in the present application;
fig. 2 is a flowchart before step S10 in fig. 1;
FIG. 3 is a schematic diagram of an embodiment of steps S11-S13 in FIG. 2;
FIG. 4 is a schematic diagram of an embodiment of steps S14-S17 in FIG. 2;
FIG. 5 is a schematic diagram illustrating a structure of step S16 in FIG. 2 according to another embodiment;
FIG. 6 is a schematic structural diagram of another embodiment corresponding to steps S11-S17 in FIG. 2;
FIG. 7 is a schematic diagram of a structure of another embodiment corresponding to steps S11-S17 in FIG. 2;
FIG. 8 is a schematic diagram of an embodiment of a semiconductor package structure according to the present application;
FIG. 9 is a schematic diagram of an embodiment of a semiconductor package structure according to the present application;
FIG. 10 is a schematic diagram of an embodiment of a semiconductor package structure according to the present application;
FIG. 11 is a schematic diagram of an embodiment of a semiconductor package structure according to the present application;
FIG. 12 is a schematic diagram of an embodiment of a semiconductor package structure according to the present application;
fig. 13 is a schematic structural view of an embodiment of a semiconductor package structure in the present application.
Reference numerals illustrate: 1 a lead frame; 11 pins; 12 carrying areas; a 13-base island; 2, a chip; 21 functional surfaces; 22 back side; 23 bonding pads; 24 insulating layers; 25 via holes; 3 a connecting part; 31 a connecting column; 4, a support pad; 5 packaging materials; 6 filling materials; 7, a second heat conduction structure; 8 a heat dissipation structure; 81 heat sinks; 9 a first thermally conductive structure; 92 a thermally conductive metal; 93 gold plating; 94 metallic indium flakes; 10 temporary carrier plate.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 1, the present application provides a method for manufacturing a semiconductor package structure, which includes:
the application provides a preparation method of a semiconductor packaging structure, which comprises the following steps:
s10: providing a lead frame 1 and a packaged chip 2, wherein the packaged chip 2 comprises a packaging structure and the chip 2, the packaging structure covers the area of the chip 2 except for a functional surface 21, and the functional surface 21 of the chip 2 is provided with a connecting part 3;
in the packaged chip 2 provided in this step, the package structure does not cover the functional surface 21 of the chip 2, but covers only the area of the chip 2 except for the functional surface 21 to protect the chip 2 from outside moisture.
S20: the chip 2 is mounted on the lead frame 1 with the functional surface 21 of the chip 2 facing the lead frame 1, and the lead frame 1 is connected to the pads 23 on the functional surface 21 of the chip 2 via the connection portions 3.
Specifically, the chip 2 is attached to the lead frame 1, the functional surface 21 of the chip 2 faces the lead frame 1, and at this time, the bonding pad 23 of the chip 2 is closer to the lead frame 1, and the two are connected through the connection portion 3, so that the resistance can be effectively reduced.
Referring to fig. 2 and 3, specifically, in step S10, the step of providing the packaged chip 2 includes:
s11: the temporary carrier 10 is provided, and the functional surface 21 of the chip 2 is bonded to the temporary carrier 10.
With continued reference to fig. 3, before the functional surface 21 of the chip 2 is attached to the temporary carrier 10, an insulating layer 24 may be prepared on the functional surface 21 of the chip 2 to protect the chip 2, and at the same time, a via hole 25 is disposed at a position of the insulating layer 24 corresponding to the bonding pad 23 of the chip 2, so as to facilitate electrical connection between the chip 2 and the outside. In one embodiment, the insulating layer 24 may be a photosensitive polyimide coating, which has the advantage of being easy to prepare. The functional surface 21 of the chip 2 is attached to the temporary carrier plate 10, and the temporary carrier plate 10 is used for facilitating the preparation of subsequent processes.
S12: a package structure is formed covering the back side 22 and the side faces of the chip 2.
The back surface 22 and the side surface of the chip 2 are covered by the packaging material 5, so that the preparation of the packaging structure is completed, and the packaging structure can effectively protect the exposed surface of one side of the chip 2 far away from the lead frame 1.
S13: the temporary carrier plate 10 is peeled off.
After the package structure is prepared, the temporary carrier plate 10 can be peeled off at this time because the chip 2 has the protection of the package structure.
S14: a metal paste column is formed in the region of the bonding pad 23 of the functional surface 21 of the chip 2.
Referring to fig. 2 and 4, the metal glue column is connected to the pad 23 area of the chip 2, so that the electrical signal in the chip 2 can be led out through the metal glue column. The metal glue column can be prepared by adopting a glue dispensing process, or adopting a die, wherein an opening is formed in the region of the die corresponding to the bonding pad 23, glue is coated in the opening corresponding to the bonding pad 23 by utilizing a scraper, and then the die is taken down, so that the preparation of the metal glue column is completed.
S15: the supporting pad 4 is formed on the packaged chip 2, and the height of the supporting pad 4 is smaller than that of the metal glue column, so that the supporting pad 4 supports the lead frame 1 during pressing.
With continued reference to fig. 4, the support pad 4 is prepared, and the support pad 4 and the metal glue column are prepared at intervals, and the heights of the support pad 4 and the metal glue column may be the same or different. In one embodiment, the height of the support pad 4 is less than the height of the metal glue string. The height of the supporting pad 4 may be kept constant during the subsequent process, so that the supporting pad 4 plays a role of keeping the distance between the chip 2 and the lead frame 1 during the subsequent lamination of the chip 2 and the lead frame 1.
S16: the lead frame 1 is pressed on the functional surface 21 of the chip 2, and the metal glue column is solidified to form the connecting part 3 for connecting the lead frame 1 and the chip 2 while heating is performed during the pressing.
With continued reference to fig. 4, in one embodiment, the curing temperature of the support pad 4 and the first heat conductive structure 9 is lower than the curing temperature of the metal glue string. The first heating can be performed during pressing, the curing of the supporting pad 4 and the first heat conducting structure 9 is completed, after a certain time of heating, the second heating is performed, the temperature of the second heating is higher than that of the first heating, the height of the metal adhesive column can be changed after the heating, and after the heating is completed, the lead frame 1 and the chip 2 are fixed together through the metal adhesive column, so that an integral structure is formed.
In an embodiment, the metal glue column is cured to obtain the connection portion 3, and the connection portion 3 includes at least two connection columns 31, wherein the connection columns 31 are located in two side areas of the opposite side of the chip 2 to the lead frame 1, and serve to connect the chip 2 and the lead frame 1. In the process of heating the metal glue column to obtain the connecting part 3, the heating temperature is 100-200 ℃; the fixed connection between the chip 2 and the lead frame 1 is achieved by a heating temperature of 100-200 deg.c.
In one embodiment, the metal glue pillars comprise nano copper glue pillars and the connection portion 3 comprises copper pillars. Meanwhile, the lead frame 1 can be made of copper, the connecting part 3 and the lead frame 1 are made of copper, so that the resistance of signal transmission in the semiconductor packaging structure can be reduced, loss is reduced, and the semiconductor packaging structure in the application can be suitable for high-power devices. In addition, the copper column can be prepared by sintering nano copper particle glue at low temperature, and the nano copper glue is sintered to form a pure copper material which is combined with the lead frame 1 of the copper material, so that the high-power device performance is improved.
S17: the gap of the lead frame 1, the gap between the functional surface 21 of the chip 2 and the lead frame 1, and the gap between the package structure and the lead frame 1 are filled with the filling material 6.
With continued reference to fig. 4, the gaps of the lead frame 1, the gaps between the functional surfaces 21 of the chips 2 and the lead frame 1, and the gaps between the package structure and the lead frame 1 are effectively filled by utilizing the advantage of the high flowability of the filling material 6. The filler material 6 is distributed in the gaps of the lead frame 1, the gaps between the functional surface 21 of the chip 2 and the lead frame 1, and the gaps between the package structure and the lead frame 1, so that the structural stability of the lead frame 1 is maintained, and the electrical connection between the lead frame 1 and the chip 2 is ensured.
In this embodiment, the lead frame has no islands; in other embodiments, the lead frame may further have a base island, and when the base island is provided, a heat conducting structure may be formed between the base island and the chip, so as to dissipate heat from the chip by using the base island.
Specifically, referring to fig. 5, before the chip is attached to the lead frame, a first heat conducting structure 9 is formed on the functional surface 21 of the chip 2, and the first heat conducting structure 9 is located between the two connection posts 31.
Referring to fig. 2 and 5, the first heat-conducting structure 9 is disposed on the functional surface 21 of the chip 2, and in an embodiment, the first heat-conducting structure 9 may be a heat-conducting glue. In an embodiment, the connection posts 31 are located at the sides of the chip 2, the first heat conductive structures 9 are located between the connection posts 31, and the first heat conductive structures 9 cover the central area of the chip 2, so that the contact area between the first heat conductive structures 9 and the chip 2 is larger.
In one embodiment, the lead frame 1 includes the island 13, and when the lead frame 1 includes the island 13, the step S20 includes:
s21: the islands 13 are connected to the first thermally conductive structure 9.
While step S20 is being performed, when the chip 2 is mounted on the lead frame 1, correspondingly, the base island 13 is correspondingly connected to the first heat conductive structure 9, and in an embodiment, the orthographic projection of the base island 13 on the chip 2 is greater than the orthographic projection of the first heat conductive structure 9 on the chip 2. The first heat conducting structure 9 can transfer heat generated in the operation process of the chip 2 to the base island 13, so as to increase a heat dissipation path of the semiconductor packaging structure in the application.
Further, referring to fig. 6 and 7, the heat dissipation structure 8 may be formed on the back surface 22 of the chip 2, and the package structure does not cover the heat dissipation structure 8. Specifically, step S11 further includes:
s111: a second heat conducting structure 7 is formed on the back side 22 of the chip 2.
On the back side 22 of the chip 2, the preparation of the second heat conducting structure 7 is performed, in an embodiment the second heat conducting structure 7 comprises a heat conducting glue and/or a heat conducting metal 92. The heat conducting glue and the heat conducting metal 92 can play a good role in heat conduction, so that the second heat conducting structure 7 can timely conduct out heat generated in the chip 2.
In one embodiment, the second heat conductive structure 7 includes a heat conductive metal 92, and the heat conductive metal 92 includes a gold plating layer 93 on the back surface 22 of the chip 2, and a metal indium sheet 94 connecting the gold plating layer 93 and the heat sink 81. In the preparation process, the gold-plating layer 93 may be prepared on the back surface 22 of the chip 2, then an indium sheet may be prepared on the surface of the gold-plating layer 93 on the side facing away from the chip 2, and finally the heat sink 81 may be prepared on the side of the indium sheet facing away from the gold-plating layer 93. The melting temperature of the indium sheet is low, and the gold-plated layer 93 and the radiating fin 81 are effectively connected under the low-temperature reflow process, so that the heat conduction effect of the second heat conduction structure 7 and the heat dissipation effect of the heat dissipation structure 8 are ensured.
S112: a heat-dissipating structure 8 is formed on the side of the second heat-conducting structure 7 facing away from the chip 2.
The preparation of the heat dissipation structure 8 is performed, the heat dissipation structure 8 being located at a side of the second heat conducting structure 7 facing away from the chip 2. After the preparation of the heat dissipation structure 8 is completed, the preparation of the packaging structure is performed, and the packaging structure does not cover one side surface of the heat dissipation structure 8, which faces away from the chip 2, so that the heat dissipation structure 8 can timely dissipate heat generated in the chip 2, and the heat dissipation efficiency of the semiconductor packaging structure is improved. After the preparation of the package structure, if the package structure covers a surface of the heat dissipation structure 8 facing away from the chip 2, a grinding process may be used to grind the package structure to expose a surface of the heat dissipation structure 8 facing away from the chip 2.
Referring to fig. 6 and 10, the heat dissipation structure 8 includes a heat dissipation plate 81, and the second heat conduction structure 7 includes a heat conduction glue, and the heat conduction glue connects the back surface 22 of the chip 2 and the heat dissipation plate 81. The heat sink 81 may be made of metal, specifically copper, aluminum, etc. with good heat dissipation performance.
Referring to fig. 7 and 12, the heat dissipation structure 8 includes a heat sink 81, the second heat conduction structure 7 includes a heat conduction metal 92, and the heat conduction metal 92 is located between the back surface 22 of the chip 2 and the heat sink 81; when the second heat conducting structure 7 is the heat conducting metal 92, the heat conducting efficiency is higher, and the heat generated in the working process of the chip 2 can be transferred to the heat radiating fin 81 in time.
When islands are included, the resulting structure is as shown in FIGS. 11 and 13.
Referring to fig. 8 to 13, the illustrated structure is a semiconductor package manufactured by the manufacturing method described above. When the lead frame 1 does not include the island 13, its structure is as shown in fig. 8, 10, 12; when the island 13 is included in the lead frame 1, the structure thereof is as shown in fig. 9, 11, and 13. As shown in fig. 10 to 13, the semiconductor package structure includes a heat dissipation structure 8 therein. Specifically, in fig. 10 and 11, the second heat conductive structure 7 is a heat conductive paste, and in fig. 12 and 13, the second heat conductive structure 7 is a heat conductive metal 92. The semiconductor package structure in the present application includes a lead frame 1, a chip 2, and a connection portion 3. The lead frame 1 is provided with a bearing area 12 and a pin 11, wherein the bearing area 12 is used for bearing the chip 2, and the pin 11 is used for connecting an external lead; the chip 2 is positioned in the bearing area 12 of the lead frame 1, the functional surface 21 of the chip 2 faces the lead frame 1, and the functional surface 21 of the chip 2 is provided with a bonding pad 23; the connection portion 3 is located in the carrying area 12, and has one end connected to the lead frame 1 and the other end connected to the pad 23.
Specifically, the lead frame 1 provides support for subsequent chip 2 attachment, and the lead frame 1 includes a carrier region 12 and leads 11, and in one embodiment, the carrier region 12 may provide support for the chip 2. The pins 11 lead out the electrical signals in the chip 2. During the preparation of the chip 2, the functional surface 21 of the chip 2 provided with the bonding pads 23 is directed towards the lead frame 1, so that the bonding pads 23 in the chip 2 are electrically connected to the lead frame 1 via the connection portions 3. An insulating layer 24 may be disposed on the functional surface 21 of the chip 2 to protect the chip 2, and an opening is disposed at a position of the insulating layer 24 corresponding to the bonding pad 23 of the chip 2, so that the connection post 31 passes through the insulating layer 24 and is connected with the bonding pad 23. Through design connecting portion 3 and chip 2 above the loading area 12 of lead frame 1, connecting portion 3 connects lead frame 1 and bonding pad 23 for high-power current can be transmitted between chip 2 and lead frame 1 through connecting portion 3, and makes this semiconductor packaging structure applicable to high-power device, has the advantage of high integration level, and the range of application is wide.
The foregoing description is only exemplary embodiments of the present application and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the present application.
Claims (10)
1. A method of fabricating a semiconductor package, comprising:
providing a lead frame and a packaged chip, wherein the packaged chip comprises a packaging structure and a chip, the packaging structure covers the area except for the functional surface of the chip, and the functional surface of the chip is provided with a connecting part;
and mounting the chip and the lead frame, wherein the functional surface of the chip faces the lead frame, and the lead frame is connected with the chip through the connecting part.
2. The method of manufacturing a semiconductor package according to claim 1, wherein,
the providing a packaged chip includes:
forming a metal glue column in a bonding pad area of a functional surface of the chip;
and solidifying the metal rubber column to obtain the connecting part.
3. The method of manufacturing a semiconductor package according to claim 2, wherein the curing the metal paste column to obtain the connection portion includes:
and pressing the lead frame on the functional surface of the chip, heating while pressing, and solidifying the metal glue column to form a connecting part for connecting the lead frame and the chip.
4. The method of manufacturing a semiconductor package according to claim 3, wherein the bonding the lead frame to the functional surface of the chip comprises:
and forming a supporting pad on the packaged chip, wherein the height of the supporting pad is smaller than that of the metal glue column, so that the supporting pad supports the lead frame during pressing.
5. The method of manufacturing a semiconductor package according to claim 2, wherein the curing the metal paste column to obtain the connection portion includes:
heating the metal rubber column to obtain the connecting part, wherein the heating temperature is 100-200 ℃;
optionally, the metal glue column comprises a nano copper glue column, and the connecting part comprises a copper column.
6. The method for manufacturing a semiconductor package according to any one of claims 1 to 5, wherein,
and filling gaps of the lead frames, gaps between the functional surfaces of the chips and the lead frames and gaps between the packaging structure and the lead frames with filling materials.
7. The method for manufacturing a semiconductor package according to any one of claims 1 to 5, wherein,
providing a packaged chip includes:
providing a temporary carrier plate, and attaching the functional surface of the chip to the temporary carrier plate;
forming a packaging structure, wherein the packaging structure covers the back surface and the side surface of the chip;
and stripping the temporary carrier plate.
8. The method of manufacturing a semiconductor package according to claim 7, wherein,
and forming a heat dissipation structure on the back surface of the chip, wherein the package structure does not cover the heat dissipation structure.
9. The method of manufacturing a semiconductor package according to claim 8, wherein,
forming a second heat conduction structure on the back of the chip;
and forming a heat dissipation structure on one side of the second heat conduction structure, which is away from the chip.
10. The method of manufacturing a semiconductor package according to claim 9, wherein,
the second heat conducting structure comprises heat conducting glue and/or heat conducting metal.
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