CN114895742A - Reference voltage source circuit - Google Patents
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- CN114895742A CN114895742A CN202210598542.8A CN202210598542A CN114895742A CN 114895742 A CN114895742 A CN 114895742A CN 202210598542 A CN202210598542 A CN 202210598542A CN 114895742 A CN114895742 A CN 114895742A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Abstract
The invention discloses a reference voltage source circuit, which comprises an operational amplification unit, a reference voltage generation unit and a starting unit, wherein the operational amplification unit is used for generating a reference voltage; all transistors in the operational amplification unit, the reference voltage generation unit and the starting unit adopt fully-depleted silicon-on-insulator transistors; the twelfth transistor and the thirteenth transistor in the start-up unit, and the tenth transistor and the eleventh transistor in the reference voltage generating unit each employ a counter-well PMOS device. By implementing the invention, the stability of the reference voltage source circuit can be improved, and the probability that the conventional ultralow-temperature reference voltage source circuit cannot be normally started in an ultralow-temperature environment is reduced.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a reference voltage source circuit.
Background
As a core module of an integrated circuit, a reference voltage source can provide a stable reference voltage which is not changed along with the change of power supply voltage, external temperature and transient load, is widely applied to various high-precision circuits and is a key unit of chips such as a high-precision digital-to-analog and analog-to-digital converter, a high-precision integrated operational amplifier, a high-precision voltage comparator, an on-chip system and the like.
In most applications, the working temperature range of a reference voltage source circuit is required to be-40-85 ℃, and the temperature range required to be met in military applications is-55-125 ℃. But in some applications it is desirable to be able to work in ultra-low temperature environments, such as electronics for space and planetary missions, where temperatures on the moon can range from-230 ℃ to +120 ℃; according to the traditional band-gap reference voltage source, a negative correlation relationship is presented between the voltage difference between the base electrode and the emitter electrode of the bipolar transistor and the temperature change, the emitter voltage difference delta VBE is in direct proportion to the absolute temperature when the two bipolar transistors work at different current densities, and the two voltages with opposite temperature coefficients are added in a proper proportion to obtain a reference voltage with a zero temperature coefficient. However, a great deal of research data shows that the operating temperature of the bipolar transistor manufactured by the standard process can only reach 77K (-196 ℃), because at a lower temperature, the current gain beta of the bipolar transistor can be obviously reduced, and the base resistance RB can be obviously increased.
In order to solve the problem, the existing realization mode of ultralow temperature reference voltage in a large-scale integrated circuit is to use a Dynamic Threshold MOS (DTMOS) or MOS transistor to replace a bipolar transistor, but both the two modes adopt bulk silicon CMOS process design, and a Kink effect appears in an MOS device under the ultralow temperature environment, so that the uncertainty of the circuit node voltage is increased by the Kink effect, the gain of a control circuit is reduced, and the stability margin of a feedback circuit is influenced; in addition, the threshold voltage VTH of the MOS device is significantly increased in an ultra-low temperature environment, which may cause the device to fail to be normally turned on.
Disclosure of Invention
The embodiment of the invention provides a reference voltage source circuit, which can improve the stability of the circuit and reduce the probability that the conventional ultralow-temperature reference voltage source circuit cannot be normally started in an ultralow-temperature environment.
An embodiment of the present invention provides a reference voltage source circuit, including: an operational amplification unit, a reference voltage generation unit and a start-up unit;
the operational amplification unit includes: the circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first resistor and a first capacitor;
the reference voltage generating unit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a second resistor, and a third resistor;
the starting unit includes: a twelfth transistor, a thirteenth transistor, and a second capacitor;
the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor are all fully depleted silicon-on-insulator transistors;
the tenth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor are inverse well PMOS devices, and the tenth transistor and the eleventh transistor work in a weak inversion region;
a source of the fifth transistor is connected to a power supply voltage, a drain of the fifth transistor is connected to a source of the first transistor and a source of the second transistor, and a gate of the fifth transistor is connected to a gate of the seventh transistor;
a gate of the first transistor is connected to a drain of the eighth transistor and a source of the tenth transistor, and a drain of the first transistor is connected to a drain and a gate of the third transistor;
the drain of the second transistor is connected with the drain of the fourth transistor, and the gate of the second transistor is connected with the second end of the second resistor and the first end of the third resistor;
the source electrode of the third transistor is grounded, and the grid electrode of the third transistor is also connected with the grid electrode of the fourth transistor;
the drain electrode of the fourth transistor is also connected with the grid electrode of the sixth transistor, and the source electrode of the fourth transistor is grounded;
the grid electrode of the sixth transistor is also connected with the first end of the first capacitor, the drain electrode of the sixth transistor is connected with the second end of the first resistor, and the source electrode of the sixth transistor is grounded; the second end of the first capacitor is grounded, and the first end of the first resistor is connected with the drain electrode of the seventh transistor;
the grid electrode of the seventh transistor is also connected with the grid electrode of the twelfth transistor, and the source electrode of the seventh transistor is connected with the power supply voltage;
a gate of the eighth transistor is connected to a gate of the seventh transistor, and a source of the eighth transistor is connected to the power supply voltage;
a gate of the ninth transistor is connected to a gate of the seventh transistor, a drain of the ninth transistor is connected to a first end of the second resistor, and a source of the ninth transistor is connected to the power supply voltage; the drain electrode of the ninth transistor is a reference voltage output end;
the grid electrode and the drain electrode of the tenth transistor are grounded; the grid electrode and the drain electrode of the eleventh transistor are grounded, and the source electrode of the eleventh transistor is connected with the second end of the third resistor;
the source of the twelfth transistor is connected with the power supply voltage, the gate of the twelfth transistor is also connected with the source of the thirteenth transistor, and the drain of the twelfth transistor is connected with the first end of the second capacitor; the second end of the second capacitor is grounded;
a drain of the thirteenth transistor is grounded, and a gate of the thirteenth transistor is connected to a drain of the twelfth transistor;
the gate voltage of the first transistor is equal to the gate voltage of the second transistor.
Further, the first transistor, the second transistor, the fifth transistor, the seventh transistor, the eighth transistor and the ninth transistor are conventional well PMOS devices; the third transistor, the fourth transistor and the sixth transistor are conventional well NMOS devices.
Further, the method also comprises the following steps: a second starting unit; the second starting unit includes: a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twentieth transistor, a twenty-third transistor, and a twenty-fourth transistor;
a source of the fourteenth transistor is connected to the power supply voltage, a gate of the fourteenth transistor is connected to a gate of the fifteenth transistor, and a drain of the fourteenth transistor is connected to a source of the fifteenth transistor;
the grid electrode of the fifteenth transistor is also connected with the grid electrode of the sixteenth transistor, and the drain electrode of the fifteenth transistor is connected with the source electrode of the sixteenth transistor;
the grid electrode of the sixteenth transistor is also connected with the grid electrode of the seventeenth transistor, and the drain electrode of the sixteenth transistor is connected with the source electrode of the seventeenth transistor;
a drain of the seventeenth transistor is connected to a drain of the eighteenth transistor and a gate of the eighteenth transistor;
the source electrode of the eighteenth transistor is grounded, and the grid electrode of the eighteenth transistor is also connected with the grid electrode of the nineteenth transistor;
a source of the nineteenth transistor is grounded, and a drain of the nineteenth transistor is connected to a drain of the twentieth transistor and a gate of the twentieth transistor;
the source of the twentieth transistor is connected to the supply voltage, and the gate of the twentieth transistor is also connected to the gate of the twenty-first transistor;
a source of the twenty-first transistor is connected to the power supply voltage, and a drain of the twenty-first transistor is connected to a source of the twenty-second transistor;
a gate of the twenty-second transistor is connected to a gate of the twenty-third transistor, and a drain of the twenty-second transistor is connected to a drain of the twenty-third transistor and a gate of the twenty-fourth transistor;
the grid electrode of the twenty-third transistor is also connected with the reference voltage output end, and the source electrode of the twenty-third transistor is grounded;
the drain of the twenty-fourth transistor is connected to the supply voltage, and the source of the twenty-fourth transistor is connected to the first end of the first capacitor.
Further, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, and the twenty-fourth transistor are all fully depleted silicon-on-insulator transistors.
Further, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the twentieth transistor, the twenty-first transistor and the twentieth transistor are all conventional well PMOS devices; the eighteenth, nineteenth, twenty-third and twenty-fourth transistors are conventional well NMOS devices.
The embodiment of the invention has the following beneficial effects:
the reference voltage source circuit disclosed by the embodiment of the invention comprises an operational amplification unit, a reference voltage generation unit and a starting unit; all transistors in the operational amplification unit, the reference voltage generation unit and the starting unit adopt fully-depleted silicon-on-insulator transistors; compared with the existing bulk silicon MOS device, the silicon MOS device has negligible drain-source substrate capacitance, no latch-up effect and ideal device isolation, thereby improving the stability of the circuit; in addition, the substrate voltage of the fully depleted silicon-on-insulator transistor can be flexibly set, so the threshold voltage of the device can be flexibly adjusted by utilizing the back gate bias voltage, based on the characteristic, the twelfth transistor and the thirteenth transistor in the starting unit of the invention adopt reverse-well PMOS devices, have very low starting threshold voltage, so that the circuit can still be started in an extremely low temperature environment, meanwhile, the tenth transistor and the eleventh transistor in the reference voltage generating unit also adopt reverse-well PMOS devices, have very low starting threshold voltage, and can still normally work in the extremely low temperature environment, thereby reducing the probability that the existing ultra-low temperature reference voltage source circuit cannot be normally started in the ultra-low temperature environment.
Drawings
Fig. 1 is a schematic circuit diagram of a reference voltage source circuit according to an embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of a reference voltage source circuit according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a reference voltage source circuit, which includes an operational amplifier unit 1, a reference voltage generator unit 2, and a start unit 3;
the operational amplification unit 1 includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a first resistor R1 and a first capacitor C1;
the reference voltage generating unit 2 includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a second resistor R2, and a third resistor R3;
the starting unit 3 includes: a twelfth transistor MS12, a thirteenth transistor MS13, and a second capacitor C2;
the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor MS12 and the thirteenth transistor MS13 are all fully depleted silicon-on-insulator transistors;
the tenth transistor M10, the eleventh transistor M11, the twelfth transistor MS12 and the thirteenth transistor MS13 are reverse-well PMOS devices, and the tenth transistor M10 and the eleventh transistor M11 operate in a weak inversion region;
a source of the fifth transistor M5 is connected to a power supply voltage VDD, a drain of the fifth transistor M5 is connected to a source of the first transistor M1 and a source of the second transistor M2, and a gate of the fifth transistor M5 is connected to a gate of the seventh transistor M7;
a gate of the first transistor M1 is connected to a drain of the eighth transistor M8 and a source of the tenth transistor M10, and a drain of the first transistor M1 is connected to a drain and a gate of the third transistor M3;
the drain of the second transistor M2 is connected to the drain of the fourth transistor M4, and the gate of the second transistor M2 is connected to the second end of the second resistor R2 and the first end of the third resistor R3;
the source of the third transistor M3 is grounded, and the gate of the third transistor M3 is also connected to the gate of the fourth transistor M4;
the drain of the fourth transistor M4 is also connected with the gate of the sixth transistor M6, and the source of the fourth transistor M4 is grounded;
the gate of the sixth transistor M6 is further connected to the first end of the first capacitor C1, the drain of the sixth transistor M6 is connected to the second end of the first resistor R1, and the source of the sixth transistor M6 is grounded; the second end of the first capacitor C1 is grounded, and the first end of the first resistor R1 is connected with the drain electrode of the seventh transistor M7;
the gate of the seventh transistor M7 is also connected with the gate of the twelfth transistor MS12, and the source of the seventh transistor M7 is connected with the power supply voltage VDD;
the gate of the eighth transistor M8 is connected with the gate of the seventh transistor M7, and the source of the eighth transistor M8 is connected with the power supply voltage VDD;
a gate of the ninth transistor M9 is connected to a gate of the seventh transistor M7, a drain of the ninth transistor M9 is connected to a first end of the second resistor R2, and a source of the ninth transistor M9 is connected to the power supply voltage VDD; the drain of the ninth transistor M9 is a reference voltage output terminal;
the gate and the drain of the tenth transistor M10 are grounded; the gate and the drain of the eleventh transistor M11 are grounded, and the source of the eleventh transistor M11 is connected to the second end of the third resistor R3;
a source of the twelfth transistor MS12 is connected to the power supply voltage VDD, a gate of the twelfth transistor MS12 is further connected to a source of the thirteenth transistor MS13, and a drain of the twelfth transistor MS12 is connected to the first end of the second capacitor C2; a second end of the second capacitor C2 is grounded;
the drain of the thirteenth transistor MS13 is grounded, and the gate of the thirteenth transistor MS13 is connected with the drain of the twelfth transistor MS 12;
the gate voltage of the first transistor M1 is equal to the gate voltage of the second transistor M2.
Preferably, the first transistor M1, the second transistor M2, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 are conventional well PMOS devices; the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are conventional well NMOS devices.
The various units in the circuit are further described below:
firstly, the reference voltage generating unit 2 is provided, wherein the tenth transistor M10 and the eleventh transistor M11 in the reference voltage generating unit 2 are anti-well PMOS devices, and the tenth transistor M10 and the eleventh transistor M11 operate in a weak inversion region (the other transistors of the present invention operate in a saturation region by default without specific description); the inverted trap structure is that the source-drain doping and the trap doping of the device are the same in type. The substrates of the tenth transistor M10 and the eleventh transistor M11 are connected to zero, which can effectively lower the threshold voltages of the two tubes of the tenth transistor M10 and the eleventh transistor M11, so that the two tubes are still in an on state in an ultra-low temperature environment. The eighth transistor M8 and the ninth transistor M9 are PMOS devices using a conventional well, i.e., a fully depleted silicon-on-insulator (FDSOI) transistor with source-drain doping of the opposite type to the well doping, and the substrates of the eighth transistor M8 and the ninth transistor M9 are connected to VDD potential.
Specifically, the drain-source currents of both the tenth transistor M10 and the eleventh transistor M11 may be respectively expressed as:
wherein, I ds10 For the drain-source current of the tenth transistor M10, exp () is an exponential function, I ds11 Is the drain-source current of the eleventh transistor M11, μ is the carrier mobility, C ox Is a gate oxide capacitance per unit area,
and
width to length ratios of the tenth transistor M10 and the eleventh transistor M11, respectively, n is a non-ideality factor, V T It is shown that the thermal voltage is,
where k is Boltzmann's constant, T is absolute temperature, q is electronic electric quantity, and V gs10 And V gs11 Gate-source voltages of the tenth transistor M10 and the eleventh transistor M11 respectively,V th10 and V th11 The threshold voltages of the tenth transistor M10 and the eleventh transistor, respectively.
The eighth transistor M8 and the ninth transistor M9 form a current mirror, and the width-to-length ratio of the eighth transistor M8 and the ninth transistor M9 determines I ds10 And I ds11 If the width-to-length ratio of the eighth transistor M8 and the ninth transistor M9 is p:1,
V th10 ＝V th11 then the formula (1) and the formula (2) are compared to obtain
From equation (3), since the gate voltage of the first transistor M1 is equal to the gate voltage of the second transistor M2, i.e. the voltages at points a and B are equal in the figure, it can be obtained that:
V R3 ＝V gs10 -V gs11 ＝nV T ln(p) (4)
V R3 is the voltage across the third resistor R3;
the reference voltage V thus generated REF Can be expressed as:
since the eleventh transistor M11 is in a weak inversion state, its gate-source voltage V gs11 Is a voltage with a negative temperature coefficient, so that by reasonably setting the P value and the resistance ratio of R2 to R3, the reference voltage generating unit 2 can generate a reference voltage VREF with an approximately zero temperature coefficient, and illustratively, when P is 5 and R2: R3 is 1:10, the reference voltage VREF with the approximately zero temperature coefficient can be generatedVREF。
For the operational amplification unit 1, which is a self-biased operational amplifier, no additional bias circuit is needed to provide working current, and the function of the operational amplification unit is to ensure that the potentials of the point a and the point B in the circuit of the reference voltage generation unit 2 are equal.
For the start-up unit 3, the twelfth transistor MS12 and the thirteenth transistor MS13 are anti-well PMOS devices, having a very low start-up threshold voltage. In an extremely low temperature environment, the thirteenth transistor MS13 can still be normally turned on, and when the thirteenth transistor MS13 is turned on, the potential at the point C in the figure is pulled low, so that the fifth transistor M5, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 are turned on to supply an operating current. Thus, the reference voltage generating unit 2 enters a normal operating state and outputs a reference voltage independent of temperature.
As shown in fig. 2, in another embodiment of the present invention, the reference voltage source circuit further includes: a second starting unit 4; the second activation unit 4 includes: a fourteenth transistor MS1, a fifteenth transistor MS2, a sixteenth transistor MS3, a seventeenth transistor MS4, an eighteenth transistor MS5, a nineteenth transistor MS6, a twentieth transistor MS7, a twenty-first transistor MS8, a twentieth transistor MS9, a twenty-third transistor MS10, and a twenty-fourth transistor MS 11;
a source of the fourteenth transistor MS1 is connected to the power supply voltage VDD, a gate of the fourteenth transistor MS1 is connected to the gate of the fifteenth transistor MS2, and a drain of the fourteenth transistor MS1 is connected to the source of the fifteenth transistor MS 2;
the gate of the fifteenth transistor MS2 is further connected with the gate of the sixteenth transistor MS3, and the drain of the fifteenth transistor MS2 is connected with the source of the sixteenth transistor MS 3;
the gate of the sixteenth transistor MS3 is further connected with the gate of a seventeenth transistor MS4, and the drain of the sixteenth transistor MS3 is connected with the source of the seventeenth transistor MS 4;
a drain of the seventeenth transistor MS4 is connected to a drain of the eighteenth transistor MS5 and a gate of the eighteenth transistor MS 5;
the source of the eighteenth transistor MS5 is grounded, and the gate of the eighteenth transistor MS5 is also connected with the gate of the nineteenth transistor MS 6;
the source of the nineteenth transistor MS6 is grounded, and the drain of the nineteenth transistor MS6 is connected to the drain of the twentieth transistor MS7 and the gate of the twentieth transistor MS 7;
the source of the twentieth transistor MS7 is connected to the power supply voltage VDD, and the gate of the twentieth transistor MS7 is further connected to the gate of the twenty-first transistor MS 8;
a source of the twenty-first transistor MS8 is connected to the supply voltage VDD, and a drain of the twenty-first transistor MS8 is connected to a source of the twenty-second transistor MS 9;
a gate of the twentieth transistor MS9 is connected to a gate of the twenty-third transistor MS10, and a drain of the twentieth transistor MS9 is connected to a drain of the twenty-third transistor MS10 and a gate of the twenty-fourth transistor MS 11;
the gate of the twenty-third transistor MS10 is further connected to the reference voltage output terminal, and the source of the twenty-third transistor MS10 is grounded;
the drain of the twenty-fourth transistor MS11 is connected to the supply voltage VDD, and the source of the twenty-fourth transistor MS11 is connected to the first end of the first capacitor C1.
In a preferred embodiment, the fourteenth transistor MS1, the fifteenth transistor MS2, the sixteenth transistor MS3, the seventeenth transistor MS4, the eighteenth transistor MS5, the nineteenth transistor MS6, the twentieth transistor MS7, the twenty-first transistor MS8, the twentieth transistor MS9, the twenty-third transistor MS10 and the twenty-fourth transistor MS11 are all fully depleted silicon-on-insulator transistors.
In a preferred embodiment, the fourteenth transistor MS1, the fifteenth transistor MS2, the sixteenth transistor MS3, the seventeenth transistor MS4, the twentieth transistor MS7, the twenty-first transistor MS8 and the twentieth transistor MS9 are all conventional well PMOS devices; the eighteenth transistor MS5, the nineteenth transistor MS6, the twenty-third transistor MS10, and the twenty-fourth transistor MS11 are all conventional well NMOS devices.
By providing the second starting means 4 as a backup starting circuit, the starting function of the circuit can be maintained in the event of a failure of the above-mentioned starting means 3. When the second start unit 4 is operated, a start current is injected into the upper plate of the first capacitor C1, so that the sixth transistor M6 is turned on, and further the fifth transistor M5, the seventh transistor M7, the eighth transistor M8 and the ninth transistor M9 are turned on, thereby providing an operating current. Thus, the reference voltage generating unit 2 enters a normal operating state and outputs a reference voltage independent of temperature.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (5)
1. A reference voltage source circuit, comprising: an operational amplification unit, a reference voltage generation unit and a start-up unit;
the operational amplification unit includes: the circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first resistor and a first capacitor;
the reference voltage generating unit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a second resistor, and a third resistor;
the starting unit includes: a twelfth transistor, a thirteenth transistor, and a second capacitor;
the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor are all fully depleted silicon-on-insulator transistors;
the tenth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor are inverse well PMOS devices, and the tenth transistor and the eleventh transistor work in a weak inversion region;
a source of the fifth transistor is connected to a power supply voltage, a drain of the fifth transistor is connected to the source of the first transistor and the source of the second transistor, and a gate of the fifth transistor is connected to a gate of the seventh transistor;
a gate of the first transistor is connected to a drain of the eighth transistor and a source of the tenth transistor, and a drain of the first transistor is connected to a drain and a gate of the third transistor;
the drain of the second transistor is connected with the drain of the fourth transistor, and the gate of the second transistor is connected with the second end of the second resistor and the first end of the third resistor;
the source electrode of the third transistor is grounded, and the grid electrode of the third transistor is also connected with the grid electrode of the fourth transistor;
the drain electrode of the fourth transistor is also connected with the grid electrode of the sixth transistor, and the source electrode of the fourth transistor is grounded;
the grid electrode of the sixth transistor is also connected with the first end of the first capacitor, the drain electrode of the sixth transistor is connected with the second end of the first resistor, and the source electrode of the sixth transistor is grounded; the second end of the first capacitor is grounded, and the first end of the first resistor is connected with the drain electrode of the seventh transistor;
the grid electrode of the seventh transistor is also connected with the grid electrode of the twelfth transistor, and the source electrode of the seventh transistor is connected with the power supply voltage;
a gate of the eighth transistor is connected to a gate of the seventh transistor, and a source of the eighth transistor is connected to the power supply voltage;
a gate of the ninth transistor is connected to a gate of the seventh transistor, a drain of the ninth transistor is connected to a first end of the second resistor, and a source of the ninth transistor is connected to the power supply voltage; the drain electrode of the ninth transistor is a reference voltage output end;
the grid electrode and the drain electrode of the tenth transistor are grounded; the grid electrode and the drain electrode of the eleventh transistor are grounded, and the source electrode of the eleventh transistor is connected with the second end of the third resistor;
the source of the twelfth transistor is connected with the power supply voltage, the gate of the twelfth transistor is also connected with the source of the thirteenth transistor, and the drain of the twelfth transistor is connected with the first end of the second capacitor; the second end of the second capacitor is grounded;
a drain of the thirteenth transistor is grounded, and a gate of the thirteenth transistor is connected to a drain of the twelfth transistor;
the gate voltage of the first transistor is equal to the gate voltage of the second transistor.
2. The reference voltage source circuit according to claim 1, wherein the first transistor, the second transistor, the fifth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are normal well PMOS devices; the third transistor, the fourth transistor and the sixth transistor are conventional well NMOS devices.
3. The reference voltage source circuit according to claim 1, further comprising: a second starting unit; the second starting unit includes: a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twentieth transistor, a twenty-third transistor, and a twenty-fourth transistor;
a source of the fourteenth transistor is connected to the power supply voltage, a gate of the fourteenth transistor is connected to a gate of the fifteenth transistor, and a drain of the fourteenth transistor is connected to a source of the fifteenth transistor;
the grid electrode of the fifteenth transistor is also connected with the grid electrode of the sixteenth transistor, and the drain electrode of the fifteenth transistor is connected with the source electrode of the sixteenth transistor;
the grid electrode of the sixteenth transistor is also connected with the grid electrode of the seventeenth transistor, and the drain electrode of the sixteenth transistor is connected with the source electrode of the seventeenth transistor;
a drain of the seventeenth transistor is connected to a drain of the eighteenth transistor and a gate of the eighteenth transistor;
the source electrode of the eighteenth transistor is grounded, and the grid electrode of the eighteenth transistor is also connected with the grid electrode of the nineteenth transistor;
a source of the nineteenth transistor is grounded, and a drain of the nineteenth transistor is connected to a drain of the twentieth transistor and a gate of the twentieth transistor;
the source of the twentieth transistor is connected to the supply voltage, and the gate of the twentieth transistor is also connected to the gate of the twenty-first transistor;
a source of the twenty-first transistor is connected to the power supply voltage, and a drain of the twenty-first transistor is connected to a source of the twenty-second transistor;
a gate of the twenty-second transistor is connected to a gate of the twenty-third transistor, and a drain of the twenty-second transistor is connected to a drain of the twenty-third transistor and a gate of the twenty-fourth transistor;
the grid electrode of the twenty-third transistor is also connected with the reference voltage output end, and the source electrode of the twenty-third transistor is grounded;
the drain of the twenty-fourth transistor is connected to the supply voltage, and the source of the twenty-fourth transistor is connected to the first end of the first capacitor.
4. The reference voltage source circuit according to claim 3, wherein the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, the twenty-first transistor, the twenty-second transistor, the twenty-third transistor, and the twenty-fourth transistor are all fully depleted silicon-on-insulator transistors.
5. The reference voltage source circuit of claim 3, wherein the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the twentieth transistor, the twenty-first transistor, and the twenty-second transistor are all conventional well PMOS devices; the eighteenth, nineteenth, twenty-third and twenty-fourth transistors are conventional well NMOS devices.
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| US20160334826A1 (en) * | 2015-05-15 | 2016-11-17 | Postech Academy-Industry Foundation | Low-power bandgap reference voltage generator using leakage current |
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| US6760209B1 (en) * | 2002-05-16 | 2004-07-06 | Lattice Semiconductor Corporation | Electrostatic discharge protection circuit |
| US20040036460A1 (en) * | 2002-07-09 | 2004-02-26 | Atmel Nantes S.A. | Reference voltage source, temperature sensor, temperature threshold detector, chip and corresponding system |
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| US20130099770A1 (en) * | 2010-12-15 | 2013-04-25 | Liang Cheng | Reference power supply circuit |
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