CN114884489A - Wide power supply voltage range input level detection circuit - Google Patents
Wide power supply voltage range input level detection circuit Download PDFInfo
- Publication number
- CN114884489A CN114884489A CN202210523549.3A CN202210523549A CN114884489A CN 114884489 A CN114884489 A CN 114884489A CN 202210523549 A CN202210523549 A CN 202210523549A CN 114884489 A CN114884489 A CN 114884489A
- Authority
- CN
- China
- Prior art keywords
- power supply
- tube
- pmos
- supply voltage
- detection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a wide power supply voltage range input level detection circuit which comprises an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, a PMOS tube P0, a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a resistor R1 and a resistor R2. The wide power supply voltage range input level detection circuit regulates the opening currents of N2 and P0 through the N1 tube, and therefore level identification and inversion of an output end are achieved. The circuit can expand the range of the VDD power supply voltage, so that the VDD power supply voltage meets the requirement of lower power supply voltage, and the digital input turning point of the invention is
The gate capacitance charge-discharge balance of the PMOS tube P3 and the NMOS tube N3 at the rear stage is adjusted by adding the resistor R1 and the resistor R2, so that the pulse width duty cycle transmission stability of the final circuit output waveform is realized.
Description
Technical Field
The invention belongs to the field of integrated circuit devices and digital signal transmission, and particularly relates to a wide power supply voltage range input level detection circuit.
Background
With the high-speed development of integrated circuits, digital signal transmission is becoming more and more common in systems, and the transmission of digital signals involves the problem of identification of digital signals, and the conventional level input detection circuit usually uses the inverter structure of fig. 2. The digital level input signal IN generally needs to meet the identification criteria, VDD being the chip supply voltage, generally the input voltage is lower than 0.35 VDD and identified as low, and higher than 0.65 VDD and identified as high. In some current applications, the voltage range of VDD needs to be expanded; when the VDD is small, the high and low levels defined by the above specifications have the problem that the input high and low levels are difficult to identify if the traditional inverter connection method is adopted, the main reason is that the threshold voltages of an N1 NMOS transistor and a P1 PMOS transistor limit the minimum value that the VDD can reach, and the wide range of the VDD can be expanded by adopting the low-threshold NMOS transistor commonly provided by a process factory, but the threshold voltage difference between the low-threshold NMOS transistor and the PMOS transistor is too large, so that the turning point is not close to 0.5 times of the power supply voltage, and the duty ratio of the square wave input signal changes obviously.
Disclosure of Invention
In view of the above disadvantages in the prior art, the input level detection circuit with a wide power supply voltage range provided by the present invention solves the problem that the VDD voltage range of the conventional level input detection circuit is too narrow.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a wide power supply voltage range input level detection circuit comprises an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, a PMOS transistor P0, a PMOS transistor P1, a PMOS transistor P2, a PMOS transistor P3, a resistor R1 and a resistor R2;
the grid electrode of the PMOS tube P0 is connected with the grid electrode of the NMOS tube N2 and is used as the input end of the wide power supply voltage range input level detection circuit, the drain electrode of the PMOS tube P0 is grounded, and the source electrode of the PMOS tube P0 is connected with the source electrode of the NMOS tube N1;
the grid electrode of the NMOS tube N1 is connected with a VDD power supply, the substrate of the NMOS tube N1 is grounded, the drain electrode of the NMOS tube N1 is respectively connected with one end of the resistor R1 and the grid electrode of the PMOS tube P2, the other end of the resistor R1 is connected with the drain electrode of the PMOS tube P1, the source electrode of the PMOS tube P1 is connected with the VDD power supply, and the grid electrode of the PMOS tube P1 is respectively connected with one end of the resistor R2, the drain electrode of the NMOS tube N2 and the grid electrode of the NMOS tube N3;
the source electrode of the NMOS tube N2 is grounded, the other end of the resistor R2 is connected with the drain electrode of the PMOS tube P2 and the grid electrode of the PMOS tube P3 respectively, the source electrode of the PMOS tube P2 is connected with the VDD power supply, the source electrode of the PMOS tube P3 is connected with the VDD power supply, the drain electrode of the PMOS tube P3 is connected with the drain electrode of the NMOS tube N3 and serves as the output end of the wide power supply voltage range input level detection circuit, and the source electrode of the NMOS tube N3 is grounded.
Further: the NMOS transistor N1 is a low-threshold NMOS transistor, and the threshold voltage of the low-threshold NMOS transistor is 0.2V.
Further: the PMOS tube P1, the PMOS tube P2, the resistor R1 and the resistor R2 form a positive feedback loop.
Further: when the input signal of the input end of the wide power voltage range input level detection circuit is changed from the low level of logic 0 to the high level of logic 1, the PMOS tube P0 is closed, the NMOS tube N2 is opened, and the positive feedback loop is conducted and pulls down the gate voltage of the NMOS tube N3 and the gate voltage of the PMOS tube P3 to the low level of logic 0.
Further: when the input signal of the input end of the wide power voltage range input level detection circuit is changed from the high level of logic 1 to the low level of logic 0, the PMOS tube P0 is turned on, the NMOS tube N2 is turned off, and the positive feedback loop is turned on and pulls the gate voltage of the NMOS tube N3 and the gate voltage of the PMOS tube P3 to the high level of logic 1.
The beneficial effects of the above further scheme are: the charging speed of the gates of the NMOS transistor N3 and the PMOS transistor P3 can be controlled by adjusting the resistance values of the resistor R1 and the resistor R2, and the charging and discharging balance is realized.
Further: taking the grid voltage of the PMOS tube P3 as an X-point voltage Vx, and taking the grid voltage of the NMOS tube N3 as a Y-point voltage Vy;
when the VDD power supply voltage is low voltage 1V, and the wide power supply voltage range is input to the input end of the level detection circuitWhen the input signal of the NMOS tube N1 is changed from the low level of logic 0 to the high level of logic 1, the channel of a PMOS tube P1-a resistor R1-an NMOS tube N1-a PMOS tube P0 is closed by the NMOS tube N1, the NMOS tube N2 is opened, and the voltage Vx at the X point and the voltage Vy at the Y point are pulled down to the high level of the PMOS tube P1-a resistor R1-a PMOS tube N1-a PMOS tube P0
And the output end of the wide power supply voltage range input level detection circuit outputs a high level of logic 1.
Further: taking the grid voltage of the PMOS pipe P2 as a Z-point voltage Vz;
when the VDD power voltage is a low voltage of 1V, and the input signal at the input terminal of the wide power voltage range input level detection circuit is changed from a high level of logic 1 to a low level of logic 0, and when the voltage VIN of the input signal satisfies the following formula, the path of the PMOS transistor P1-the resistor R1-the NMOS transistor N1-the PMOS transistor P0 is opened, and the Z-point voltage Vz is pulled down to a low voltage of 1V
The power supply voltage is that the PMOS tube P3 is switched on, the NMOS tube N2 is switched off, and the voltage Vx at the X point and the voltage Vy at the Y point are pulled high
A power supply voltage, the output end of the wide power supply voltage range input level detection circuit outputs a low level of logic 0;
VDD-VIN＝VTHP+0.2V
wherein, VTHP is the threshold voltage of PMOS pipe P0.
The invention has the beneficial effects that: the wide power supply voltage range input level detection circuit regulates the opening currents of N2 and P0 through the N1 tube, and therefore level identification and inversion of an output end are achieved. And the circuit can expand the range of the VDD power supply voltage, so that the VDD power supply voltage meets the requirement of lower power supply voltage.
The digital input turning point of the invention is
The gate capacitance charge-discharge balance of the PMOS tube P3 and the NMOS tube N3 at the rear stage is adjusted by adding the resistor R1 and the resistor R2, so that the pulse width duty cycle transmission stability of the final circuit output waveform is realized.
Drawings
FIG. 1 is a schematic circuit diagram of the present invention;
fig. 2 shows a conventional inverter structure.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined by the appended claims, and all changes that can be made by the invention using the inventive concept are intended to be protected.
Example 1:
as shown in fig. 1, in an embodiment of the present invention, a wide power voltage range input level detection circuit includes an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, a PMOS transistor P0, a PMOS transistor P1, a PMOS transistor P2, a PMOS transistor P3, a resistor R1, and a resistor R2;
the grid electrode of the PMOS tube P0 is connected with the grid electrode of the NMOS tube N2 and is used as the input end of the wide power supply voltage range input level detection circuit, the drain electrode of the PMOS tube P0 is grounded, and the source electrode of the PMOS tube P0 is connected with the source electrode of the NMOS tube N1;
the grid electrode of the NMOS tube N1 is connected with a VDD power supply, the substrate of the NMOS tube N1 is grounded, the drain electrode of the NMOS tube N1 is respectively connected with one end of the resistor R1 and the grid electrode of the PMOS tube P2, the other end of the resistor R1 is connected with the drain electrode of the PMOS tube P1, the source electrode of the PMOS tube P1 is connected with the VDD power supply, and the grid electrode of the PMOS tube P1 is respectively connected with one end of the resistor R2, the drain electrode of the NMOS tube N2 and the grid electrode of the NMOS tube N3;
the source electrode of the NMOS tube N2 is grounded, the other end of the resistor R2 is connected with the drain electrode of the PMOS tube P2 and the grid electrode of the PMOS tube P3 respectively, the source electrode of the PMOS tube P2 is connected with the VDD power supply, the source electrode of the PMOS tube P3 is connected with the VDD power supply, the drain electrode of the PMOS tube P3 is connected with the drain electrode of the NMOS tube N3 and serves as the output end of the wide power supply voltage range input level detection circuit, and the source electrode of the NMOS tube N3 is grounded.
In this embodiment, the NMOS transistor N1 is a low-threshold NMOS transistor, the threshold voltage of the NMOS transistor is 0.2V, and the PMOS transistor P1, the PMOS transistor P2, the resistor R1, and the resistor R2 form a positive feedback loop.
The on-currents of the NMOS transistor N2 and the PMOS transistor P0 are adjusted through the NMOS transistor N1, and therefore level identification overturning of a differential load pair of a positive feedback loop is achieved.
Example 2:
the embodiment aims at the specific working condition of the wide power supply voltage range input level detection circuit when the input signal at the input end changes.
When the input signal of the input end of the wide power voltage range input level detection circuit is changed from the low level of logic 0 to the high level of logic 1, the PMOS tube P0 is closed, the NMOS tube N2 is opened, and the positive feedback loop is conducted and pulls down the gate voltage of the NMOS tube N3 and the gate voltage of the PMOS tube P3 to the low level of logic 0.
When the input signal of the input end of the wide power voltage range input level detection circuit is changed from the high level of logic 1 to the low level of logic 0, the PMOS tube P0 is turned on, the NMOS tube N2 is turned off, and the positive feedback loop is turned on and pulls the gate voltage of the NMOS tube N3 and the gate voltage of the PMOS tube P3 to the high level of logic 1.
In the process of pulling down or pulling up the gate voltage of the NMOS transistor N3 and the gate voltage of the PMOS transistor P3, the charging speed of the gates of the NMOS transistor N3 and the PMOS transistor P3 can be controlled by adjusting the resistance values of the resistor R1 and the resistor R2, and the charge-discharge balance is realized.
Example 3:
the embodiment is directed to specific working conditions of the wide power supply voltage range input level detection circuit under low power supply voltage.
In this embodiment, the low power supply voltage is related to the cmos process, and the process adopted in the present invention is a cmos process of 0.3um, and the low power supply voltage is 1V.
Taking the grid voltage of the PMOS tube P3 as an X-point voltage Vx, and taking the grid voltage of the NMOS tube N3 as a Y-point voltage Vy;
when the VDD power voltage is low voltage 1V, and when the input signal of the input end of the wide power voltage range input level detection circuit is converted from the low level of logic 0 to the high level of logic 1, the NMOS tube N1 closes the passage of the PMOS tube P1-the resistor R1-the NMOS tube N1-the PMOS tube P0, the NMOS tube N2 is opened, and the voltage Vx at the X point and the voltage Vy at the Y point are pulled down to the low voltage 1V
And the output end of the wide power supply voltage range input level detection circuit outputs a high level of logic 1.
When the voltage VIN of an input signal rises under low power supply voltage, the channel of the PMOS pipe P1, the resistor R1, the NMOS pipe N1 and the PMOS pipe P0 is closed through the NMOS pipe N1, voltages VX and VY at the point X, Y are pulled down through the opening of the NMOS pipe N2, and finally high level identification is achieved.
Taking the grid voltage of the PMOS pipe P2 as a Z-point voltage Vz;
when the VDD power voltage is a low voltage of 1V, and the input signal at the input terminal of the wide power voltage range input level detection circuit is changed from a high level of logic 1 to a low level of logic 0, and when the voltage VIN of the input signal satisfies the following formula, the path of the PMOS transistor P1-the resistor R1-the NMOS transistor N1-the PMOS transistor P0 is opened, and the Z-point voltage Vz is pulled down to a low voltage of 1V
The power supply voltage, the PMOS pipe P3 is switched on, the NMOS pipe N2 is switched off, and the voltage Vx at the X point and the voltage Vy at the Y point are pulled high
A power supply voltage, the output end of the wide power supply voltage range input level detection circuit outputs a low level of logic 0;
VDD-VIN＝VTHP+0.2V
wherein, VTHP is the threshold voltage of PMOS pipe P0.
When the input voltage is reduced under the low power supply voltage, and when VDD-VIN is equal to VTHP +0.2V, a channel of a PMOS pipe P1-a resistor R1-an NMOS pipe N1-a PMOS pipe P0 is opened, the voltage of a Z point is pulled down, at the moment, a PMOS pipe P3 is opened, then the NMOS pipe N2 is gradually closed, the voltage of VX and VY is increased, and finally the input low level recognition under the low power supply voltage is realized.
The invention has the beneficial effects that: the wide power supply voltage range input level detection circuit regulates the opening current of N2 and P0 through the N1 tube, and therefore level identification overturning of the output end is achieved. And the circuit can expand the range of the VDD power supply voltage, so that the VDD power supply voltage meets the requirement of lower power supply voltage.
The digital input turning point of the invention is
The gate capacitance charge-discharge balance of the PMOS tube P3 and the NMOS tube N3 at the rear stage is adjusted by adding the resistor R1 and the resistor R2, so that the pulse width duty cycle transmission stability of the final circuit output waveform is realized.
In the description of the present invention, it is to be understood that the terms "center", "thickness", "upper", "lower", "horizontal", "top", "bottom", "inner", "outer", "radial", and the like, indicate orientations and positional relationships based on the orientations and positional relationships shown in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or an implicit indication of the number of technical features. Thus, features defined as "first", "second", "third" may explicitly or implicitly include one or more of the features.
Claims (7)
1. A wide power supply voltage range input level detection circuit is characterized by comprising an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, a PMOS transistor P0, a PMOS transistor P1, a PMOS transistor P2, a PMOS transistor P3, a resistor R1 and a resistor R2;
the grid electrode of the PMOS tube P0 is connected with the grid electrode of the NMOS tube N2 and is used as the input end of the wide power supply voltage range input level detection circuit, the drain electrode of the PMOS tube P0 is grounded, and the source electrode of the PMOS tube P0 is connected with the source electrode of the NMOS tube N1;
the grid electrode of the NMOS tube N1 is connected with a VDD power supply, the substrate of the NMOS tube N1 is grounded, the drain electrode of the NMOS tube N1 is respectively connected with one end of the resistor R1 and the grid electrode of the PMOS tube P2, the other end of the resistor R1 is connected with the drain electrode of the PMOS tube P1, the source electrode of the PMOS tube P1 is connected with the VDD power supply, and the grid electrode of the PMOS tube P1 is respectively connected with one end of the resistor R2, the drain electrode of the NMOS tube N2 and the grid electrode of the NMOS tube N3;
the source electrode of the NMOS tube N2 is grounded, the other end of the resistor R2 is connected with the drain electrode of the PMOS tube P2 and the grid electrode of the PMOS tube P3 respectively, the source electrode of the PMOS tube P2 is connected with the VDD power supply, the source electrode of the PMOS tube P3 is connected with the VDD power supply, the drain electrode of the PMOS tube P3 is connected with the drain electrode of the NMOS tube N3 and serves as the output end of the wide power supply voltage range input level detection circuit, and the source electrode of the NMOS tube N3 is grounded.
2. The wide power supply voltage range input level detection circuit of claim 1, wherein the NMOS transistor N1 is a low threshold NMOS transistor with a threshold voltage of 0.2V.
3. The wide supply voltage range input level detection circuit of claim 2, wherein the PMOS transistor P1, the PMOS transistor P2, the resistor R1 and the resistor R2 form a positive feedback loop.
4. The wide supply voltage range input level detection circuit of claim 3, wherein when the input signal at the input of the wide supply voltage range input level detection circuit changes from a low level of logic 0 to a high level of logic 1, the PMOS transistor P0 is turned off, the NMOS transistor N2 is turned on, and the positive feedback loop is turned on and pulls down the gate voltages of the NMOS transistor N3 and the PMOS transistor P3 to a low level of logic 0.
5. The wide supply voltage range input level detection circuit of claim 3, wherein when the input signal at the input of the wide supply voltage range input level detection circuit changes from a high level of logic 1 to a low level of logic 0, the PMOS transistor P0 is turned on, the NMOS transistor N2 is turned off, and the positive feedback loop is turned on and pulls up the gate voltage of the NMOS transistor N3 and the gate voltage of the PMOS transistor P3 to a high level of logic 1.
6. The wide supply voltage range input level detection circuit of claim 5, wherein the gate voltage of the PMOS transistor P3 is taken as an X-point voltage Vx, and the gate voltage of the NMOS transistor N3 is taken as a Y-point voltage Vy;
when the VDD power supply voltage is low voltage 1V, and the input signal of the input end of the wide power supply voltage range input level detection circuit is converted from the low level of logic 0 to the high level of logic 1, the NMOS transistor N1 closes the path of the PMOS transistor P1-the resistor R1-the NMOS transistor N1-the PMOS transistor P0, the NMOS transistor N2 is turned on, and the X-point voltage Vx and the Y-point voltage Vy are pulled down to the low level
And the output end of the wide power supply voltage range input level detection circuit outputs a high level of logic 1.
7. The wide power supply voltage range input level detection circuit according to claim 6, wherein the gate voltage of the PMOS transistor P2 is taken as a Z-point voltage Vz;
when the VDD power voltage is a low voltage of 1V, and the input signal at the input end of the wide power voltage range input level detection circuit is changed from a high level of logic 1 to a low level of logic 0, and when the voltage VIN of the input signal satisfies the following formula, the path of the PMOS transistor P1-the resistor R1-the NMOS transistor N1-the PMOS transistor P0 is opened, and the VDD power voltage is at a low voltage of 1V, and the path of the PMOS transistor P1-the resistor R1-the NMOS transistor N1-the PMOS transistor P0 is openedThe voltage Vz at the point Z is reduced to
The power supply voltage is that the PMOS tube P3 is switched on, the NMOS tube N2 is switched off, and the voltage Vx at the X point and the voltage Vy at the Y point are pulled high
A power supply voltage, the output end of the wide power supply voltage range input level detection circuit outputs a low level of logic 0;
VDD-VIN＝VTHP+0.2V
wherein, VTHP is the threshold voltage of PMOS pipe P0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210523549.3A CN114884489A (en) | 2022-05-13 | 2022-05-13 | Wide power supply voltage range input level detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210523549.3A CN114884489A (en) | 2022-05-13 | 2022-05-13 | Wide power supply voltage range input level detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114884489A true CN114884489A (en) | 2022-08-09 |
Family
ID=82675275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210523549.3A Pending CN114884489A (en) | 2022-05-13 | 2022-05-13 | Wide power supply voltage range input level detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114884489A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6002290A (en) * | 1997-12-23 | 1999-12-14 | Sarnoff Corporation | Crisscross voltage level shifter |
| KR20050122292A (en) * | 2004-06-24 | 2005-12-29 | 삼성전자주식회사 | Level shifter improving duty rate and level shifting method using the same |
| US20070002640A1 (en) * | 2005-06-30 | 2007-01-04 | Hynix Semiconductor Inc. | Bulk bias voltage level detector in semiconductor memory device |
| US20080074148A1 (en) * | 2006-08-23 | 2008-03-27 | Stmicroelectronics Pvt. Ltd. | High speed level shifter |
| US7755392B1 (en) * | 2009-05-21 | 2010-07-13 | Ememory Technology Inc. | Level shift circuit without high voltage stress of transistors and operating at low voltages |
| JP2011166461A (en) * | 2010-02-10 | 2011-08-25 | Seiko Npc Corp | Level shift circuit and oscillator using the same |
| US20130162294A1 (en) * | 2011-12-22 | 2013-06-27 | Renesas Electronics Corporation | Level shift circuit and drive circuit of display device |
| CN111817705A (en) * | 2020-07-27 | 2020-10-23 | 中国电子科技集团公司第五十八研究所 | Self-induction self-acceleration bidirectional level conversion circuit |
-
2022
- 2022-05-13 CN CN202210523549.3A patent/CN114884489A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6002290A (en) * | 1997-12-23 | 1999-12-14 | Sarnoff Corporation | Crisscross voltage level shifter |
| KR20050122292A (en) * | 2004-06-24 | 2005-12-29 | 삼성전자주식회사 | Level shifter improving duty rate and level shifting method using the same |
| US20070002640A1 (en) * | 2005-06-30 | 2007-01-04 | Hynix Semiconductor Inc. | Bulk bias voltage level detector in semiconductor memory device |
| US20080074148A1 (en) * | 2006-08-23 | 2008-03-27 | Stmicroelectronics Pvt. Ltd. | High speed level shifter |
| US7755392B1 (en) * | 2009-05-21 | 2010-07-13 | Ememory Technology Inc. | Level shift circuit without high voltage stress of transistors and operating at low voltages |
| JP2011166461A (en) * | 2010-02-10 | 2011-08-25 | Seiko Npc Corp | Level shift circuit and oscillator using the same |
| US20130162294A1 (en) * | 2011-12-22 | 2013-06-27 | Renesas Electronics Corporation | Level shift circuit and drive circuit of display device |
| CN111817705A (en) * | 2020-07-27 | 2020-10-23 | 中国电子科技集团公司第五十八研究所 | Self-induction self-acceleration bidirectional level conversion circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7511555B2 (en) | Level conversion circuit and input-output device using same | |
| US7521970B2 (en) | High voltage tolerant input buffer | |
| US10944390B2 (en) | High-speed and low-noise dynamic comparator | |
| CN103780242B (en) | Driving circuit | |
| JPS63304718A (en) | Output interface circuit | |
| US5796281A (en) | Input buffer circuit with hysteresis for noise control | |
| CN114441842B (en) | Zero-crossing detection circuit for peak current mode control Buck converter | |
| CN101777316B (en) | Output buffer with high driving ability | |
| CN114884489A (en) | Wide power supply voltage range input level detection circuit | |
| CN112671391A (en) | Level conversion circuit | |
| CN110007127B (en) | Voltage detection circuit | |
| US20230132469A1 (en) | Level shift circuit | |
| CN106374886B (en) | Non-repeatable triggering CMOS integrated monostable circuit | |
| CN111510090B (en) | Operational amplifier with high voltage slew rate and wide output range | |
| US20130181764A1 (en) | Semiconductor integrated circuit | |
| CN111510118B (en) | Low-power-consumption high-speed comparator | |
| CN113726330A (en) | Level conversion circuit and chip | |
| US6252437B1 (en) | Circuit and method for reducing a propagation delay associated with a comparator and a comparator employing the same | |
| US8766692B1 (en) | Supply voltage independent Schmitt trigger inverter | |
| CN220492858U (en) | Push-pull type output circuit for preventing reverse input electric leakage | |
| CN106292817B (en) | The voltage buffer circuit and system of fast lifting output current | |
| CN115118270A (en) | Level shift circuit | |
| US10848135B1 (en) | Receiver design with reduced variation | |
| CN216649654U (en) | Substrate bias circuit | |
| CN111313879B (en) | Time delay circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |