CN114884379B

CN114884379B - Synchronous rectification control circuit, switching power supply and chip

Info

Publication number: CN114884379B
Application number: CN202210667468.0A
Authority: CN
Inventors: 蔡林甫; 沈飏; 王梁
Original assignee: Chengdu Lipson Microelectronics Co ltd
Current assignee: Chengdu Lipson Microelectronics Co ltd
Priority date: 2022-06-13
Filing date: 2022-06-13
Publication date: 2023-03-21
Anticipated expiration: 2042-06-13
Also published as: CN114884379A

Abstract

The application relates to a synchronous rectification control circuit, a switching power supply and a chip, and belongs to the technical field of electronic circuits. The synchronous rectification control circuit comprises a difference circuit and a discharge circuit. The difference circuit outputs a difference current based on the difference between the sampling voltage of the drain end voltage of the secondary rectifier tube and a preset reference voltage; the discharge circuit is respectively connected with the difference circuit and the grid end of the secondary rectifying tube, and is used for amplifying the difference current of the difference circuit and discharging the grid end voltage of the secondary rectifying tube by using the amplified difference current so as to reduce the grid end voltage of the secondary rectifying tube. The synchronous rectification control circuit can solve the problems that Vg can be excessively pulled down to cause the Ron of the secondary rectifier tube to be increased, the loss efficiency of the secondary rectifier tube is high and the false opening of the secondary rectifier tube is easily triggered in the existing scheme of pulling down the gate end voltage of the secondary rectifier tube in advance.

Description

Synchronous rectification control circuit, switching power supply and chip

Technical Field

The application belongs to the technical field of electronic circuits, and particularly relates to a synchronous rectification control circuit, a switching power supply and a chip.

Background

In a secondary synchronous rectification scheme of a switching power supply, aiming at the problems that a secondary rectifier tube (particularly, a Metal OxIde Semiconductor Field Effect Transistor (MOSFET)) is low in turn-off speed, the primary rectifier tube and the secondary rectifier tube are easy to be communicated with each other, a crossover phenomenon is generated (the primary rectifier tube and the secondary rectifier tube are simultaneously conducted, so that the current of the secondary rectifier tube is rapidly increased), extra chip loss is generated by a light person, and a chip is burnt by a heavy person, a gate terminal voltage Vg of the secondary rectifier tube is pulled down in advance, so that after a turn-off mechanism is triggered, the voltage Vg of the secondary rectifier tube can be immediately pulled down, and the rapid turn-off is realized.

Fig. 1 is a control schematic diagram of a gate terminal voltage of a conventional advanced pull-down secondary rectifier, and an internal circuit schematic diagram of a control chip U1 in fig. 1 is shown by a dashed line box in fig. 2. When Vd > Vref, the comparison signal is low, the Q1 transistor is turned on, and at this time, the gate terminal voltage Vg of the secondary rectifier is charged by the branch current of the bias current source, and Ron (on-resistance) of the secondary rectifier decreases as Vg increases, and it can be known from Vd = Id × Ron that Vd decreases less negatively as Ron decreases. When Vd < Vref, the comparison signal is high level, the Q1 tube is turned off, the gate voltage Vg of the secondary rectifier tube is pulled down by the branch current of the bias current source, as Vg decreases, ron (on-resistance) of the secondary rectifier tube increases, as can be known from Vd = Id Ron, as Ron increases, vd will be more negative, when Vd > Vref, the comparison signal is low level, the Q1 tube is turned on, at this time, the gate voltage Vg of the secondary rectifier tube is charged by the branch current of the bias current source, and thus, the Vd voltage will fluctuate (oscillate) around the Vref voltage. When Id =0, the turn-off mechanism immediately pulls Vg to a low potential, and turns off the secondary rectifier tube.

The inventor of the present invention has found that, when the gate terminal voltage of the conventional auxiliary rectifier is pulled down in advance, the pull-down current (which is a constant magnitude current injected by the bias current source) cannot be controlled in real time, and excessive pull-down of Vg increases Ron of the auxiliary rectifier, resulting in high loss efficiency of the auxiliary rectifier. And the voltage comparator has time delay, when Vd is less than Vref, it may cause that the Q1 tube cannot be turned off in time, vg is pulled high by the continuous charging of the fixed current, light Vd is caused to oscillate back and forth near Vref, heavy Vd may cause the secondary side rectifier tube to be triggered to be turned on again, so the pre-turn-off technology is equivalent to failure.

Disclosure of Invention

Therefore, an object of the present invention is to provide a synchronous rectification control circuit, a switching power supply and a chip, so as to solve the problems of the conventional scheme that Vg may be excessively pulled down, ron of a secondary rectifier becomes large, loss efficiency of the secondary rectifier is high, and the secondary rectifier is easily triggered to be turned on by mistake.

The embodiment of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a synchronous rectification control circuit, including: a difference circuit and a discharge circuit; the difference circuit outputs a difference current based on the difference between the sampling voltage of the drain end voltage of the secondary rectifier tube and a preset reference voltage; the discharge circuit is respectively connected with the difference circuit and the grid end of the secondary rectifying tube, and is used for amplifying the difference current and discharging the grid end voltage of the secondary rectifying tube by the amplified difference current so as to reduce the grid end voltage of the secondary rectifying tube.

In the embodiment of the present application, a differential current is generated based on a difference between a sampled voltage (for example, vd _ SENSE) of a drain terminal voltage of the secondary rectifier tube and a preset reference voltage VR, and the differential current is amplified to be used as a pull-down current of a gate terminal of the secondary rectifier tube, and the gate terminal voltage of the secondary rectifier tube is pulled down (discharged), so that the gate terminal voltage of the secondary rectifier tube is reduced. Because the voltage comparator is not used for outputting high and low levels as in the prior art, the difference circuit is used for outputting the difference current and is used as the pull-down current of the gate end of the secondary side rectifying tube, the defect caused by time delay of the voltage comparator is overcome (the Q1 tube can not be turned off in time, vg is pulled up by continuously charging the fixed current, vd oscillates back and forth near Vref in light and the secondary side rectifying tube can be triggered to be turned on again in heavy), and the response speed is improved. Simultaneously, the pull-down current in this application can receive sampling voltage real-time adjustment to control Vg's pull-down current, make Vg voltage descend slowly, vd voltage is the trend that gradually tends to 0 and rises, can not cause excessive Vg that draws down like this, thereby cause the Ron grow of vice limit rectifier tube, cause the problem that loss efficiency of vice limit rectifier tube is big.

With reference to a possible implementation manner of the embodiment of the first aspect, the difference circuit includes: a pull-down threshold branch circuit and a first current mirror unit; a pull-down threshold branch for generating the preset reference voltage; one side of the first current mirror unit is grounded, the other side of the first current mirror unit is connected with the pull-down threshold branch circuit and the discharge circuit, and the pull-down threshold branch circuit is connected to the sampling voltage of the drain terminal voltage of the secondary rectifier tube.

In the embodiment of the application, the preset reference voltage is generated by setting the pull-down threshold branch circuit, the corresponding differential current is generated by setting the first current mirror unit according to the comparison result of the sampling circuit and the preset reference voltage, so that the pull-down current is controlled by the sampling voltage, and the excessive pull-down Vg is avoided, so that the Ron of the secondary rectifier tube is increased, and the loss efficiency of the secondary rectifier tube is increased.

With reference to one possible implementation manner of the embodiment of the first aspect, the first current mirror unit includes: the device comprises a first constant current source, a second constant current source, a first MOS (metal oxide semiconductor) tube and a second MOS tube which forms a mirror image with the first MOS tube; the second end of the first MOS tube is connected with the first constant current source, and the first end of the first MOS tube is grounded; the second constant current source is respectively connected with the second end of the second MOS tube and the discharge circuit, and the first end of the second MOS tube is connected with the pull-down threshold branch.

In the embodiment of the present application, the first current mirror unit structure is sampled, so that the difference current generated by the difference circuit is I2-IM2, I2 is the current of the second constant current source, and IM2 is the current flowing through the second MOS transistor M2, so that the magnitude of the difference current is controllable.

With reference to one possible implementation manner of the embodiment of the first aspect, the first current mirror unit further includes: a third MOS tube and a fourth MOS tube; the second end of the third MOS tube is connected with the first constant current source, the second end of the third MOS tube is connected with the grid end of the third MOS tube, and the first end of the third MOS tube is connected with the second end of the first MOS tube; the grid end of the fourth MOS tube is connected with the grid end of the third MOS tube, the second end of the fourth MOS tube is connected with the second constant current source, the second end of the fourth MOS tube is connected with the discharge circuit, and the first end of the fourth MOS tube is connected with the second end of the second MOS tube.

In the embodiment of the application, by further adding a cascode current mirror (a third MOS transistor and a fourth MOS transistor constitute the cascode current mirror), the output voltage of a point a (i.e., a second end of the fourth MOS transistor) of the cascode current mirror changes more under the same voltage variation, so that the voltage of the point a drops faster, the IM2 drops faster, and finally the I2-IM2 rises faster, so as to increase the differential current output by the differential circuit, where the maximum current is I2.

With reference to a possible implementation manner of the embodiment of the first aspect, a size of the first MOS transistor is consistent with a size of the second MOS transistor, and a size of the third MOS transistor is consistent with a size of the fourth MOS transistor.

In the embodiment of the application, the size of the first MOS transistor is consistent with that of the second MOS transistor, and the size of the third MOS transistor is consistent with that of the fourth MOS transistor, so that the proportionality coefficient between the input current and the output current of the first current mirror unit can be ensured to be 1 to 1.

With reference to one possible implementation manner of the embodiment of the first aspect, the drop-down threshold branch includes: the switch comprises a plurality of switch branches connected in parallel, each switch branch comprises a switch and a voltage regulating resistor connected in series, and the resistance values of the voltage regulating resistors corresponding to different switch branches are different; alternatively, the pull-down threshold branch comprises a pull-down resistor.

In the embodiment of the application, the pull-down threshold branch circuit comprising a plurality of parallel switch branch circuits is adopted, and the on and off of the switch are controlled in advance, so that the resistance value of the pull-down threshold branch circuit can be changed, and the size of the preset reference voltage VR is adjusted.

With reference to one possible implementation manner of the embodiment of the first aspect, the discharge circuit includes: a current limiting resistor and a second current mirror unit; the first end of the second current mirror unit is connected with the difference circuit, the second end of the second current mirror unit is connected with the grid end of the secondary rectifier tube through the current-limiting resistor, the ratio coefficient of the input current and the output current of the second current mirror unit is 1 to M, M is the amplification factor, and M is more than 1.

With reference to one possible implementation manner of the embodiment of the first aspect, the second current mirror unit includes: an input MOS tube branch and an output MOS tube branch; the input MOS tube branch circuit is connected with the difference circuit, the input MOS tube branch circuit comprises A input MOS tubes which are connected in series, and A is an integer more than or equal to 1; the output MOS tube branch comprises N output MOS tubes connected in parallel, N is an integer greater than or equal to 1, and M = A × N; every the gate terminal of output MOS pipe with the gate terminal of the input MOS pipe in the input MOS pipe branch road is connected, every the first end ground connection of output MOS pipe, every the second end of output MOS pipe passes through current-limiting resistor with the gate terminal of vice limit rectifier tube is connected.

In the embodiment of the present application, with the second current mirror unit having the above structure, the amplification factor of the second current mirror unit can be set by setting the values of a and N.

With reference to one possible implementation manner of the embodiment of the first aspect, the synchronous rectification control circuit further includes a sampling circuit, configured to sample a drain terminal voltage of the secondary rectifier tube, and output a sampled voltage to the difference circuit.

With reference to one possible implementation manner of the embodiment of the first aspect, the synchronous rectification control circuit further includes a driving circuit connected to a gate terminal of the secondary rectifier, where the driving circuit is configured to output a driving signal to control on or off of the secondary rectifier.

In a second aspect, an embodiment of the present application further provides a switching power supply, including: a secondary rectifier and a synchronous rectification control circuit as provided in the above-described embodiment of the first aspect and/or in connection with any one of the possible implementations of the embodiment of the first aspect.

In a third aspect, an embodiment of the present application further provides a chip, which integrates the synchronous rectification control circuit as provided in the foregoing first aspect and/or in combination with any one of the possible implementations of the first aspect.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.

Fig. 1 is a control schematic diagram of a gate terminal voltage of a conventional advanced pull-down secondary rectifier.

Fig. 2 is a schematic diagram of a connection between an internal circuit of the control chip U1 and a secondary rectifier in the related art in fig. 1.

Fig. 3 shows a schematic diagram of a switching power supply provided in an embodiment of the present application.

Fig. 4 shows a schematic connection diagram of a synchronous rectification control circuit and a secondary rectifier according to an embodiment of the present application.

Fig. 5 shows a schematic connection diagram of a synchronous rectification control circuit and a secondary rectifier according to an embodiment of the present application.

Fig. 6 shows a schematic diagram of waveforms involved in a synchronous rectification control circuit provided by an embodiment of the present application.

Fig. 7 shows a schematic connection diagram of a synchronous rectification control circuit and a secondary rectifier according to an embodiment of the present application.

Fig. 8 shows a schematic connection diagram of a further synchronous rectification control circuit and a secondary rectifier provided in an embodiment of the present application.

Fig. 9 shows a schematic connection diagram of another synchronous rectification control circuit and a secondary rectifier provided in the embodiment of the present application.

Fig. 10 shows a schematic connection diagram of a synchronous rectification control circuit and a secondary rectifier according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely in the description herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process item or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, item or apparatus. Without further limitation, an element defined by the phrases "comprising a" \8230; "does not exclude the presence of additional like elements in a process, article, or device that comprises the element.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, e.g., as meaning either a fixed connection, a detachable connection, or an integral connection; or may be an electrical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.

Furthermore, the term "and/or" in this application is only one kind of association relationship describing the associated object, and means that there may be three relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The term "plurality" usually means 2 and 2 or more by default unless otherwise specified.

In view of the defects of the prior art that the gate terminal voltage of the secondary rectifier is pulled down in advance, as shown in fig. 2, in a first aspect, an embodiment of the present application provides a synchronous rectification control circuit, which generates a difference current by a difference between a sampled voltage (e.g., vd _ SENSE) of a drain terminal voltage Vd of the secondary rectifier and a preset reference voltage VR, amplifies the difference current to be a pull-down current of the gate terminal of the secondary rectifier, and pulls down (discharges) the gate terminal voltage of the secondary rectifier to lower the gate terminal voltage of the secondary rectifier. It should be noted that, the discovery process of the above problems and the solutions proposed by the embodiments of the present invention for the above problems should be contributions from the inventors to the present invention in the process of the present invention.

Because the voltage comparator is not used for outputting high and low levels as in the prior art, the difference circuit is used for outputting the difference current and is used as the pull-down current of the gate end of the secondary side rectifying tube, the defect caused by time delay of the voltage comparator is overcome (the Q1 tube can not be turned off in time, vg is pulled up by continuously charging the fixed current, vd oscillates back and forth near Vref in light and the secondary side rectifying tube can be triggered to be turned on again in heavy), and the response speed is improved. Simultaneously, the pull-down current in this application can receive sampling voltage real-time adjustment to control Vg's pull-down current, make Vg voltage descend slowly, vd voltage is the trend that gradually tends to 0 and rises, can not cause excessive Vg that draws down like this, thereby cause the Ron grow of vice limit rectifier tube, cause the problem that loss efficiency of vice limit rectifier tube is big.

For the convenience of understanding, the following description is made in conjunction with a switching power supply provided in an embodiment of the present application, and the switching power supply includes a synchronous rectification control circuit for pulling down a gate terminal voltage of a secondary side rectifier in advance before a turn-off mechanism is triggered. In one embodiment, a schematic diagram of a switching power supply is shown in fig. 3. The switching power supply comprises a synchronous rectification control circuit, a transformer T, a primary side tube N2, a secondary side rectification tube N1 and an energy storage capacitor C0. The resistor R shown in fig. 3 is a load supplied by the switching power supply. The synchronous rectification control circuit is used for pulling down the grid end voltage of the secondary rectifier tube in advance before the turn-off mechanism is triggered, so that Vg can be pulled to a low potential immediately after the turn-off mechanism is triggered, and the secondary rectifier tube is turned off. Under normal conditions, the primary side tube N2 and the secondary side rectifier tube N1 cannot be conducted simultaneously, and when the primary side tube N2 is conducted, the secondary side rectifier tube N1 is in an off state. If the secondary rectifier tube N1 is low in turn-off speed, the mutual communication between the primary rectifier tube N2 and the secondary rectifier tube N1 is easily caused, therefore, the grid end voltage of the secondary rectifier tube N1 is pulled down in advance through the synchronous rectification control circuit in the application, so that after a turn-off mechanism is triggered, vg can be pulled to a low potential immediately to turn off the secondary rectifier tube N1.

A synchronous rectification control circuit provided in an embodiment of the present application will be described below with reference to fig. 4, where the synchronous rectification control circuit includes: a difference circuit and a discharge circuit. Optionally, the synchronous rectification control circuit may further include a sampling circuit, configured to sample a drain terminal voltage of the secondary rectifier tube, and output the sampled voltage to the difference circuit. The sampling circuit may be one that is currently commonly used to collect voltages.

And the difference circuit is used for outputting a difference current based on the difference between the sampling voltage (represented by Vd _ SENSE) of the drain end voltage of the secondary side rectifier tube and the preset reference voltage VR. And the discharge circuit is respectively connected with the difference circuit and the gate end of the secondary rectifying tube and is used for amplifying the difference current output by the difference circuit, and using the amplified difference current as the pull-down current of the gate end of the secondary rectifying tube to pull down (discharge) the voltage of the gate end of the secondary rectifying tube so as to reduce the voltage of the gate end of the secondary rectifying tube.

In one embodiment, the difference circuit includes a pull-down threshold branch and a first current mirror unit. One side of the first current mirror unit is grounded, the other side of the first current mirror unit is connected with a pull-down threshold branch circuit and a discharge circuit, and the pull-down threshold branch circuit is connected to a sampling voltage of the drain voltage of the secondary rectifier tube. The ratio coefficient of the input current to the output current of the first current mirror unit is 1 to 1. And the pull-down threshold branch is used for generating a preset reference voltage VR. And generating a difference current by the difference of the sampling voltages Vd _ SENSE and VR, and then amplifying the current to be used as a pull-down current of Vg, so that the size of the pull-down current is adjustable.

In an optional implementation manner, the pull-down threshold branch may only include one resistor, and in order to implement that the preset reference voltage is adjustable, optionally, as shown in fig. 5, the pull-down threshold branch may include a plurality of switch branches connected in parallel, each switch branch includes a switch and a voltage-regulating resistor connected in series, and the resistance values of the voltage-regulating resistors corresponding to different switch branches may be different or may be the same. The on and off of the switches (S1, S2 and/or S3) are controlled, so that the resistance value of the pull-down threshold branch circuit can be changed, and the size of the preset reference voltage VR is adjusted. It should be noted that only 3 parallel switching branches are shown in fig. 5. The number of switching legs is not limited thereto and therefore should not be construed as a limitation of the present application.

In one embodiment, and with continued reference to fig. 5, the first current mirror unit includes: the MOS transistor comprises a first constant current source, a second constant current source, a first MOS transistor (such as M1) and a second MOS transistor (such as M2) which forms a mirror image with the first MOS transistor. In fig. 5, I1 is a current of the first constant current source, I2 is a current of the second constant current source, IM1 is a current flowing through the first MOS transistor M1, IM2 is a current flowing through the second MOS transistor M2, and I1= I2.

The second end of the first MOS tube is connected with the first constant current source, the second end of the first MOS tube is connected with the grid end of the first MOS tube, and the first end of the first MOS tube is grounded; the grid end of the second MOS tube is connected with the grid end of the first MOS tube, the second end of the second MOS tube is connected with the second constant current source, the second end of the second MOS tube is also connected with the discharge circuit, and the first end of the second MOS tube is connected into the sampling voltage through the pull-down threshold branch. Optionally, the size of the first MOS transistor is the same as that of the second MOS transistor, so as to ensure that the current flowing through the first MOS transistor is the same as that flowing through the second MOS transistor.

Optionally, both the first MOS transistor and the second MOS transistor may be N transistors, and accordingly, the first end of the first MOS transistor and the first end of the second MOS transistor are source terminals, and the second end of the first MOS transistor and the second end of the second MOS transistor are drain terminals. Of course, the first MOS transistor and the second MOS transistor may also be P transistors, and accordingly, the first end of the first MOS transistor and the first end of the second MOS transistor are drain terminals, and the second end of the first MOS transistor and the second end of the second MOS transistor are source terminals.

In the application, a difference current (I2-IM 2) is generated based on a difference value between Vd _ SENSE and a preset reference voltage VR, and then the difference current is amplified and converted into a pull-down current Vg. By setting the amplification factor M and the size of the (I2-IM 2), the Vg pull-down current can be controlled in real time, so that the Vg voltage is slowly reduced, and the Vd voltage gradually tends to be increased to 0.

Assuming that the voltage difference of the pull-down threshold branch is VR and the pull-down current is I3, I3= (I2-IM 2) × M, where M is the amplification factor of the discharge circuit, and M > 1. Since the first current mirror cell ratio is 1, when VD _ SENSE + VR =0, then Vgs2= Vgs1, i.e. IM2= IM1, then I2-IM2=0, at which time the difference current is zero, accordingly, I3=0. When VD _ SENSE + VR <0, then Vgs2> Vgs1, i.e. IM2> I2, I2-IM2<0, the difference current is zero, accordingly, I3=0. When VD _ SENSE + VR >0, then Vgs2< Vgs1, I2-IM2>0, the differential current is I2-IM2, accordingly, I3= (I2-IM 2) = M. Vgs2 is the gate-source voltage of the M2 tube, and Vgs1 is the gate-source voltage of the M1 tube.

Fig. 6 shows a waveform diagram of the synchronous rectification control circuit according to the embodiment of the present application. In fig. 6, GD signal is a gate control signal of a primary side rectifier, id is a secondary side current, vd is a drain voltage of a secondary side rectifier, GD-SR signal is a gate control signal of the secondary side rectifier, and VR _ DOWN is a gate threshold of the advanced pull-DOWN secondary side rectifier.

This process of Vd changing from VR _ DOWN to the off threshold (0 mV in fig. 6) is a process of adjusting the Vg voltage, and if the VREF _ DOWN design value is too close to the off threshold, the Vg voltage is pulled DOWN by a small amount, resulting in an increased off delay. In order to reduce the turn-off delay, the value of VR _ DOWN and the size of I3 need to be properly designed. For example, in one embodiment, the value of VR _ DOWN is set to the value corresponding to VR when Vd _ SENSE + VR =0, and the magnitude of VR can be adjusted by adjusting the resistance value of the pull-DOWN threshold branch circuit; the pull-down capability of I3 can be adjusted by adjusting the amplification factor M or the current (I2-IM 2).

In the application, I2-IM2 is controlled by Vd _ SENSE voltage, if Vd _ SENSE is more than VR, the value of I2-IM2 is larger, I3 is larger, vg voltage is lower, ron is larger, vd is more negative, and the value of I2-IM2 is reduced. It can be seen that the structure of the synchronous rectification control circuit in the present application is a negative feedback control structure. Through negative feedback control, can stabilize Vd near the VR design value, compare with direct injection fixed current, the drop-down current in this application can crescent, efficiency problem when effectively having solved drop-down Vg.

It is considered that if the feedback speed of the difference circuit cannot keep up, vd may trigger the turn-on threshold, which may cause false turn-on, and the early turn-off function may be disabled. Therefore, in one embodiment, the parasitic capacitance of the MOS transistor can be reduced by reducing the size of the MOS transistor, for example, by using the MOS transistor with the gate end having a length of 180 to 600nm, so as to improve the sensitivity of the MOS transistor. In another embodiment, the difference current of the difference circuit can be increased by further adding a cascode current mirror, so that Vd _ SENSE changes faster I2-IM2 with the same voltage change.

In this embodiment, as shown in fig. 7, the first current mirror unit further includes: a third MOS transistor (such as M3) and a fourth MOS transistor (M4), wherein M3 and M4 form a cascode current mirror. Correspondingly, the second end of the third MOS tube is connected with the first constant current source, the second end of the third MOS tube is connected with the grid end of the third MOS tube, and the first end of the third MOS tube is connected with the second end of the first MOS tube; the grid end of the fourth MOS tube is connected with the grid end of the third MOS tube, the second end of the fourth MOS tube is connected with a second constant current source, the second end of the fourth MOS tube is further connected with a discharge circuit, and the first end of the fourth MOS tube is connected with the second end of the second MOS tube. Optionally, the size of the third MOS transistor is the same as the size of the fourth MOS transistor.

Optionally, the third MOS transistor and the fourth MOS transistor may both be N transistors, and accordingly, a first end of the third MOS transistor and a first end of the fourth MOS transistor are source terminals, and a second end of the third MOS transistor and a second end of the fourth MOS transistor are drain terminals. Of course, the third MOS transistor and the fourth MOS transistor may also be P transistors, and accordingly, the first end of the third MOS transistor and the first end of the fourth MOS transistor are drain terminals, and the second end of the third MOS transistor and the second end of the fourth MOS transistor are source terminals.

By further adding a cascode current mirror on the basis of fig. 5, the amplification factor of the discharge circuit can be improved, so that Vd _ SENSE can change the I2-IM2 faster with the same voltage change. Assuming that V1 is the variation of the voltage at point a and V2 is the variation of the voltage at point B, V1/ro4 (1/gm 4)/ro 2 (1/gm 2) = V2, then V1= gm4 ro4 × gm2 × ro2 × V2. Accordingly, the amplification factor is gm4 × ro4 × gm2 × ro2. Where ro4 is the on-resistance of M4, gm4 is the transconductance of M4, gm2 is the on-resistance of M2 of ro2, and gm2 is the transconductance of M2.

Under one embodiment, a discharge circuit includes: a current limiting resistor and a second current mirror unit. The first end of the second current mirror unit is connected with the difference circuit, the second end of the second current mirror unit is connected with the grid end of the secondary rectifier tube through a current-limiting resistor, the ratio coefficient of the input current and the output current of the second current mirror unit is 1 to M, M is an amplification factor and is M & gt 1, and the numerical value of M can be set as required.

As shown in fig. 8, the second current mirror unit includes an input MOS transistor branch and an output MOS transistor branch. And the input MOS tube branch circuit is connected with the difference circuit, the input MOS tube branch circuit comprises A input MOS tubes which are connected in series, and A is an integer more than or equal to 1. The output MOS tube branch comprises N output MOS tubes connected in parallel, N is an integer larger than or equal to 1, and M = A × N. The gate end of each output MOS tube is connected with the gate end of the input MOS tube in the input MOS tube branch, the first end of each output MOS tube is grounded, and the second end of each output MOS tube is connected with the gate end of the secondary rectifying tube through a current-limiting resistor. The input MOS tube and the output MOS tube can be N tubes or P tubes.

For better understanding, the example is given by taking the case that the input MOS transistor branch includes 2 input MOS transistors, and a schematic diagram thereof is shown in fig. 9. At this time, the amplification ratio of the second current mirror unit is 1. The output MOS transistor branch in fig. 9 includes N output MOS transistors connected in parallel, and not all of them are shown in the figure. Further, the specific example of I3=2N (I2-IM 2) in fig. 9 should not be construed as limiting the present application. If the input MOS transistor branch includes 1 input MOS transistor, the amplification ratio of the second current mirror unit is 1. If the input MOS transistor branch includes 3 input MOS transistors, the amplification ratio of the second current mirror unit is 1. If the input MOS transistor branch includes a input MOS transistors, the amplification ratio of the second current mirror unit is 1 a × N, and accordingly I3= a × N (I2-IM 2) = M (I2-IM 2).

Optionally, as shown in fig. 10, the synchronous rectification control circuit further includes a driving circuit connected to a gate terminal of the secondary rectifier, and the driving circuit is configured to output a driving signal to control on or off of the secondary rectifier. If the secondary rectifier tube is an N tube, the secondary rectifier tube is turned on when the driving signal is at a high level, and is turned off when the driving signal is at a low level. On the contrary, the secondary rectifier tube is a P-tube, and the secondary rectifier tube is turned on when the driving signal is at a low level and turned off when the driving signal is at a high level. The driving circuit may be a commonly used driving circuit in the market.

Based on the same inventive concept, the embodiment of the present application further provides a chip, and the chip is integrated with the synchronous rectification control circuit shown above. The chip integrated with the synchronous rectification control circuit can be applied to a switching power supply and is used for controlling the on/off of a secondary rectifier tube in the switching power supply.

The chip provided by the embodiment of the present application has the same implementation principle and technical effect as those of the aforementioned embodiment of the synchronous rectification control circuit, and for the sake of brief description, no mention is made in the embodiment of the chip, and reference may be made to the corresponding contents in the embodiment of the synchronous rectification control circuit.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A synchronous rectification control circuit, comprising:

the difference circuit outputs a difference current based on the difference between the sampling voltage of the drain end voltage of the secondary rectifier tube and a preset reference voltage;

and the discharge circuit is respectively connected with the difference circuit and the grid end of the secondary rectifying tube, and is used for amplifying the difference current and discharging the grid end voltage of the secondary rectifying tube by using the amplified difference current so as to reduce the grid end voltage of the secondary rectifying tube.

2. The synchronous rectification control circuit of claim 1, wherein the difference circuit comprises:

a pull-down threshold branch for generating the preset reference voltage;

the first current mirror unit, the input current side ground of first current mirror unit, the first end of the output current side of first current mirror unit is passed through drop-down threshold value branch road inserts the sampling voltage of the drain terminal voltage of vice limit rectifier tube, the second end of output current side with discharge circuit connects.

3. The synchronous rectification control circuit of claim 2, wherein the first current mirror unit comprises:

a first constant current source and a second constant current source;

the MOS transistor comprises a first MOS transistor and a second MOS transistor which forms a mirror image with the first MOS transistor;

the second end of the first MOS tube is connected with the first constant current source, and the first end of the first MOS tube is grounded;

the second constant current source is respectively connected with the second end of the second MOS tube and the discharge circuit, and the first end of the second MOS tube is connected with the pull-down threshold branch.

4. The synchronous rectification control circuit of claim 3, wherein the first current mirror unit further comprises:

the second end of the third MOS tube is connected with the first constant current source, the second end of the third MOS tube is connected with the grid end of the third MOS tube, and the first end of the third MOS tube is connected with the second end of the first MOS tube;

the grid end of the fourth MOS tube is connected with the grid end of the third MOS tube, the second end of the fourth MOS tube is connected with the second constant current source, the second end of the fourth MOS tube is further connected with the discharge circuit, and the first end of the fourth MOS tube is connected with the second end of the second MOS tube.

5. The synchronous rectification control circuit of claim 4, wherein the first MOS transistor has a size consistent with that of the second MOS transistor, and the third MOS transistor has a size consistent with that of the fourth MOS transistor.

6. The synchronous rectification control circuit of claim 2, wherein the pull-down threshold branch comprises:

the switch comprises a plurality of switch branches connected in parallel, each switch branch comprises a switch and a voltage regulating resistor connected in series, and the resistance values of the voltage regulating resistors corresponding to different switch branches are different;

alternatively, the pull-down threshold branch comprises a pull-down resistor.

7. The synchronous rectification control circuit of any one of claims 1-6, wherein the discharge circuit comprises:

a current limiting resistor;

the input of second current mirror unit with difference circuit connects, the output of second current mirror unit passes through current-limiting resistor with the grid end of secondary side rectifier tube is connected, the input current of second current mirror unit and output current's scale factor are 1 than M, M be the magnification, and M > 1.

8. The synchronous rectification control circuit of claim 7, wherein the second current mirror unit comprises:

the input MOS tube branch circuit is connected with the difference circuit and comprises A input MOS tubes which are connected in series, and A is an integer more than or equal to 1;

the output MOS tube branch comprises N output MOS tubes connected in parallel, N is an integer greater than or equal to 1, and M = A × N; every the gate terminal of output MOS pipe with the gate terminal of the input MOS pipe in the input MOS pipe branch road is connected, every the first end ground connection of output MOS pipe, every the second end of output MOS pipe passes through current-limiting resistor with the gate terminal of vice limit rectifier tube is connected.

9. A switching power supply, comprising: a secondary rectifier and a synchronous rectification control circuit as claimed in any one of claims 1 to 8.

10. A chip incorporating a synchronous rectification control circuit as claimed in any one of claims 1 to 8.