CN114883303A

CN114883303A - WAT test structure and method

Info

Publication number: CN114883303A
Application number: CN202210345474.4A
Authority: CN
Inventors: 张炜虎; 仇峰; 王珊珊
Original assignee: GTA Semiconductor Co Ltd
Current assignee: GTA Semiconductor Co Ltd
Priority date: 2022-03-31
Filing date: 2022-03-31
Publication date: 2022-08-09

Abstract

The invention provides a WAT test structure and a method, wherein the WAT test structure comprises: the three-region array unit comprises an input region and an output region with a first doping type and a base region with a second doping type; the base region separates the input region from the output region, and the input region and the output region of the plurality of three-region array units have different spacing sizes; the input area receives a voltage input signal, and the output area outputs a voltage output signal; the voltage detection array units correspond to the three-region array units one by one, and receive the voltage output signals and output corresponding current output signals according to the magnitude of the voltage output signals. The invention judges the number of the three-region array units of the PN junction which is conducted and represents the width range of the depletion layer of the PN junction by arranging the input region and the output region with different interval sizes and applying the same voltage input signal.

Description

WAT test structure and method

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a WAT test structure and a method.

Background

The PN junction is a basic structure of a semiconductor device, and in a wat (wafer acceptable test) test for the PN junction, the performance of the PN junction of the semiconductor device is generally measured from three dimensions, namely, a forward conduction voltage drop, a reverse leakage current, and a reverse breakdown voltage.

Currently, one important characteristic parameter affecting the three dimensions described above for PN junctions in devices is depletion layer width. Especially under the condition of applying reverse bias, the width of the depletion layer has important significance for establishing design rules related to isolation in the design of a semiconductor circuit. In the stage of platform development, for PN junctions formed by different ion implantation, a test capable of accurately representing the width of a depletion layer plays a considerable role in research.

However, currently, no WAT test structure can directly characterize the depletion layer width of the PN junction, and how to accurately characterize the depletion layer width of the PN junction of the device is of great significance to device development.

Therefore, there is a need to provide a new WAT test structure and method to solve the above problems.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a WAT test structure and method for solving the problem that the WAT test structure in the prior art cannot accurately characterize the depletion layer width of the PN junction.

To achieve the above and other related objects, the present invention provides a WAT test structure, comprising:

a plurality of three-region array units including input and output regions having a first doping type and a base region having a second doping type; the base region separates the input region from the output region, and the input region and the output region of a plurality of three-region array units have different spacing sizes; the input area receives a voltage input signal, and the output area outputs a voltage output signal;

the voltage detection array units are in one-to-one correspondence with the three-region array units, and receive the voltage output signals and output corresponding current output signals according to the voltage output signals.

As an alternative of the invention, the first doping type is N-type and the second doping type is P-type, or the first doping type is P-type and the second doping type is N-type.

As an alternative of the present invention, the maximum value of the plurality of different said interval sizes is the maximum estimated value of the depletion layer width of the PN junction between the input region and the base region, and the minimum value of the plurality of different said interval sizes is the minimum estimated value of the depletion layer width of the PN junction between the input region and the base region.

As an alternative of the present invention, the number of the three-region array units is n, n is an integer greater than 1, and a plurality of the spacing dimensions are in an arithmetic progression with a tolerance of a difference between a maximum estimated value and a minimum estimated value of the depletion layer width divided by n-1.

As an alternative of the present invention, the voltage detection array unit is an MOS transistor, a source region and a drain region of the MOS transistor have a first doping type, and a plurality of the MOS transistors correspond to a plurality of the three-region array units one to one.

As an alternative of the present invention, the output regions of the three-region array units are connected to the gates of the MOS transistors, the input regions of a plurality of the three-region array units are connected to serve as the total input end of the WAT test structure, the source regions of a plurality of the MOS transistors are connected to serve as the total output end of the WAT test structure, and a MOS transistor input voltage is applied to the drain regions of a plurality of the MOS transistors.

As an alternative of the present invention, the input region of the three-region array unit is connected to the drain region of the MOS transistor, and the input voltage of the total input terminal of the WAT test structure is simultaneously used as the input voltage of the MOS transistor.

As an alternative of the present invention, the input regions of the three-region array units are connected to the drain region or the source region of the MOS transistor, the input regions of a plurality of the three-region array units are connected to serve as the total input end of the WAT test structure, the source regions or the drain regions of a plurality of the MOS transistors are connected to serve as the total output end of the WAT test structure, and a MOS transistor switching voltage is applied to the gates of a plurality of the MOS transistors.

As an alternative of the present invention, the three-region array unit is prepared on a semiconductor substrate, and the three-region array unit is connected to the voltage detection array unit through a via structure; heavily doped regions of a first doping type are further formed between the input region and the through hole structure and between the output region and the through hole structure.

The invention also provides a WAT test method, which comprises the following steps:

providing a WAT test structure according to the invention;

applying the same voltage input signal to the input regions of a plurality of the three-region array units;

judging the number of the PN junctions between the input regions and the base regions which are conducted in the three-region array units to be m according to the current output signal;

the maximum spacing size of m three-region array units with the smallest spacing size among the plurality of three-region array units is the calculated minimum value of the depletion layer width; the maximum gap size among m +1 of the three-region array units having the smallest gap size among the plurality of three-region array units is an estimated maximum value of the depletion layer width.

As described above, the present invention provides a WAT test structure and method, which sets an input region and an output region having different interval sizes, determines the number of three-region array cells in which a PN junction has been turned on by applying the same voltage input signal, and characterizes the depletion layer width range of the PN junction.

Drawings

Fig. 1 is a top view of a single three-region array unit according to an embodiment of the invention.

Fig. 2 is a cross-sectional view of a single three-region array unit according to an embodiment of the invention.

Fig. 3 shows the WAT test structure formed by a plurality of three-region array units and a plurality of MOS transistors according to an embodiment of the invention.

Description of the element reference numerals

100 three-area array unit

101 semiconductor substrate

102 input area

103 output area

104 base region

105 through hole structure

106 heavily doped region

107 silicon local oxidation isolation

108 interlayer dielectric layer

200 MOS tube

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

Please refer to fig. 1 to 3. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Example one

Referring to fig. 1 to 3, the present invention provides a WAT test structure, which includes:

a plurality of three-region array cells 100, the three-region array cells 100 including input regions 102 and output regions 103 having a first doping type and base regions 104 having a second doping type; the base region 104 separates the input region 102 from the output region 103, and the input region 102 and the output region 103 of a plurality of the three-region array units 100 have different spacing dimensions D therebetween; the input area 102 receives a voltage input signal, and the output area 103 outputs a voltage output signal;

and the voltage detection array units correspond to the three-region array unit 100 one by one, receive the voltage output signals and output corresponding current output signals according to the magnitude of the voltage output signals.

As an example, as shown in fig. 1, is a top view of a single three-region array unit 100, the three-region array unit 100 being fabricated on a semiconductor substrate 101. Fig. 2 is a cross-sectional view of a single three-region array unit 100 in fig. 1, and fig. 3 is the WAT test structure composed of a plurality of three-region array units 100 and a plurality of MOS transistors 200.

As an example, the first doping type is N-type and the second doping type is P-type, or the first doping type is P-type and the second doping type is N-type.

In this embodiment, the first doping type is N-type and the second doping type is P-type, that is, the three-region array unit 100 is NPN structure, and the MOS transistor is an NMOS transistor. In other embodiments of the present invention, the first doping type may be P-type and the second doping type may be N-type, that is, the three-region array unit has a PNP structure, and the MOS transistor is a PMOS transistor. As shown in fig. 1, the semiconductor substrate 101 is a P-type substrate, the base region 104 is a portion of the P-type substrate, and the input region 102 and the output region 103 form an N-type doped region on the P-type substrate through a furnace diffusion process or an ion implantation process. Specifically, the maximum value of the plurality of different spacing dimensions D is the maximum estimated value of the depletion layer width of the PN junction between the input region and the base region, and the minimum value of the plurality of different spacing dimensions D is the minimum estimated value of the depletion layer width of the PN junction between the input region and the base region. As shown in fig. 3, the number of the three-region array units is n, n is an integer greater than 1, and a plurality of the spacing dimensions are in an arithmetic progression with a tolerance of a difference between a maximum estimated value and a minimum estimated value of the depletion layer width divided by n-1. For example, assuming that the approximate width of the depletion layer is in the range of 1 to 2 μm, the spacing dimension D of the n three-region array units is in the range of 1 to 2 μm. Assuming that n is 11 in this embodiment and there are 11 three-region array units such as S1-S11 in total in fig. 3, the tolerance of the arithmetic progression is 0.1 μm, and the spacing dimension D is 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm, and 2 μm in this order. In other embodiments of the present invention, the range of the spacing dimension D and the tolerance of the arithmetic progression may also be modified according to practical situations and experience.

As an example, as shown in fig. 3, in the present embodiment, the voltage detection array unit is an MOS transistor 200, a source region and a drain region of the MOS transistor 200 have a first doping type, and a plurality of the MOS transistors 200 correspond to a plurality of the three-region array units 100 one to one.

As an example, as shown in fig. 3, the output region 103 of the three-region array unit 100 is connected to the gate of the MOS transistor, the input regions 102 of a plurality of the three-region array units 100 are connected as the total input end of the WAT test structure, the source regions of a plurality of the MOS transistors 200 are connected as the total output end of the WAT test structure, and a MOS transistor input voltage is applied to the drain regions of a plurality of the MOS transistors 200.

providing the WAT test structure according to the present embodiment;

applying the same voltage input signal to the input regions 102 of a plurality of the three-region array units 100;

judging the number of the PN junctions between the input region 102 and the base region 104 that have been conducted in the plurality of three-region array units 100 to be m according to the current output signal;

the maximum spacing dimension D of the m three-region array units 100 having the smallest spacing dimension among the plurality of three-region array units 100 is the estimated minimum value of the depletion layer width; the maximum gap size among m +1 of the three-region array units having the smallest gap size among the plurality of three-region array units is an estimated maximum value of the depletion layer width.

Specifically, in fig. 3, the input region 102 of the three-region array unit 100 is connected to the drain region of the MOS transistor 200, and the input voltage of the total input terminal of the WAT test structure is simultaneously used as the MOS transistor input voltage. In other embodiments of the present invention, the input region and the drain region of the MOS transistor may be further connected to different input voltage sources. Assuming that the saturation current of the MOS transistor 200 is 5mA, if the current output signal is 20mA, it can be determined that the number of PN junctions between the input region 102 and the base region 104 that have been turned on in the plurality of three-region array units 100 is 4. That is, the PN junctions of the three-region array unit 100, whose values of the spacing dimension D are 1 μm, 1.1 μm, 1.2 μm, and 1.3 μm in this order, are turned on, and the actual width of the depletion layer ranges from 1.3 μm to 1.4 μm. In the NPN structure in this embodiment, the conduction of the reverse PN junction depends on the breakdown thereof, and the breakdown of the PN junction is related to not only the electric field strength but also the width of the space charge region, and under the same voltage condition, the depletion layer width in the reverse PN junction of the three-region array unit 100 has reached its interval dimension D, such as 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, which is smaller than the interval dimension D, so that the reverse PN junction of the other three-region array unit is conducted, whereas in the three-region array unit 100 with the interval dimension D of 1.4 μm, the depletion layer width has not reached its interval dimension D, and the reverse PN junction is not conducted, which indicates that the depletion layer width is smaller than 1.4 μm, and therefore, the actual depletion layer width ranges from 1.3 μm to 1.4 μm. It should be noted that, in this embodiment, the voltage detection array unit is the MOS transistor 200, and it can provide a corresponding current output signal according to the corresponding change of the voltage input signal with different space sizes, that is, in this embodiment, the MOS transistor 200 corresponding to the three-region array unit 100 that meets the condition that the depletion layer width reaches the space size D will output a saturation current signal, and the MOS transistors 200 corresponding to the other three-region array units 100 will not output a current signal. In other embodiments of the present invention, the voltage detection array unit may also select other possible device structures, and provide corresponding current output signals according to the corresponding changes of the voltage input signals with different granularity.

As an example, as shown in fig. 2, the three-region array unit 100 is prepared on a semiconductor substrate 101, and the three-region array unit 100 is connected to the voltage detection array unit through a via structure 105; a heavily doped region 106 of the first doping type is also formed between the input region 102 and the via structure 105, and between the output region 103 and the via structure 105. Optionally, a local oxidation of silicon isolation 107(LOCOS) is further formed in the area around the input region 102 and the output region 103, and the via structure 105 is formed in an interlayer dielectric layer 108. In this embodiment, the three-region array unit 100 and the MOS transistor 200 may be integrated on the same semiconductor substrate 101. In other embodiments of the present invention, a voltage regulator tube may be connected in parallel between the gate of the MOS transistor and the output region, so that the voltage of the input region may be adjusted to meet the requirement of continuous reading; the WAT test structure may be continuously scaled at continuously varying voltages to further analyze structural characteristics.

Example two

The present embodiment provides a WAT test structure, which is different from the first embodiment in that input regions of the three-region array units are connected to drain regions or source regions of the MOS transistors, input regions of a plurality of the three-region array units are connected to serve as a total input end of the WAT test structure, source regions or drain regions of a plurality of the MOS transistors are connected to serve as a total output end of the WAT test structure, and a MOS transistor switching voltage is applied to gates of the MOS transistors.

In this embodiment, the voltage detection array unit is an MOS transistor, and provides a corresponding current output signal according to a corresponding change of the voltage input signal with different interval sizes. Namely, when the width of the depletion layer reaches the interval dimension D, the MOS transistor corresponding to the three-region array unit outputs a saturation current signal.

Other components and manufacturing methods of the WAT test structure provided in this embodiment are the same as those in the first embodiment, and are not described herein again.

In summary, the present invention provides a WAT test structure and a method, where the WAT test structure includes: a plurality of three-region array units including input and output regions having a first doping type and a base region having a second doping type; the base region separates the input region from the output region, and the input region and the output region of a plurality of three-region array units have different spacing sizes; the input area receives a voltage input signal, and the output area outputs a voltage output signal; the voltage detection array units are in one-to-one correspondence with the three-region array units, and receive the voltage output signals and output corresponding current output signals according to the voltage output signals. The invention judges the number of the three-region array units of the PN junction which is conducted and represents the width range of the depletion layer of the PN junction by arranging the input region and the output region with different interval sizes and applying the same voltage input signal.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A WAT test structure, comprising:

2. The WAT test structure of claim 1, wherein the first doping type is N-type and the second doping type is P-type, or the first doping type is P-type and the second doping type is N-type.

3. A WAT test structure as claimed in claim 1, wherein the maximum of a plurality of different said granularity is the maximum estimate of the depletion layer width of the PN junction between said input region and said base region, and the minimum of a plurality of different said granularity is the minimum estimate of the depletion layer width of the PN junction between said input region and said base region.

4. A WAT test structure according to claim 3, wherein the number of said three-region array elements is n, n is an integer greater than 1, and a plurality of said spacer dimensions are in an arithmetic progression with a tolerance of the difference between the maximum and minimum estimates of said depletion layer width divided by n-1.

5. The WAT test structure of claim 1, wherein the voltage detection array unit is an MOS transistor, a source region and a drain region of the MOS transistor have a first doping type, and a plurality of the MOS transistors correspond to a plurality of the three-region array units one by one.

6. The WAT test structure of claim 5, wherein the output regions of the three-region array units are connected to the gates of the MOS transistors, the input regions of a plurality of the three-region array units are connected to serve as the total input terminal of the WAT test structure, the source regions of a plurality of the MOS transistors are connected to serve as the total output terminal of the WAT test structure, and MOS transistor input voltages are applied to the drain regions of a plurality of the MOS transistors.

7. The WAT test structure of claim 6, wherein the input region of the three-region array unit is connected with the drain region of the MOS transistor, and the input voltage of the total input end of the WAT test structure is simultaneously used as the input voltage of the MOS transistor.

8. The WAT test structure of claim 5, wherein the input regions of the three-region array units are connected with the drain region or the source region of the MOS transistor, the input regions of a plurality of the three-region array units are connected as the total input end of the WAT test structure, the source regions or the drain regions of a plurality of the MOS transistors are connected as the total output end of the WAT test structure, and a MOS transistor switching voltage is applied to the gates of a plurality of the MOS transistors.

9. The WAT test structure of claim 1, wherein the three-region array unit is prepared on a semiconductor substrate, and the three-region array unit is connected with the voltage detection array unit through a through hole structure; heavily doped regions of a first doping type are further formed between the input region and the through hole structure and between the output region and the through hole structure.

10. A WAT test method is characterized by comprising the following steps:

providing a WAT test structure according to any one of claims 1 to 9;

judging the number of the conducted PN junctions between the input region and the base region in the three-region array units to be m according to the current output signal;