CN114882824A - Shift register, display driver and display panel - Google Patents

Abstract

The invention discloses a shift register, a display driver and a display panel. The shift register includes: the trigger writing module is used for writing the trigger signal into the first node according to the first clock signal; the power supply leading-in module is used for writing a first power supply signal into a second node according to a first clock signal; the first output adjusting module is used for adjusting a first output signal of a first output end of the shift register according to the trigger signal of the first node and the first power supply signal of the second node; and the second output adjusting module is used for generating a second output signal of the second output end of the shift register opposite to the first output signal according to the trigger signal of the first node and the first output signal. The technical scheme of the embodiment of the invention realizes that two scanning signals can be output by using one shift register, thereby reducing the frame of the display panel.

Description

Shift register, display driver and display panel

Technical Field

The invention relates to the technical field of display, in particular to a shift register, a display driver and a display panel.

Background

With the development of display technology, the application of display panels is becoming more and more extensive, and the requirements for display panels are also becoming higher and higher. The display panel needs to provide various scanning signals required by pixel display through the shift register, and when the pixel circuit needs different scanning signals, the pixel circuit needs different shift registers to realize the scanning signals, which is not favorable for the narrow-frame design of the display panel.

Disclosure of Invention

The invention provides a shift register, a display driver and a display panel, which can output two scanning signals by using one shift register so as to reduce the frame of the display panel.

According to an aspect of the present invention, there is provided a shift register including:

the trigger writing module is used for writing the trigger signal into the first node according to the first clock signal;

the power supply leading-in module is used for writing a first power supply signal into the second node according to the first clock signal;

a first output adjusting module, configured to adjust a first output signal of a first output end of the shift register according to the trigger signal of the first node and the first power signal of the second node;

and the second output adjusting module is used for generating a second output signal of a second output end of the shift register opposite to the first output signal according to the trigger signal of the first node and the first output signal.

Optionally, the second output adjustment module comprises:

a first end of the first pull-up sub-module is connected to a second power supply signal, a second end of the first pull-up sub-module is electrically connected with the second output end, and a control end of the first pull-up sub-module is electrically connected with the first output end;

a first pull-down sub-module, a first end of which is connected to the first power signal, a second end of which is electrically connected to the second output end, and a control end of which is electrically connected to the first node;

the conduction control signal of the first pull-up sub-module is opposite to the conduction control signal of the first pull-down sub-module.

Optionally, the second output adjustment module comprises:

a first end of the first pull-up sub-module is connected to a second power supply signal, a second end of the first pull-up sub-module is electrically connected with the second output end, and a control end of the first pull-up sub-module is electrically connected with the first node;

a first pull-down sub-module, a first end of which is connected to the first power signal, a second end of which is electrically connected to the second output end, and a control end of which is electrically connected to the first output end;

the conduction control signal of the first pull-up sub-module is opposite to the conduction control signal of the first pull-down sub-module.

Optionally, the first pull-up sub-module includes a first transistor, a first end of the first transistor is a first end of the first pull-up sub-module, a second end of the first transistor is a second end of the first pull-up sub-module, and a control end of the first transistor is a control end of the first pull-up sub-module;

the first pull-down sub-module comprises a second transistor, a first end of the second transistor is a first end of the first pull-down sub-module, a second end of the second transistor is a second end of the first pull-down sub-module, and a control end of the second transistor is a control end of the first pull-down sub-module;

the turn-on control signal of the first transistor is opposite to the turn-on control signal of the second transistor.

Optionally, the shift register further comprises a third transistor;

a first end of the third transistor is electrically connected with the first node, a second end of the third transistor is electrically connected with the trigger writing module, and a control end of the third transistor is connected to the first power supply signal; or the like, or, alternatively,

a first end of the third transistor is electrically connected to the first output adjustment module, a second end of the third transistor is electrically connected to the first node, and a control end of the third transistor is connected to the first power signal.

Optionally, the shift register further comprises:

a first feedback sub-module configured to write the first clock signal to the second node according to the trigger signal of the first node;

a second feedback submodule configured to write a second power signal into the first node according to the first power signal and a second clock signal of the second node.

Optionally, the first output adjustment module comprises:

a first end of the second pull-up sub-module is connected to a second power signal, a second end of the second pull-up sub-module is electrically connected with the first output end, and a control end of the second pull-up sub-module is electrically connected with the second node;

and a first end of the second pull-down submodule is connected with a second clock signal, a second end of the second pull-down submodule is electrically connected with the first output end, and a control end of the second pull-down submodule is electrically connected with the first node.

Optionally, the first output adjustment module further includes a first capacitor and a second capacitor;

a first end of the first capacitor is connected to a second power supply signal, and a second end of the first capacitor is electrically connected with the second node;

the first end of the second capacitor is electrically connected with the first node, and the second end of the second capacitor is electrically connected with the first output end.

According to another aspect of the present invention, there is provided a display driver comprising a plurality of cascaded shift registers according to any one of the embodiments of the present invention;

the trigger signal of the nth stage shift register is provided by the output signal of the first output end of the (n-1) th stage shift register, and n is an integer greater than or equal to 2.

According to another aspect of the present invention, there is provided a display panel including the display driver according to any one of the embodiments of the present invention and a plurality of pixel circuits;

the first output end and the second output end of the shift register are used for providing scanning signals for the corresponding pixel circuits.

Optionally, the pixel circuit includes: the device comprises a driving module, a light-emitting module, a threshold compensation module, a first initialization module and a storage module;

the driving module is used for generating a driving current, and the light-emitting module is used for responding to the driving current;

the storage module is used for maintaining the electric potential of the control end of the driving module;

the threshold compensation module is used for capturing the threshold voltage of the driving module to the control end of the driving module;

the first initialization module is used for initializing the electric potential of the control end of the driving module;

the control end of the first initialization module is electrically connected with the second output end of the corresponding shift register, the first end of the first initialization module is accessed to an initialization signal, and the second end of the first initialization module is electrically connected with the control end of the driving module; the first end of the threshold compensation module is electrically connected with the control end of the driving module, the second end of the threshold compensation module is electrically connected with the first end of the driving module, and the control end of the threshold compensation module is electrically connected with the second output end of the corresponding shift register.

According to the technical scheme of the embodiment of the invention, the shift register comprises a first output adjusting module, a second output adjusting module and a third output adjusting module, wherein the first output adjusting module is used for adjusting a first output signal of a first output end of the shift register according to the potentials of a first node and a second node; the trigger writing module is used for writing a trigger signal into a first node according to a first clock signal; the power supply leading-in module is used for writing a first power supply signal into the second node according to the first clock signal; the second output adjusting module is used for generating a second output signal with the polarity opposite to that of the first output signal according to the potential of the first node and the first output signal, so that the shift register can provide two scanning signals with the polarities opposite to each other, the requirements of the pixel circuit are met, the number of the shift registers is reduced, and the narrow frame design of the display panel is facilitated. The technical scheme of the embodiment of the invention solves the problem that when the pixel circuit needs different scanning signals, different shift registers are needed to realize, which is not beneficial to the narrow frame design of the display panel, and realizes that two kinds of scanning signals can be output by using one shift register, thereby reducing the frame of the display panel.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic circuit diagram of a shift register according to an embodiment of the present invention;

FIG. 2 is a timing diagram of a shift register according to an embodiment of the present invention;

fig. 3 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 4 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 5 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 6 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

FIG. 7 is a timing diagram of another shift register according to an embodiment of the present invention;

fig. 8 is a schematic circuit diagram of another shift register according to an embodiment of the present invention;

fig. 9 is a schematic circuit diagram of a display driver according to an embodiment of the present invention;

fig. 10 is a schematic circuit diagram of a display panel according to an embodiment of the present invention;

fig. 11 is a schematic circuit structure diagram of a pixel circuit according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic circuit diagram of a shift register according to an embodiment of the present invention, and referring to fig. 1, the shift register includes: a trigger write module 102, configured to write a trigger signal SIN into a first node N1 according to a first clock signal SCK 1; a power supply introducing module 103 for writing a first power supply signal VGL into a second node N2 according to the first clock signal SCK 1; a first output adjusting module 101, configured to adjust a first output signal Gout1 at a first output end of the shift register according to the trigger signal SIN at the first node N1 and the first power supply signal VGL at the second node N2; and a second output adjusting module 104, configured to generate a second output signal Gout2 of a second output terminal of the shift register opposite to the first output signal Gout1 according to the trigger signal SIN at the first node N1 and the first output signal Gout 1.

Specifically, the trigger writing module 102 may write the trigger signal SIN input by the trigger signal input terminal into the first node N1 according to the first clock signal SCK1, and the shift register may shift the trigger signal SIN to be output through the first output terminal thereof, that is, the output signal Gout1 of the first output terminal of the shift register is the shift signal of the trigger signal SIN. The first output regulating module 101 can output the second power signal VGH or the second clock signal SCK2, for example, when the potential of the first node N1 enables the first output regulating module 101, the first output terminal of the shift register outputs the second clock signal SCK 2; when the potential at the second node N2 enables the first output adjustment module 101, the first output terminal of the shift register outputs a second power signal VGH; the potential of the first node N1 is controlled by the trigger writing module 102, that is, the trigger signal SIN is written into the first node N1 under the control of the first clock signal SCK 1; the first clock signal SCK1 and the second clock signal SCK2 may be inverse signals, that is, when the first clock signal SCK1 is at a low level, the second clock signal SCK2 is at a high level, and when the first clock signal SCK1 is at a high level, the second clock signal SCK2 is at a low level; the second node N2 is controlled by the power introducing module 103, the power introducing module 103 writes the first power signal VGL into the second node N2 under the control of the first clock signal SCK1, the first power signal VGL and the second power signal VGH are opposite signals, for example, the first power signal VGL is at a low level, and the second power signal VGH is at a high level; through the cooperative control of the first clock signal SCK1 and the second clock signal SCK2, the first output signal Gout1 at the first output end of the shift register shifts relative to the trigger signal SIN; the first output signal Gout1 at the first output terminal of the shift register can be used as a scanning signal for pixels in the display panel. The second output regulation module 104 may also be controlled by the potential of the first node N1 and the first output signal Gout1, such that the second output regulation module 104 is capable of outputting the first power supply signal VGL or the second power supply signal VGH; for example, when the potential of the first node N1 enables the second output regulation module 104, the second output regulation module 104 outputs the first power signal VGL, i.e., the second output signal Gout2 output by the second output terminal of the shift register is the first power signal VGL; when the first output signal Gout1 enables the second output regulation module 104, the second output regulation module 104 outputs the second power supply signal VGH, that is, the second output signal Gout2 output by the second output terminal of the shift register is the second power supply signal VGH; the second output signal Gout2 of the second output terminal of the shift register can be used as a scanning signal of the pixels in the display panel.

In this embodiment, the second output signal Gout2 at the second output terminal of the shift register is adjustable according to the first output signal Gout1, and when the first output signal Gout1 is at a high level, the second output signal Gout2 at the second output terminal of the shift register is at a low level; when the first output signal Gout1 is at a low level, the second output signal Gout2 at the second output terminal of the shift register is at a high level, that is, the polarity of the second output signal Gout2 at the second output terminal of the shift register is opposite to that of the first output signal Gout1, so that the shift register can provide two scan signals with opposite polarities, thereby meeting the requirements of the pixel circuits, reducing the number of the shift registers, and being beneficial to the narrow-frame design of the display panel.

In addition, by controlling the second output regulation module 104 using the first node N1 and the first output signal Gout1, the load of the first output terminal can be reduced, and distortion of the first output signal Gout1 can be avoided, thereby ensuring accuracy of the first output signal Gout 1.

Fig. 2 is a timing diagram of a shift register according to an embodiment of the present invention, which may correspond to the shift register shown in fig. 1, and referring to fig. 1 and fig. 2, in this embodiment, for example, the first output adjusting module 101, the trigger writing module 102, and the power introducing module 103 are turned on at a low level and turned off at a high level; the second output adjusting module 104 may output different signals according to the high and low levels; the working process of the shift register can comprise six stages from t1 to t 6:

at the stage t1, the trigger signal SIN is at a low level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level; the trigger writing module 102 is turned on, and writes the trigger signal SIN into the first node N1, the potential of the first node N1 is at a low level, and the potential of the first node N1 enables the first output adjustment module 101 to output the second clock signal SCK 2; the power supply introducing module 103 is turned on, the first power supply signal VGL is written into the second node N2, the potential of the second node N2 is at a low level, and the potential of the second node N2 enables the first output regulating module 101 to output the second power supply signal VGH, that is, the first output signal Gout1 is at a high level; the first output signal Gout1 or the potential of the first node N1 enables the second output regulation module 104 to output the first power signal VGL, i.e., the second output signal Gout2 is at a low level;

at the stage t2, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level; the write trigger block 102 and the power supply introduction block 103 are triggered to turn off, the first node N1 maintains a low level, and the potential of the first node N1 enables the first output regulating block 101 to output the second clock signal SCK2, that is, the first output signal Gout1 is at a low level; the first output signal Gout1 or the potential of the first node N1 enables the second output regulation module 104 to output the second power signal VGH, i.e., the second output signal Gout2 is at a high level;

at the stage t3, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level; the power supply introducing module 103 is turned on to write the first power supply signal VGL into the second node N2, the potential of the second node N2 is at a low level, and the potential of the second node N2 enables the first output regulating module 101 to output the second power supply signal VGH, i.e., the first output signal Gout1 is at a high level; the trigger writing module 102 is turned on, the trigger signal SIN is written into the first node N1, the potential of the first node N1 is at a high level, and the potential of the first node N1 or the first output signal Gout1 enables the second output adjustment module 104 to output the first power signal VGL, that is, the second output signal Gout2 is at a low level;

at the stage t4, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level; the trigger write module 102 and the power supply introduction module 103 are turned off, the first node N1 maintains a high level, the second node N2 maintains a low level, and the potential of the second node N2 enables the first output regulation module 101 to output the second power supply signal VGH, i.e., the first output signal Gout1 is at a high level; the potential of the first node N1 or the first output signal Gout1 enables the second output regulating module 104 to output the first power signal VGL, i.e., the second output signal Gout2 is at a low level;

at the stage t5, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level; the power supply introducing module 103 is turned on to write the first power supply signal VGL into the second node N2, the potential of the second node N2 is at a low level, and the potential of the second node N2 enables the first output regulating module 101 to output the second power supply signal VGH, i.e., the first output signal Gout1 is at a high level; the trigger writing module 102 is turned on, the trigger signal SIN is written into the first node N1, the potential of the first node N1 is at a high level, and the potential of the first node N1 or the first output signal Gout1 enables the second output adjustment module 104 to output the first power signal VGL, that is, the second output signal Gout2 is at a low level;

at the stage t6, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level; the trigger write module 102 and the power supply introduction module 103 are turned off, the first node N1 maintains a high level, the second node N2 maintains a low level, and the potential of the second node N2 enables the first output regulation module 101 to output the second power supply signal VGH, i.e., the first output signal Gout1 is at a high level; the potential of the first node N1 or the first output signal Gout1 enables the second output regulating module 104 to output the first power signal VGL, i.e., the second output signal Gout2 is at a low level.

Therefore, the polarities of the first output signal Gout1 and the second output signal Gout2 are opposite, that is, the shift register can output two different scanning signals, so that the requirements of the pixel circuit in the display panel on different scanning signals can be met, the number of the shift register can be reduced, and the reduction of the frame of the display panel is facilitated.

In the technical solution of this embodiment, the shift register includes a first output adjustment module, configured to adjust a first output signal of a first output terminal of the shift register according to potentials of a first node and a second node; the trigger writing module is used for writing the trigger signal into the first node according to the first clock signal; the power supply leading-in module is used for writing a first power supply signal into the second node according to the first clock signal; the second output adjusting module is used for generating a second output signal with the polarity opposite to that of the first output signal according to the potential of the first node and the first output signal, so that the shift register can provide two scanning signals with the polarities opposite to each other, the requirements of the pixel circuit are met, the number of the shift registers is reduced, and the narrow frame design of the display panel is facilitated. The technical scheme of the embodiment solves the problem that when the pixel circuit needs different scanning signals, different shift registers are needed to realize, and the narrow frame design of the display panel is not facilitated, and the purpose that two kinds of scanning signals can be output by using one kind of shift register is achieved, so that the frame of the display panel is reduced.

Fig. 3 is a schematic circuit diagram of another shift register according to an embodiment of the present invention, and optionally, referring to fig. 3, the second output adjusting module 104 includes: a first pull-up sub-module 1041, a first end of the first pull-up sub-module 1041 is connected to the second power signal VGH, a second end of the first pull-up sub-module 1041 is electrically connected to the second output end, and a control end of the first pull-up sub-module 1041 is electrically connected to the first output end; a first pull-down sub-module 1042, wherein a first end of the first pull-down sub-module 1042 is connected to a first power signal VGL, a second end of the first pull-down sub-module 1042 is electrically connected to a second output end, and a control end of the first pull-down sub-module 1042 is electrically connected to a first node N1; the turn-on control signal of the first pull-up sub-module 1041 is opposite to the turn-on control signal of the first pull-down sub-module 1042.

Specifically, the first pull-up sub-module 1041 and the first pull-down sub-module 1042 are turned on in response to control signals with different polarities, that is, when the first pull-up sub-module 1041 is turned on, the first pull-down sub-module 1042 is turned off; when the first pull-up sub-module 1041 is turned off, the first pull-down sub-module 1042 is turned on; for example, when the first output signal Gout1 is at a low level, the first pull-up sub-block 1041 is turned on, and the first pull-up sub-block 1041 outputs the second power signal VGH, that is, the second output signal Gout2 is at a high level; when the voltage level of the first node N1 is high, the first pull-down sub-module 1042 is turned on, and the first pull-down sub-module 1042 outputs the first power signal VGL, i.e., the second output signal Gout2 is low.

Alternatively, fig. 4 is a schematic circuit structure diagram of another shift register provided in an embodiment of the present invention, and optionally, referring to fig. 4, the second output adjusting module 104 includes: a first end of the first pull-up sub-module 1041 is connected to the second power signal VGH, a second end of the first pull-up sub-module 1041 is electrically connected to the second output end, and a control end of the first pull-up sub-module 1041 is electrically connected to the first node N1; a first pull-down sub-module 1042, wherein a first end of the first pull-down sub-module 1042 is connected to a first power signal VGL, a second end of the first pull-down sub-module 1042 is electrically connected to a second output end, and a control end of the first pull-down sub-module 1042 is electrically connected to the first output end; the turn-on control signal of the first pull-up sub-module 1041 is opposite to the turn-on control signal of the first pull-down sub-module 1042.

Specifically, the first pull-up sub-module 1041 and the first pull-down sub-module 1042 are turned on in response to control signals with different polarities, that is, when the first pull-up sub-module 1041 is turned on, the first pull-down sub-module 1042 is turned off; when the first pull-up sub-module 1041 is turned off, the first pull-down sub-module 1042 is turned on; for example, when the first output signal Gout1 is at a high level, the first pull-down sub-module 1042 is turned on, and the first pull-down sub-module 1042 outputs the first power signal VGL, that is, the second output signal Gout2 is at a low level; when the voltage level of the first node N1 is low, the first pull-up sub-module 1041 is turned on, and the first pull-up sub-module 1041 outputs the second power signal VGH, i.e. the second output signal Gout2 is high.

Fig. 5 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, optionally, referring to fig. 5, the first pull-up sub-module 1041 includes a first transistor M1, a first end of the first transistor M1 is a first end of the first pull-up sub-module 1041, a second end of the first transistor M1 is a second end of the first pull-up sub-module 1041, and a control end of the first transistor M1 is a control end of the first pull-up sub-module 1041; the first pull-down sub-module 1042 includes a second transistor M2, a first end of the second transistor M2 is a first end of the first pull-down sub-module 1042, a second end of the second transistor M2 is a second end of the first pull-down sub-module 1042, and a control end of the second transistor M2 is a control end of the first pull-down sub-module 1042; the turn-on control signal of the first transistor M1 is opposite to the turn-on control signal of the second transistor M2.

Specifically, the first transistor M1 is of a different type from the second transistor M2, for example, the first transistor M1 is a P-type transistor, the second transistor M2 is an N-type transistor, when the potential of the first node N1 is at a high level, the second transistor M2 is turned on, the second transistor M2 outputs the first power signal VGL, that is, the second output signal Gout2 at the second output terminal is at a low level; when the first output signal Gout1 is at a low level, the first transistor M1 is turned on, and the first transistor M1 outputs the second power supply signal VGH, i.e., the second output signal Gout2 at the second output terminal is at a high level, so that the polarities of the first output signal Gout1 and the second output signal Gout2 are opposite.

Optionally, the shift register further comprises a third transistor M3; a first end N11 of the third transistor M3 is electrically connected to the first node N1, a second end N12 of the third transistor M3 is electrically connected to the trigger writing module 102, and a control end of the third transistor M3 is connected to the first power signal VGL; or, the first end N11 of the third transistor M3 is electrically connected to the first output adjustment module 101, the second end N12 of the third transistor M3 is electrically connected to the first node N1, and the control end of the third transistor M3 is connected to the first power signal VGL.

Specifically, with reference to fig. 5, the second output adjustment module 104 is electrically connected to the first end N11 of the third transistor M3, the third transistor M3 is, for example, a P-type transistor, and the control end of the third transistor M3 is connected to the first power signal VGL, so the third transistor M3 is always in a conducting state. For example, when the trigger writing module 102 is turned on, the trigger signal SIN is written into the second end N12 of the third transistor M3, and when the trigger signal SIN is at a low level, the second end N12 of the third transistor M3 is at a low level, the first end N11 of the third transistor M3 is also at a low level, the second transistor M2 is turned off, and the second output adjustment module 104 maintains the signal output of the previous frame; when the trigger signal SIN is at a high level, the second terminal N12 of the third transistor M3 is at a high level, the first terminal N11 of the third transistor M3 is at a high level, the second transistor M2 is turned on, and the second output adjustment module 104 outputs the first power signal VGL, i.e., the second output signal Gout2 at the second output terminal of the shift register is at a low level, so as to adjust the second output signal Gout2 at the second output terminal of the shift register.

Alternatively, fig. 6 is a schematic circuit structure diagram of another shift register according to an embodiment of the present invention, referring to fig. 6, the second output adjustment module 104 is electrically connected to the second end N12 of the third transistor M3, the third transistor M3 is, for example, a P-type transistor, and the control end of the third transistor M3 is connected to the first power signal VGL, so that the third transistor M3 is always in an on state. For example, when the trigger writing module 102 is turned on, the trigger signal SIN is written into the second end N12 of the third transistor M3, and when the trigger signal SIN is at a low level, the second end N12 of the third transistor M3 is at a low level, the second transistor M2 is turned off, and the second output adjustment module 104 maintains the signal output of the previous frame; when the trigger signal SIN is at a high level, the second terminal N12 of the third transistor M3 is at a high level, the second transistor M2 is turned on, and the second output adjustment module 104 outputs the first power signal VGL, i.e., the second output signal Gout2 at the second output terminal of the shift register is at a low level, so as to adjust the second output signal Gout2 at the second output terminal of the shift register.

Optionally, with continued reference to fig. 5, the shift register further comprises: the first feedback submodule is used for writing a first clock signal SCK1 into a second node N2 according to a trigger signal SIN of a first node N1; and a second feedback sub-module for writing the second power signal VGH into the first node N1 according to the first power signal VGL and the second clock signal SCK2 at the second node N2.

Illustratively, the first feedback sub-module includes a fourth transistor M4, a first terminal of the fourth transistor M4 is connected to the first clock signal SCK1, a second terminal of the fourth transistor M4 is electrically connected to the second node N2, and a control terminal of the fourth transistor M4 is electrically connected to the first node N1; the second feedback sub-module comprises a fifth transistor M5 and a sixth transistor M6, a first end of the fifth transistor M5 is connected to the second power supply signal VGH, a second end of the fifth transistor M5 is electrically connected to a first end of the sixth transistor M6, and a control end of the fifth transistor M5 is electrically connected to the second node N2; a second terminal of the sixth transistor M6 is electrically connected to the first node N1, and a control terminal of the sixth transistor M6 is coupled to the second clock signal SCK 2. The first feedback module can feedback-control the second node N2 according to the potential of the first node N1, so that when the second clock signal SCK2 is at a low level and the second pull-down submodule of the first output adjusting module 101 is turned on, the second pull-up submodule of the first output adjusting module 101 is in an off state, the first output end of the shift register is prevented from outputting a high level and a low level at the same time, and the unstable state of Gout1 is also prevented from being discovered; the second feedback module can feedback control the potential of the first node N1 according to the potential of the second node N2, so that the second clock signal SCK2 is at a low level, and when the second node N2 is at a low level, the first node N1 is controlled to be at a high level, so that the first output end of the shift register is prevented from outputting a high level and a low level at the same time, that is, the Gout1 is prevented from being unstable.

Optionally, with continued reference to fig. 5, the first output adjustment module 101 comprises: a first end of the first pull-up sub-module is connected with a first power supply signal, a second end of the first pull-up sub-module is electrically connected with the first output end, and a control end of the first pull-up sub-module is electrically connected with a first node; and a first end of the second pull-down submodule is connected with a second clock signal, a second end of the second pull-down submodule is electrically connected with the first output end, and a control end of the second pull-down submodule is electrically connected with the first node.

Illustratively, the second pull-up sub-module includes a seventh transistor M7, the first terminal of the seventh transistor M7 is the first terminal of the second pull-up sub-module, the second terminal of the seventh transistor M7 is the second terminal of the second pull-up sub-module, and the control terminal of the seventh transistor M7 is the control terminal of the second pull-up sub-module. The second pull-down sub-module includes an eighth transistor M8, a first terminal of the eighth transistor M8 is a first terminal of the second pull-down sub-module, a second terminal of the eighth transistor M8 is a second terminal of the second pull-down sub-module, and a control terminal of the eighth transistor M8 is a control terminal of the second pull-down sub-module. The seventh transistor M7 and the eighth transistor M8 are, for example, P-type transistors, and in some other embodiments, the seventh transistor M7 and the eighth transistor M8 may also be other types of transistors, which is not limited herein.

Specifically, when the trigger writing module 102 is turned on, the trigger signal SIN is written into the first node N1, and when the trigger signal SIN is at a low level, the potential of the first node N1 is at a low level, the eighth transistor M8 is turned on, and the eighth transistor M8 outputs the second clock signal SCK2, that is, the first output end outputs the second clock signal SCK 2; when the power supply introducing module 103 is turned on, the first power supply signal VGL is written into the second node N2, so that the seventh transistor M7 is turned on, and the seventh transistor M7 outputs the second power supply signal VGH, that is, the first output signal Gout1 output by the first output terminal is at a high level, thereby implementing the adjustment of the first output signal Gout1 at the first output terminal of the shift register.

Optionally, with continued reference to fig. 5, the first output adjusting module 101 further includes a first capacitor C1 and a second capacitor C2, a first end of the first capacitor C1 is connected to the second power signal VGH, and a second end of the first capacitor C1 is electrically connected to the second node N2; a first terminal of the second capacitor C2 is electrically connected to the first node N1, and a second terminal of the second capacitor C2 is electrically connected to the first output terminal.

Specifically, the first capacitor C1 has an energy storage function, and can maintain the potential of the second node N2; the second capacitor C2 has energy storage function and can be the potential of the first node N1; the second capacitor C2 has a bootstrap function, for example, in the previous stage, the second end of the second capacitor C2 is at the voltage VGH, and the first end of the second capacitor C2 is at the voltage VGL + Vth; at the present stage, the second terminal of the second capacitor C2 is at a low level, the voltage is reduced, and due to the bootstrap effect of the second capacitor C2, the second capacitor C2 will keep the voltage difference between the two terminals unchanged, and the first terminal N11 of the second capacitor C2 is at an ultra-low level, so that the node N11 is at an ultra-low level.

Optionally, with continued reference to fig. 5, the toggle writing module 102 includes a ninth transistor M9, a first terminal of the ninth transistor M9 is a first terminal of the toggle writing module 102, a second terminal of the ninth transistor M9 is a second terminal of the toggle writing module 102, and a control terminal of the ninth transistor M9 is a control terminal of the toggle writing module 102. The power supply leading-in module 103 comprises a tenth transistor M10, a first terminal of the tenth transistor M10 is a first terminal of the power supply leading-in module 103, a second terminal of the tenth transistor M10 is a second terminal of the power supply leading-in module 103, and a control terminal of the tenth transistor M10 is a control terminal of the power supply leading-in module 103.

Fig. 7 is a timing diagram of another shift register according to an embodiment of the present invention, and referring to fig. 5 and 7, the second transistor M2 is, for example, an N-type transistor, and is turned on at a high level and turned off at a low level; the rest transistors in the shift register are P-type transistors, for example, and the low level is turned on and the high level is turned off; the working process of the shift register can comprise six stages from t1 to t 6:

at the stage t1, the trigger signal SIN is at a low level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level; the ninth transistor M9 and the tenth transistor M10 are turned on, the ninth transistor M9 writes the trigger signal SIN to the second end N12 of the third transistor M3, the second end N12 of the third transistor M3 is at a low level VGL + Vth, and Vth is a threshold voltage of the ninth transistor M9; the third transistor M3 is turned on, and the first end N11 of the third transistor M3 is at a low level VGL + Vth; the potential of the node N11 makes the eighth transistor M8 turned on, and the eighth transistor M8 outputs the second clock signal SCK2, that is, the first output signal Gout1 of the first output terminal is VGH. The tenth transistor M10 writes the first power signal VGL into the second node N2, the potential of the second node N2 is VGL + Vth, and Vth is the threshold voltage of the tenth transistor M10; the potential of the second node N2 makes the seventh transistor M7 turn on, and the seventh transistor M7 outputs the second power supply signal VGH, i.e., the first output signal Gout1 of the first output terminal is equal to VGH. The potential of the node N11 cannot turn on the second transistor M2, and the first output signal Gout1 cannot turn on the first transistor M1, so that the second output signal Gout2 maintains the second output signal of the previous frame.

At the stage t2, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level; the ninth transistor M9 and the tenth transistor M10 are turned off, and the second terminal N12 of the third transistor M3 maintains the low level VGL + Vth; when the third transistor M3 is turned on, the first terminal N11 of the third transistor M3 is at a low level, the potential of the node N11 makes the eighth transistor M8 turned on, and the eighth transistor M8 outputs the second clock signal SCK2, that is, the first output signal Gout1 is VGL; the potential of the second end of the second capacitor C2 is VGH in the previous stage, the potential of the first end of the second capacitor C2 is VGL + Vth, the second end of the second capacitor C2 is at a low level in this stage, the voltage is reduced, and due to the bootstrap effect of the second capacitor C2, the voltage difference between the two ends of the second capacitor C2 is kept unchanged, so the first end N11 of the second capacitor C2 is at an ultra-low level, that is, the node N11 is at an ultra-low level; the node N12 makes the fourth transistor M4 turned on, the fourth transistor M4 writes the first clock signal SCK1 into the second node N2, so that the second node N2 is at a high level VGH, and the seventh transistor is turned off. The potential of the node N11 causes the first transistor M1 to turn off; the first output signal Gout1 makes the first transistor M1 turned on, and the first transistor M1 outputs the second power supply signal VGH, that is, the second output signal Gout2 is VGH; thereby causing the second output signal Gout2 to be of opposite polarity to the first output signal Gout 1.

Alternatively, fig. 8 is a schematic circuit structure diagram of another shift register provided by an embodiment of the invention, referring to fig. 8, the control terminal of the first pull-up sub-module 1041 in the second output adjusting module 104 is electrically connected to the first terminal N11 of the third transistor M3, that is, the control terminal of the first transistor M1 is electrically connected to the first terminal N11 of the third transistor M3, when the first terminal N11 of the third transistor M3 is at an ultra-low potential, the first transistor M1 may be turned on more fully, so that the second output signal Gout2 output by the first transistor M1 better meets the requirement of the scan signal.

At the stage t3, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level; the tenth transistor M10 is turned on, the tenth transistor M10 writes the first power supply signal VGL into the second node N2, the potential of the second node N2 is low VGL + Vth, the potential of the second node N2 turns on the seventh transistor M7, and the seventh transistor M7 outputs the second power supply signal VGH, that is, the first output signal Gout1 ═ VGH; the ninth transistor M9 is turned on, the trigger signal SIN is written into the second end N12 of the third transistor M3, the second end N12 of the third transistor M3 is at a high level VGH, and the third transistor M3 is turned on, so the first end N11 of the third transistor M3 is at a high level VGH; the potential of the node N11 turns on the second transistor M2, and the second transistor M2 outputs the first power signal VGL, that is, the second output signal Gout2 is VGL; thereby causing the second output signal Gout2 to be of opposite polarity to the first output signal Gout 1.

At the stage t4, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level; the ninth transistor M9 and the tenth transistor M10 are turned off, the potentials of the node N11 and the node N12 maintain the high level VGH, and the potential of the second node N2 maintains the low level VGL + Vth; the potential of the second node N2 turns on the seventh transistor M7, and the seventh transistor M7 outputs the second power signal VGH, i.e., the first output signal Gout1 is VGH; the potential of the node N11 turns on the second transistor M2, and the second transistor M2 outputs the first power signal VGL, that is, the second output signal Gout2 is VGL; thereby causing the second output signal Gout2 to be of opposite polarity to the first output signal Gout 1.

At the stage t5, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a low level, and the second clock signal SCK2 is at a high level; the tenth transistor M10 is turned on, the tenth transistor M10 writes the first power supply signal VGL into the second node N2, the potential of the second node N2 is low VGL + Vth, the potential of the second node N2 turns on the seventh transistor M7, and the seventh transistor M7 outputs the second power supply signal VGH, that is, the first output signal Gout1 ═ VGH; the ninth transistor M9 is turned on, the trigger signal SIN is written into the second end N12 of the third transistor M3, the second end N12 of the third transistor M3 is at a high level VGH, and the third transistor M3 is turned on, so the first end N11 of the third transistor M3 is at a high level VGH; the potential of the node N11 turns on the second transistor M2, and the second transistor M2 outputs the first power signal VGL, that is, the second output signal Gout2 is VGL; thereby causing the second output signal Gout2 to be of opposite polarity to the first output signal Gout 1.

At stage t6, the trigger signal SIN is at a high level, the first clock signal SCK1 is at a high level, and the second clock signal SCK2 is at a low level; the ninth transistor M9 and the tenth transistor M10 are turned off, the potentials of the node N11 and the node N12 maintain the high level VGH, and the potential of the second node N2 maintains the low level VGL + Vth; the potential of the second node N2 turns on the seventh transistor M7, and the seventh transistor M7 outputs the second power signal VGH, i.e., the first output signal Gout1 is VGH; the potential of the node N11 turns on the second transistor M2, and the second transistor M2 outputs the first power supply signal VGL, that is, the second output signal Gout2 is equal to VGL; thereby causing the second output signal Gout2 to be of opposite polarity to the first output signal Gout 1.

In addition, referring to fig. 6, the control terminal of the second transistor M2 is electrically connected to the second terminal N12 of the third transistor M3, so that when the first terminal N11 of the third transistor M3 is at an ultra-low level, the voltage difference between the gate and the source of the second transistor M2 is too large, which may damage the second transistor M2.

Fig. 9 is a schematic circuit diagram of a display driver according to an embodiment of the present invention, and referring to fig. 9, the display driver 201 includes a plurality of cascaded shift registers 2011, and the shift registers 2011 are provided in any embodiment of the present invention; the trigger signal SIN of the nth stage shift register is provided by the output signal SCK1 at the first output terminal of the (n-1) th stage shift register, where n is greater than or equal to 2.

Specifically, the display driver 201 can be applied to a display panel to provide a scan signal for a pixel circuit in the display panel, and has the same beneficial effects because it includes the shift register provided in any embodiment of the present invention, and is not described herein again. The display driver 201 may be disposed at a frame position of the display panel, and preferably, the display panel may include two display drivers 201 disposed at two sides of the display panel, respectively, so as to reduce a voltage drop on the data lines in the display area of the display panel and improve display uniformity.

Illustratively, a first clock signal of the m-th row of pixel circuits is connected with a first clock signal input end of the m-th stage shift register, and a second clock signal of the m-th row of pixel circuits is connected with a second clock signal input end of the m-th stage shift register; the first clock signal of the m +1 row of pixel circuits is connected with the second clock signal input end of the m +1 level shift register, and the second clock signal of the m +1 row of pixel circuits is connected with the first clock signal input end of the m-1 level shift register; the shift register is convenient to shift and output the trigger signal. Wherein m is a positive integer greater than or equal to 1, and m is an odd number.

Fig. 10 is a schematic circuit structure diagram of a display panel according to an embodiment of the present invention, and referring to fig. 10, the display panel includes a display driver 201 and a plurality of pixel circuits PX according to any embodiment of the present invention; the first output terminal and the second output terminal of the shift register 2011 are used for providing scan signals to the corresponding pixel circuits.

Specifically, the display panel may include a display area and a non-display area, and the display area may include a plurality of data lines and scan lines staggered horizontally and vertically to define an area of the pixel circuit; the display panel may be, for example, a display panel on a mobile phone, a tablet, an MP3, an MP4, a smart watch, a smart helmet, or other wearable devices, and therefore, the display panel includes the display driver provided in any embodiment of the present invention, and therefore, the same advantageous effects are also provided, and further description is omitted here.

Illustratively, the pixel circuit includes: the device comprises a driving module, a light-emitting module, a threshold compensation module, a first initialization module and a storage module; the driving module is used for generating a driving current, and the light-emitting module is used for responding to the driving current to emit light; the storage module is used for maintaining the electric potential of the control end of the driving module; the threshold compensation module is used for capturing the threshold voltage of the driving module to the control end of the driving module; the first initialization module is used for initializing the electric potential of the control end of the driving module; the control end of the first initialization module is electrically connected with the second output end of the corresponding shift register, the first end of the first initialization module is connected with an initialization signal Vref, and the second end of the first initialization module is electrically connected with the control end of the driving module; the first end of the threshold compensation module is electrically connected with the control end of the driving module, the second end of the threshold compensation module is electrically connected with the first end of the driving module, and the control end of the threshold compensation module is electrically connected with the second output end of the corresponding shift register.

Specifically, fig. 11 is a schematic circuit structure diagram of a pixel circuit according to an embodiment of the present invention, and as shown in fig. 11, the driving module includes an eleventh transistor M11; the pixel circuit further includes a data write module including a twelfth transistor M12, the threshold compensation module including a thirteenth transistor M13; the pixel circuit further comprises a first light-emitting control module and a second light-emitting control module, wherein the first light-emitting control module comprises a fourteenth transistor M14, the second light-emitting control module comprises a fifteenth transistor M15, the pixel circuit further comprises a second initialization module, the second initialization module comprises a sixteenth transistor M16, and the first initialization module comprises a seventeenth transistor M17; the memory module comprises a third capacitance C3; an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17 and a third capacitor C3 are connected to form the structure shown in fig. 11; a control end of a twelfth transistor M12 in the pixel circuit of the nth row is electrically connected with a first output end of the shift register of the nth stage, and a control end of a thirteenth transistor M13 in the pixel circuit of the nth row is electrically connected with a second output end of the shift register of the nth stage; the control end of a seventeenth transistor M17 in the pixel circuit of the nth row is electrically connected with the second output end of the shift register of the (n-1) th stage; and the control end of a sixteenth transistor in the pixel circuit of the nth row is electrically connected with the first output end of the (n-1) th-stage shift register. The eleventh transistor M11, the twelfth transistor M12, the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16 may be P-type Low Temperature Polysilicon (LTPS) transistors, and the thirteenth transistor M13 and the seventeenth transistor M17 may be oxide thin film transistors, for example, IGZO, so as to reduce the leakage phenomenon at the control end of the driving module and improve the stability. In the present embodiment, the thirteenth transistor M13 and the seventeenth transistor M17 are turned on when the control terminals thereof are at a high level, and the remaining transistors are turned on when the control terminals thereof are at a low level; the driving process of the pixel circuit comprises an initialization stage, a threshold compensation stage and a light emitting stage, wherein in the initialization stage, the sixteenth transistor M16 and the seventeenth transistor M17 are switched on, and the sixteenth transistor M16 initializes the light emitting module by adopting an initialization signal Vref, so that the influence of a previous frame signal on the light emission of the frame is prevented; the seventeenth transistor M17 initializes the control terminal of the eleventh transistor M11 with the initialization signal Vref; in the threshold compensation phase, the thirteenth transistor M13 is turned on, the twelfth transistor M12 is turned on, the Data signal Data is written into the control terminal of the eleventh transistor M11 through the twelfth transistor M12, the thirteenth transistor M13 and the eleventh transistor M11 until the eleventh transistor M11 is turned off, and the Data signal Data is used for capturing the threshold voltage of the eleventh transistor M11 in the process; in the light emitting period, the fourteenth transistor M14, the eleventh transistor M11 and the fifteenth transistor M15 are turned on, and the light emitting module emits light in response to the driving current of the driving module under the coordination of the first level signal VDD and the second level signal VSS, and the driving current is independent of the threshold voltage of the driving module. As can be seen from the above driving process, in the initialization stage, the seventeenth transistor M17 and the sixteenth transistor M16 need to be turned on, the seventeenth transistor M17 needs to be turned on at a high level, the sixteenth transistor M16 needs to be turned on at a low level, in the threshold compensation stage, the thirteenth transistor M13 needs to be turned on, the turn-on level of the thirteenth transistor M12 is high, and the turn-on level of the twelfth transistor M12 is low; that is, the pixel circuit needs two different types of scan signals, which can be understood as scan signals with different polarities, i.e., one of the scan signals cannot be obtained by shifting the other scan signal; the shift register provided by this embodiment can provide scan signals for the thirteenth transistor M13 and the seventeenth transistor M17, and can also provide scan signals for the twelfth transistor M12 and the sixteenth transistor M16, which can meet the driving requirements of the pixel circuit in the display panel that require multiple scan signals; and the number of components and signal lines required by the shift register is small, so that the frame of the display panel is reduced.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A shift register, comprising:

the trigger writing module is used for writing the trigger signal into the first node according to the first clock signal;

the power supply leading-in module is used for writing a first power supply signal into the second node according to the first clock signal;

a first output adjusting module, configured to adjust a first output signal of a first output end of the shift register according to the trigger signal of the first node and the first power signal of the second node;

and the second output adjusting module is used for generating a second output signal of a second output end of the shift register opposite to the first output signal according to the trigger signal of the first node and the first output signal.

2. The shift register of claim 1, wherein the second output adjustment module comprises:

a first end of the first pull-up sub-module is connected to a second power supply signal, a second end of the first pull-up sub-module is electrically connected with the second output end, and a control end of the first pull-up sub-module is electrically connected with the first output end;

a first pull-down sub-module, a first end of which is connected to the first power signal, a second end of which is electrically connected to the second output end, and a control end of which is electrically connected to the first node;

the conduction control signal of the first pull-up sub-module is opposite to the conduction control signal of the first pull-down sub-module.

3. The shift register of claim 1, wherein the second output adjustment module comprises:

a first end of the first pull-up sub-module is connected to a second power signal, a second end of the first pull-up sub-module is electrically connected with the second output end, and a control end of the first pull-up sub-module is electrically connected with the first node;

a first pull-down sub-module, a first end of which is connected to the first power signal, a second end of which is electrically connected to the second output end, and a control end of which is electrically connected to the first output end;

the conduction control signal of the first pull-up sub-module is opposite to the conduction control signal of the first pull-down sub-module.

4. The shift register according to claim 2 or 3,

the first pull-up sub-module comprises a first transistor, a first end of the first transistor is a first end of the first pull-up sub-module, a second end of the first transistor is a second end of the first pull-up sub-module, and a control end of the first transistor is a control end of the first pull-up sub-module;

the first pull-down sub-module comprises a second transistor, a first end of the second transistor is a first end of the first pull-down sub-module, a second end of the second transistor is a second end of the first pull-down sub-module, and a control end of the second transistor is a control end of the first pull-down sub-module;

the turn-on control signal of the first transistor is opposite to the turn-on control signal of the second transistor.

5. The shift register according to claim 1, further comprising a third transistor;

a first end of the third transistor is electrically connected with the first node, a second end of the third transistor is electrically connected with the trigger writing module, and a control end of the third transistor is connected to the first power supply signal; or the like, or, alternatively,

a first end of the third transistor is electrically connected to the first output adjustment module, a second end of the third transistor is electrically connected to the first node, and a control end of the third transistor is connected to the first power supply signal.

6. The shift register according to claim 1 or 5, further comprising:

a first feedback sub-module for writing the first clock signal to the second node according to the trigger signal of the first node;

a second feedback submodule configured to write a second power signal into the first node according to the first power signal and a second clock signal of the second node.

7. The shift register of claim 1 or 5, wherein the first output adjustment module comprises:

a first end of the second pull-up sub-module is connected to a second power signal, a second end of the second pull-up sub-module is electrically connected with the first output end, and a control end of the second pull-up sub-module is electrically connected with the second node;

and a first end of the second pull-down submodule is connected with a second clock signal, a second end of the second pull-down submodule is electrically connected with the first output end, and a control end of the second pull-down submodule is electrically connected with the first node.

8. The shift register of claim 1 or 5, wherein the first output adjustment module further comprises a first capacitor and a second capacitor;

a first end of the first capacitor is connected to a second power supply signal, and a second end of the first capacitor is electrically connected with the second node;

the first end of the second capacitor is electrically connected with the first node, and the second end of the second capacitor is electrically connected with the first output end.

9. A display driver comprising a plurality of cascaded shift registers according to any of claims 1-8;

the trigger signal of the nth stage shift register is provided by the output signal of the first output end of the (n-1) th stage shift register, and n is an integer greater than or equal to 2.

10. A display panel characterized by comprising the display driver of claim 9 and a plurality of pixel circuits;

the first output end and the second output end of the shift register are used for providing scanning signals for the corresponding pixel circuits.

Images