CN114879084B - System and method for testing efficient leakage current of array diode chip - Google Patents
System and method for testing efficient leakage current of array diode chip Download PDFInfo
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- CN114879084B CN114879084B CN202210797229.7A CN202210797229A CN114879084B CN 114879084 B CN114879084 B CN 114879084B CN 202210797229 A CN202210797229 A CN 202210797229A CN 114879084 B CN114879084 B CN 114879084B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
The invention discloses a system and a method for testing efficient leakage current of an array diode chip, wherein the system comprises an input circuit, a power circuit, a circuit conversion module, a control circuit and an output circuit, wherein the input circuit is used for realizing input and information exchange from a testing machine to a testing board; the power supply circuit provides a power supply circuit required by the circuit; the control module is used for controlling the circuit conversion module to complete a specific circuit output function under different test conditions; and the output circuit is connected with an external device to be tested. The invention uses two of the three groups of outputs of the tester as output ends, and the other group as input test ends, and completes the switching between the outputs to different pins through the double-pole double-throw switch. The invention realizes the test of the array diode chip, reduces the test cost, improves the test stability, reduces the test time and improves the test efficiency.
Description
Technical Field
The invention relates to an array diode chip efficient leakage current testing system and method, and belongs to the technical field of discrete device testing.
Background
In the prior art, a matrix box is adopted, and a relay matrix consisting of a plurality of relays is arranged in the matrix box, so that input and output conduction under different requirements is realized.
The technical scheme needs to turn on the relays one by one in the test process to realize the conductive connection between the test circuit and the pins of the device to be tested, so that longer test time is needed, and the internal circuit of the matrix box is complex and has larger influence on small current test.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the defects of long test time and complex circuit in the prior art, the invention provides the efficient leakage current test system and method for the array diode chip, which can simplify the test circuit, reduce the test time and reduce the test cost on the premise of ensuring the test precision.
The technical scheme is as follows: in order to realize the purpose, the invention adopts the technical scheme that:
the utility model provides an array diode chip high efficiency leakage current test system, includes input circuit, power circuit module, circuit conversion module, control module and output circuit, wherein:
the input circuit is used for realizing the input of the testing machine to the testing board and information exchange.
The output circuit is used for completing connection with an external device to be tested.
The power circuit module provides a power supply circuit required by the circuit.
The input circuit is two groups of channels in three groups of channels of the testing machine, the output circuit is the other group of channels in the three groups of channels of the testing machine, wherein the three groups of channels of the testing machine are respectively marked as a channel B, a channel E and a channel C, the channel B and the channel E are used as the input circuit, and the channel C is used as the output circuit.
The circuit conversion module comprises a first double-pole double-throw switch group and a second double-pole double-throw switch group, the first double-pole double-throw switch group comprises a first double-pole double-throw switch and a second double-pole double-throw switch, the immobile end of the first double-pole double-throw switch is connected with the power circuit module, the action end of the first double-pole double-throw switch points to the test loop end of the channel B, the immobile end of the second double-pole double-throw switch is connected with the power circuit module, and the action end of the second double-pole double-throw switch points to the output loop end of the channel B. The second double-pole double-throw switch group comprises a first double-pole double-throw switch and a second double-pole double-throw switch, the immobile end of the first double-pole double-throw switch is connected with the power circuit module, the action end of the first double-pole double-throw switch points to the test loop end of the E channel, the immobile end of the second double-pole double-throw switch is connected with the power circuit module, and the action end of the second double-pole double-throw switch points to the output loop end of the E channel.
The control module is used for controlling the circuit conversion module to realize circuit output under different test conditions.
Preferably: the control module is loaded with a single-pole control time sequence and controls the first double-pole double-throw switch group and the second double-pole double-throw switch group according to the single-pole control time sequence, so that the output of the circuit under different test conditions is realized.
Preferably: the output circuit is connected with an external device to be tested in a clamping mode; or the output circuit is connected with an external device to be tested in a bolt connection mode.
Preferably: the first double-pole double-throw switch group and the second double-pole double-throw switch group are both relays.
A method for testing the efficient leakage current of an array diode chip comprises the following steps:
And 2, switching on the power circuit module.
And 3, the control module respectively controls the first double-pole double-throw switch I and the first double-pole double-throw switch II to complete the input of the test signal and the output signal of the channel B according to the single-pole control time sequence, and controls the actions of the action ends of the second double-pole double-throw switch I and the second double-pole double-throw switch II to complete the input of the test signal and the output signal of the channel E.
And 4, outputting a final signal through the C channel by the tester according to the input of the test signal and the output signal of the B channel and the input of the test signal and the output signal of the E channel.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention realizes the test of the array diode chip, reduces the test cost and improves the test stability.
2. Aiming at the characteristics of the existing testing machine, the relay is skillfully utilized to complete a specific testing loop under different conditions, the purpose of rapid testing is realized, the testing time is reduced, and the testing efficiency is improved.
Drawings
Fig. 1 is a test schematic of a tester.
Fig. 2 is a circuit diagram of the circuit converting module.
Fig. 3 is a simplified schematic diagram of the internal principle of the chip.
Fig. 4 is a circuit diagram of the present invention.
Fig. 5 is a timing chart of the switch control.
Detailed Description
The present invention is further illustrated by the following description in conjunction with the accompanying drawings and the specific embodiments, it is to be understood that these examples are given solely for the purpose of illustration and are not intended as a definition of the limits of the invention, since various equivalent modifications will occur to those skilled in the art upon reading the present invention and fall within the limits of the appended claims.
An array diode chip high-efficiency leakage current test system is shown in fig. 4, and comprises an input circuit, a power circuit module, a circuit conversion module, a control module and an output circuit, wherein:
the input circuit mainly realizes the input and information exchange from the testing machine to the testing board.
The power circuit module provides a power supply circuit required by the circuit.
The control module is used for controlling the circuit conversion module to realize the specific circuit output function under different test conditions.
The output circuit is used for completing connection with an external device to be tested and is connected with the external device to be tested in a clamping mode; or the output circuit is connected with an external device to be tested in a bolt connection mode.
As shown in fig. 1, in the discrete device testing industry, kelvin connection is mostly adopted, a tester generally provides three channels, i.e., B (Base), C (Collector), and E (Emitter), and each channel provides a Force (output circuit) and a Sense (judgment circuit) to form an output loop and a test loop.
In this embodiment, two of the three sets of outputs of the tester are used as output terminals, and the other set of outputs are used as input test terminals, and the output is switched to different pins through the double-pole double-throw switch.
The input circuit is two groups of channels in three groups of channels of the testing machine, the output circuit is the other group of channels in the three groups of channels of the testing machine, wherein the three groups of channels of the testing machine are respectively marked as a channel B, a channel E and a channel C, the channel B and the channel E are used as the input circuit, and the channel C is used as the output circuit.
The circuit conversion module comprises a first double-pole double-throw switch group and a second double-pole double-throw switch group, the first double-pole double-throw switch group comprises a first double-pole double-throw switch and a second double-pole double-throw switch, the immobile end of the first double-pole double-throw switch is connected with the power circuit module, the action end of the first double-pole double-throw switch points to the test loop end of the channel B, the immobile end of the second double-pole double-throw switch is connected with the power circuit module, and the action end of the second double-pole double-throw switch points to the output loop end of the channel B. The second double-pole double-throw switch group comprises a first double-pole double-throw switch and a second double-pole double-throw switch, the immobile end of the first double-pole double-throw switch is connected with the power circuit module, the action end of the first double-pole double-throw switch points to the test loop end of the E channel, the immobile end of the second double-pole double-throw switch is connected with the power circuit module, and the action end of the second double-pole double-throw switch points to the output loop end of the E channel. The first double-pole double-throw switch group and the second double-pole double-throw switch group are both relays.
The control module is loaded with a single-pole control time sequence and controls the first double-pole double-throw switch group and the second double-pole double-throw switch group according to the single-pole control time sequence, so that the output of the circuit under different test conditions is realized.
As shown in fig. 2 and 3: BF denotes B (Base) (Force), and the B channel judging circuit BS denotes a B channel judging circuit (Sense). CF denotes a (Collector) C channel output circuit (Force), and CS denotes a (Collector) C channel judgment circuit (Sense). EF represents the E (Emitter) E-channel output circuit (Force), and ES represents the E (Emitter) E-channel judgment circuit (Sense). RY1A/RY2A is a relay number, G6K is an example relay model (the technical requirement is not limited to the model), U1 is a device under test, and TVS _ SP1064 is an example device under test model (the technical requirement is not limited to the model). The first double-pole double-throw switch group is a relay RY1A, and the second double-pole double-throw switch group is a relay RY2A.
In fig. 2, taking TVS _ SP1064 device as an example, the B channel determining circuits BS and BF are respectively connected to two mutually independent input pins of the relay RY1A, ES and EF are respectively connected to two mutually independent input pins of the relay RY2A, CS and CF are respectively connected to pins 8 and 3 of the device under test, and pins 3 and 8 are common terminal pins of the device under test. The pin 3 of the input end of the relay RY1A corresponds to two output pins 2 and 4, a control signal can control an input signal to be output from which output pin, the pin 6 of the input end corresponds to two output pins 7 and 5, the control signal can control the input signal to be output from which output pin, two groups of outputs are switched simultaneously, the principle of the relay RY2A is similar to that of a double-pole double-throw switch, and the principle of the relay RY1A is the same as that of the relay RY1A. Pins 2, 4, 7 and 5 of the relay RY1A are respectively connected to pins 10, 9, 1 and 2 of the tested device U1, pins 2, 4, 7 and 5 of the relay RY2A are respectively connected to pins 4, 5, 7 and 6 of the tested device U1, the pins 1, 10, 2 and 9, pins 4 and 7, and pins 5 and 6 are mutually input and output, and each group of pins are connected with transient suppression diodes to be combined to pins 3 and 8 of a common terminal in a chip. When the signal of the B channel judging circuit BS is connected to the 10 pin of the U1 through the switch, the BF signal is simultaneously provided for the 1 pin of the U1, so that the BF and BS connecting circuit forms a Kelvin connecting circuit, and similarly, the EF and ES connecting circuit and the CF and CS connecting circuit also form a Kelvin connecting circuit. During testing, the Force circuit gives signals, and the sensor circuit conducts testing.
A method for testing the efficient leakage current of an array diode chip comprises the following steps:
And 2, switching on the power circuit module.
And 3, the control module respectively controls the first double-pole double-throw switch I and the first double-pole double-throw switch II to complete the input of the test signal and the output signal of the channel B according to the single-pole control time sequence, and controls the actions of the action ends of the second double-pole double-throw switch I and the second double-pole double-throw switch II to complete the input of the test signal and the output signal of the channel E.
And 4, outputting a final signal through the C channel by the tester according to the input of the test signal and the output signal of the B channel and the input of the test signal and the output signal of the E channel.
As shown in fig. 5, which is a timing chart of the embodiment of the present invention, SW1 indicates the output timing of relay RY1A, SW2 indicates the output timing of relay RY2A, and the high level is active.
The working steps are as follows:
s01, relay RY1A and relay RY2A are given low level.
S02, enabling a B channel output circuit BF, a B channel judging circuit BS, a C channel output circuit CF and a C channel judging circuit CS, wherein the B channel output circuit BF is used for signal output, the C channel output circuit CF is used as a B channel output circuit BF signal loop, and the B channel judging circuit BS and the C channel judging circuit CS are used for testing. And after the test is finished, the output of the B channel output circuit BF is closed, and the test of the B channel judgment circuit BS and the test of the C channel judgment circuit CS are closed.
S03, enabling an E channel output circuit EF, an E channel judgment circuit ES, a C channel output circuit CF and a C channel judgment circuit CS, wherein the E channel output circuit EF is used for outputting, the C channel output circuit CF is used as an EF signal loop of the E channel output circuit, and the C channel judgment circuit CS and the E channel judgment circuit ES are used for testing. And after the test is finished, the output of the E channel output circuit EF is closed, and the test is closed by the E channel judgment circuit ES and the C channel judgment circuit CS.
And S04, the relay RY1A and the relay RY2A are in high level, and the switch switches to output.
And S05, enabling a B channel output circuit BF, a B channel judgment circuit BS, a C channel output circuit CF and a C channel judgment circuit CS, wherein the B channel output circuit BF is used for signal output, the C channel output circuit CF is used as a BF signal loop of the B channel output circuit, and the B channel judgment circuit BS and the C channel judgment circuit CS are used for testing. And after the test is finished, the output of the B channel output circuit BF is closed, and the test of the B channel judgment circuit BS and the test of the C channel judgment circuit CS are closed.
And S06, enabling an E channel output circuit EF, an E channel judgment circuit ES, a C channel output circuit CF and a C channel judgment circuit CS, wherein the E channel output circuit EF is used for outputting, the C channel output circuit CF is used as an EF signal loop of the E channel output circuit, and the E channel judgment circuit ES and the C channel judgment circuit CS are used for testing. And after the test is finished, the E channel output circuit EF closes the output, and the E channel judgment circuit ES and the C channel judgment circuit CS close the test.
S07, relay RY1A and relay RY2A return to low level.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.
Claims (2)
1. A test method of an array diode chip high-efficiency leakage current test system is provided, the array diode chip comprises a plurality of same-direction diodes and a reverse diode, the same-direction diodes are connected in parallel and then connected in series with the reverse diode, and the test method is characterized in that: the high-efficient leakage current test system of array diode chip includes input circuit, power supply circuit module, circuit conversion module, control module and output circuit, wherein:
the input circuit is used for realizing the input and information exchange from the testing machine to the testing board;
the output circuit is used for completing the connection with an external device to be tested;
the power supply circuit module provides a power supply circuit required by the circuit;
the input circuit is two groups of channels in three groups of channels of the testing machine, the output circuit is the other group of channels in the three groups of channels of the testing machine, wherein the three groups of channels of the testing machine are respectively marked as a channel B, a channel E and a channel C, the channel B and the channel E are used as input circuits, and the channel C is used as an output circuit;
the circuit conversion module comprises a first double-pole double-throw switch group and a second double-pole double-throw switch group, the first double-pole double-throw switch group comprises a first double-pole double-throw switch and a second double-pole double-throw switch, the immobile end of the first double-pole double-throw switch is connected with the power circuit module, the action end of the first double-pole double-throw switch points to the test loop end of the channel B, the immobile end of the second double-pole double-throw switch is connected with the power circuit module, and the action end of the second double-pole double-throw switch points to the output loop end of the channel B; the second double-pole double-throw switch group comprises a first double-pole double-throw switch and a second double-pole double-throw switch, the fixed end of the first double-pole double-throw switch is connected with the power circuit module, the action end of the first double-pole double-throw switch points to the test loop end of the E channel, the fixed end of the second double-pole double-throw switch is connected with the power circuit module, and the action end of the second double-pole double-throw switch points to the output loop end of the E channel; the first double-pole double-throw switch group is a relay RY1A, and the second double-pole double-throw switch group is a relay RY2A;
the control module is used for controlling the circuit conversion module to realize circuit output under different test conditions; the control module is loaded with a single-pole control time sequence and controls the first double-pole double-throw switch group and the second double-pole double-throw switch group according to the single-pole control time sequence so as to realize the output of the circuit under different test conditions;
the test method comprises the following steps:
step 1, loading a single-blade control time sequence to be controlled into a control module during testing; each channel of the tester provides a force output circuit F and a judgment circuit S to form an output loop and a test loop; two groups of three groups of outputs of the tester are used as output ends, the other group is used as an input test end, and the switching from the outputs to different pins is completed through a double-pole double-throw switch;
step 2, switching on a power circuit module;
step 3, the control module respectively controls the first double-pole double-throw switch I and the first double-pole double-throw switch II to finish the input of the test signal and the output signal of the channel B according to the single-pole control time sequence, and controls the actions of the action ends of the second double-pole double-throw switch I and the second double-pole double-throw switch II to finish the input of the test signal and the output signal of the channel E;
step 4, the testing machine outputs a final signal through the C channel according to the input of the test signal and the output signal of the B channel and the input of the test signal and the output signal of the E channel;
the test working steps are as follows:
s01, the relay RY1A and the relay RY2A give low level;
s02, enabling a B channel output circuit BF, a B channel judgment circuit BS, a C channel output circuit CF and a C channel judgment circuit CS, wherein the B channel output circuit BF is used for signal output, the C channel output circuit CF is used as a BF signal loop of the B channel output circuit, and the B channel judgment circuit BS and the C channel judgment circuit CS are used for testing; after the test is finished, the output of the B channel output circuit BF is closed, and the test of the B channel judgment circuit BS and the test of the C channel judgment circuit CS are closed;
s03, enabling an E channel output circuit EF, an E channel judgment circuit ES, a C channel output circuit CF and a C channel judgment circuit CS, wherein the E channel output circuit EF is used for outputting, the C channel output circuit CF is used as an E channel output circuit EF signal loop, and the C channel judgment circuit CS and the E channel judgment circuit ES are used for testing; after the test is finished, the output of the E channel output circuit EF is closed, and the test is closed by the E channel judgment circuit ES and the C channel judgment circuit CS;
s04, the relay RY1A and the relay RY2A supply high level, and the switch switches to output;
s05, enabling a B channel output circuit BF, a B channel judgment circuit BS, a C channel output circuit CF and a C channel judgment circuit CS, wherein the B channel output circuit BF is used for signal output, the C channel output circuit CF is used as a BF signal loop of the B channel output circuit, and the B channel judgment circuit BS and the C channel judgment circuit CS are used for testing; after the test is finished, the output of the B channel output circuit BF is closed, and the test of the B channel judgment circuit BS and the test of the C channel judgment circuit CS are closed;
s06, enabling an E channel output circuit EF, an E channel judgment circuit ES, a C channel output circuit CF and a C channel judgment circuit CS, wherein the E channel output circuit EF is used for outputting, the C channel output circuit CF is used as an EF signal loop of the E channel output circuit, and the E channel judgment circuit ES and the C channel judgment circuit CS are used for testing; after the test is finished, the output of the E channel output circuit EF is closed, and the test is closed by the E channel judgment circuit ES and the C channel judgment circuit CS;
s07, relay RY1A and relay RY2A return to low level.
2. The testing method of the array diode chip efficient leakage current testing system according to claim 1, characterized in that: the output circuit is connected with an external device to be tested in a clamping mode; or the output circuit is connected with an external device to be tested in a bolt connection mode.
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