CN114868254A - 包括与场效应晶体管串联的绝缘栅场效应晶体管的半导体器件 - Google Patents

包括与场效应晶体管串联的绝缘栅场效应晶体管的半导体器件 Download PDF

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CN114868254A
CN114868254A CN202080073907.4A CN202080073907A CN114868254A CN 114868254 A CN114868254 A CN 114868254A CN 202080073907 A CN202080073907 A CN 202080073907A CN 114868254 A CN114868254 A CN 114868254A
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K-H·埃克隆德
L·韦斯特林
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K EKLUND INNOVATION
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Abstract

一种半导体器件，包括与场效应晶体管(2)FET串联的绝缘栅场效应晶体管(1)，其中，FET(2)包括若干平行导电层(n1‑n5，p1‑p4)，并且其中，第一导电类型的衬底(11)布置为半导体器件的基底，从而在两个晶体管(1，2)下方延伸，第二导电类型的第一层(n1)布置为在衬底(11)上方延伸，其中，在所述第一层(n1)的顶部布置有具有沟道的若干导电层，所述沟道由若干第一导电类型掺杂的外延层(n2‑n4)形成，所述第一导电类型掺杂的外延层(n2‑n4)的两侧具有第一导电类型的层(p1‑p4)，其中，所述器件的最上层(p5)优选地比直接在表面下的若干平行导电层(p1‑p4，n1‑n4)实质上更厚，场效应晶体管(2)JFET在JFET的源极侧通过第二导电类型的深多晶硅沟槽DNPT(22)隔开，绝缘栅场效应晶体管(1)通过两侧的第一导电类型的深多晶硅沟槽DPPT(22，23)隔开，包括逻辑和模拟控制功能的另一隔开的区域(5)通过两侧的第一导电类型的深多晶硅沟槽DPPT(23，24)隔开。

Description

包括与场效应晶体管串联的绝缘栅场效应晶体管的半导体 器件
本发明涉及一种具有改进的电压和电流能力的包括与场效应晶体管串联的绝缘栅场效应晶体管的半导体器件，特别是具有非常低的导通电阻的器件。本发明特别是对申请人于2019年3月14日提交的先前申请PCT/SE2019/050229的进一步发展。
为了将高压功率器件与低压模拟和数字功能结合在同一芯片上，在硅的内部与JFET串联的绝缘栅场效应晶体管(例如MOSFET)长期以来一直是业界的主力。为了改进电压和电流能力，已经从单面JFET演变为将导通电阻降低到一半的对称JFET，如美国专利No 4,811,075A所述，该专利描述了串联在同一芯片上以形成高压MOS晶体管的绝缘栅场效应晶体管和双面结型栅场效应晶体管，并且进一步开发有具有两个串联沟道的JFET，从而进一步降低了30％的导通电阻，如美国专利No 5,313,082A所示。
美国专利No 6,168,983B1进一步改进了最新专利，其提出了在衬底中的衬底顶部的共用N阱或N型外延层中垂直实施的具有若干平行导电层的JFET。后来还表明，如果绝缘栅场效应晶体管和JFET的串联连接是在外部进行的，那么可以进一步降低导通电阻、改进高频性能并且提高可靠性，如美国专利No 8,264,015B2所述。在该专利中，还提出了若干平行的JFET沟道与绝缘栅场效应晶体管串联实施在共用N阱中，所述绝缘栅场效应晶体管的尺寸可以优化为与JFET沟道的数量相匹配。由于是外部连接，这在美国专利No 6,168,983B1中无法实现，因为其连接是在硅内部。
平行导电层的数量实际上通过绝缘栅晶体管设定，并且进一步通过在该专利中设置为15μm的N阱的深度设定。在美国专利No8,264,015B2中也存在类似的限制，平行导电层的数量通过注入能量设定。
由于先前所述的非常高的能量注入是一个基本限制，因此提出的通过离子注入来产生多个导电层的概念并不像预期的那样成功。
其它限制性问题是降低迁移率的辐射损失和注入的原子的轮廓的扩展。当前的水平仍然是2至3层平行的导电层，例如根据Don Disney等人的《High-Voltage IntegratedCircuits:History,State of the Art,And Future Prospects》，IEEE电子器件汇刊(IEEETransactions on Electron Devices)，2017年3月，第3期，第64卷。
目前的方法提出了导电层通过具有更好的控制的外延层制成，该方法没有辐射损失。此外，可以用As代替P作为离子注入中的掺杂剂，从而提供更高的迁移率。利用外延技术，可以平行制作的导电层的数量没有基本限制。
由于导电层的电阻已知，因此性能的估计可以作为器件的优值Ron*A很容易地实现：
对于6-8层导电层，可得：
对于230V的器件，Ron*A大约为100mΩmm2，而目前的技术水平为500mΩmm2
对于700V的器件，Ron*A大约为2Ω*mm2，而目前的技术水平为15Ω*mm2，例如根据Don Disney等人的《High-Voltage Integrated Circuits:History,State of the Art,And Future Prospects》，IEEE电子器件汇刊(IEEE Transactions on ElectronDevices)，2017年3月，第3期，第64卷。
面积优势当然意味着更低的成本，而且还意味着大幅降低的电容、提高的切换速度和更高的效率。即使在1200V下，也有真正的机会与垂直功率MOS器件和SiC器件竞争。
所有这些都具有数量适中的6-8层平行导电层。因为没有基本限制而仅仅是实用性限制，所以可以容易地增加层的数量。
现在将借助附图所示的几个非限制性实施方案以及包括先前申请的实施方案来进一步说明本发明，其中图1示意性地示出了根据先前发明的具有与包括若干导电层的JFET串联的MOS晶体管的形式的半导体器件的第一实施方案，图2示出了根据先前发明的具有与包括若干导电层的JFET串联的MOS晶体管的形式的半导体器件的第二实施方案，每个外延层中有两个注入的p层，图3示出了以利用BOX层的SOI技术的方式实现类似于图1的器件，图4示出了用于创建与根据图1或图3的器件的接地漏极并联的肖特基二极管的另一可选的栅极注入掩模，图5示出了用于创建与根据图2的器件的接地漏极并联的肖特基二极管的可选的栅极注入掩模，图6示出了在SOI上实施的基于根据图2的器件的LIGBT器件，其中漏极的掺杂已经改变为p+，并且与DPPT接触，从而创建无闭锁的LIGBT，图7示出了根据本发明的类似于图1、具有与包括若干导电层的JFET串联的MOS晶体管的形式的半导体器件的第一实施方案，其具有用于CMOS兼容性的p型上层，图8示出了图1中的器件的替代解决方案，其中，在底层中具有附加的导电层，以降低总电阻，图9示出了根据先前发明的类似于图2、具有与包括若干导电层的JFET串联的MOS晶体管的形式的半导体器件的第二实施方案，每个外延层中有两个注入的p层，其具有用于CMOS兼容性的p型上层，图10示出了图2所示的半导体器件的替代解决方案，其中，在底层中具有附加的导电层，以降低总电阻。
图1中示出了左边的MOS晶体管1与右边的JFET2串联，JFET2包括若干导电层、由如图所示的平行的n层n1-n5形成并且通过共用的p层p1-p4(栅极)隔开的JFET沟道。所述层在外延反应器中原位沉积，或者在两个反应器中沉积，其中，n层在一个反应器中沉积，p层在另一个反应器中沉积。如果使用两个反应器，那么如果晶圆在真空下通过互锁从一个反应器传输到另一个反应器，这将会是巨大的优势。第一层开始于电阻率范围为10Ωcm至135Ωcm的p型衬底的顶部。所述层的厚度和掺杂浓度通过resurf原理确定，这意味着层的厚度和掺杂浓度的乘积应当为大约每平方厘米2*1012电荷，这意味着只要满足此条件，厚度和掺杂浓度可以改变。
图中的第一沟道区域选择为2μm厚，掺杂浓度为1*1016/cm3，那么，满足上述条件。然后将接下来的层的厚度和掺杂浓度选择为0.5μm和4*1016/cm3的掺杂浓度，并且实际上也可以是与其类似的厚度和掺杂浓度。
作为实际的示例，平行的n层n1-n5的数量在n5外延层之前停止，所述外延层优选地制作为更厚，为2.5μm，并且具有作为上部栅极的厚度为0.5μm且电荷量为每平方厘米1*1012的掩蔽注入的px层17。px层17只是用作最上部沟道的栅极，这使得沟道层厚度为2μm并且具有5*1015/cm3的掺杂浓度。沟道层在漏极侧利用深N型多晶硅沟槽(deep N-polytrench，DNPT)20连接在一起，沟道层在源极侧也通过深N型多晶硅沟槽(DNPT)21连接在一起。JFET2由深P型多晶硅沟槽(deep P-poly trench，DPPT)22隔开，同时连接通常将接地的p层p1-p4，并且利用开口30以大约5μm的给定间隔打断源极DNPT，以在另一方向接触p层p1-p4。除了JFET2的如此形成的隔开的区域3之外，另外的DPPT 23可以产生隔开的n岛，例如图中的4和5。
在MOS晶体管1的隔开的n型区域4内布置第一导电类型(例如p型材料)的主体区域12，并且以每cm3内1*1017至1*1018原子进行掺杂。主体区域12通常延伸至器件表面以下1μm或更小的深度。在MOS晶体管1的主体区域12内布置以每cm3内1*1018至1*1020原子进行掺杂的第二导电类型(例如n+型材料)的源极区域13。源极区域13在器件表面以下延伸例如0.4μm或更小。源极区域13左侧的第一导电类型的主体区域12中的主体接触区域121以每cm3内1*1018至1*1020原子进行掺杂。主体接触区域121在器件表面以下延伸例如0.4μm或更小。通过将主体区域12和主体接触区域121延伸到形成的凹槽区域之外，主体区域12和主体接触区域121两者可以电连接至衬底。
第二导电类型(例如n+型材料)的MOS晶体管1的漏极的接触区域16以每cm3内1*1018至1*1020原子进行掺杂。漏极的接触区域16在器件表面以下延伸例如0.4μm或更小。
在JFET2的隔开区域3内布置以每cm3内1*1018至1*1020原子进行掺杂的第二导电类型(例如n+型材料)的源极区域18和漏极区域19。源极区域18和漏极区域19在器件表面以下延伸例如0.4μm或更小。
MOS晶体管1的漏极的接触区域16将与JFET2的源极18的接触区域电接触，从而构成与JFET2串联的MOS晶体管1。
器件的击穿电压将由JFET2的源极区域18和漏极区域19之间的漂移区域LD和衬底电阻率决定。
作为逻辑和模拟控制功能的示例，可以容易地制作若干隔开的区域5。
即使逻辑和MOS器件能够如图1所示在隔开的n层中并且如先前的申请中所述实现，p层对于MOS器件的逻辑和工作也是更优选的，并且是本发明的目的。
可以产生以类似的方式隔开的p型区域，参见图7。在p层p4之后，沉积薄的外延n层n5，然后沉积外延p层p5，其优选地制作为更厚，为2.5μm并且具有掩蔽注入的nx层31。作为厚度为0.5μm且电荷量为每平方厘米1*1012的上部导电层，表面下的p5层的厚度为2μm且电荷量为每平方厘米2*1012，那么，其与1*1016/cm3的掺杂浓度相对应。p型区域4和5将具有相同的掺杂浓度，并且厚度为2.5μm，该掺杂浓度是目前的技术水平的CMOS的标准。也可以通过将p5外延层制作为夹在两个p层中间来容易地实现具有1*1015/cm3的起始p型材料掺杂浓度的CMOS的较旧的标准，其中，第一个p层厚度为1μm，掺杂浓度为2*1016，另一个p层在顶部，厚度为1.5μm，掺杂浓度为1*1015。然后，掩蔽的nx层31应当覆盖p5层的顶部。
器件可以优选地制作为对称的，在图中右侧具有镜像，其中26表示对称线。
图1所示的器件工作的一个重要要求是JFET2中任一FET的夹断电压低于MOS晶体管1的击穿电压。夹断电压将出现在FET的共用源极18上，然后连接至隔开的MOS晶体管1的漏极16。图1中表示了p型衬底11顶部的第一层n1更厚，这是为了满足高击穿电压的要求。对于大约800V的击穿电压，该层的厚度应当大约为6-7μm，夹断电压为50V或更高。这意味着MOS晶体管将以较好的裕度经受50V。此外，50V的MOS晶体管将比10V的MOS器件占用更多空间，性能更低。因此，首先建议将其余的n层设计为10V的夹断电压，并且第一层通过屏蔽层29来屏蔽JFET2的源极18，如图1所示。
然后，为了解决n1层对电流和电阻没有贡献的问题，现在提出去除屏蔽层29并且在n1层的中部靠近源极放置新的p型区域pa，于是，产生了两个新的沟道，一个在pa的顶部，另一个在pa以下，这两个沟道都会在10V以下夹断。pa的长度大约为3μm，电荷量大约为每平方厘米1*1013。这在图8中示出。这两个短沟道将略微增加n1层从漏极到源极的电阻(10-15％)。总共的，向前四个导电层平行增加第五导电层，从而将导通电阻降低大约20％。对于需要更厚的n1层的更高的击穿电压，提出增加另一个p型区域pb和可能的更多的区域pc等等，直到达到所需的性能。
随着JFET的漏极电压增加(例如，高达800V)，共用JFET的夹断电压(或者实际上是源极电压)应该很低并且恒定。这种情况将不会发生，因为漏极电压升高时，源极电压升高。通过靠近JFET源极18增大栅极层p1-p5中的掺杂浓度而沿着栅极层p1-p5的边缘形成屏蔽区域17”，从而形成与超级结FET串联的传统FET，其中栅极层将永远不会完全耗尽。这将使得当JFET的漏极电压增加到800V时，JFET2的源极电压保持恒定。这将在数量级上进一步降低重要的密勒电容。由于所示区域中的掺杂浓度已经大幅增大，因此可以用于大大降低栅极层的接地频率并且增大JFET的有效宽度。屏蔽区域中的电荷量可以大约为每平方厘米2*1013。
栅极层p1-p5将优选地通过使该层与DPPT层22在相同区域内接触的指状件17'接地，在该区域中，DNPT 21被掩模中的开口30打断，从而产生了指状件17'从栅极层延伸并且n+源极18、18'的接触将被中断的区域。也可以通过从区域中的DPPT 22延伸的DPPT的指状件连接所有栅极层，在该区域中，打断源极DNPT 21以接触每个p层p1-p5，从而替代指状件17'。DPPT指状件可以非常频繁地每隔4-5μm接触p层。DPPT指状件还将充当n层的侧栅极，然后将提供与如上所述的屏蔽区域17”相同的性能优势。
衬底11是第一导电类型并且通常作为第一导电类型的层接地。当漏极(即n1层)上的电压增大时，该层将从衬底和第一p层p1耗尽。因此，衬底将用作第二导电类型的第一层n1的第二栅极。
图2示出了与JFET 2串联的MOS晶体管1，JFET 2包括若干导电层、平行的JFET沟道(图2中的导电n层并且通过图案化的共用p层(栅极)隔开)。
厚度为2μm的第一n型外延层在电阻率范围为10Ωcm至135Ωcm的p型衬底的顶部生长。将晶圆从反应器中取出，通过注入的栅极层p1和p2形成两个导电层n1和n2。
所述层的厚度和掺杂浓度通过resurf原理确定，这意味着层的厚度和掺杂浓度的乘积应当为大约每平方厘米2*1012电荷，这意味着只要满足此条件，厚度和掺杂浓度可以改变。
图中的第一沟道区域n1选择为0.5μm厚，掺杂浓度为4*1016/cm3，那么，满足上述条件。
然后接下来的层的厚度和掺杂浓度选择为0.5μm，掺杂浓度为4*1016/cm3，并且实际上也可以是一个与其类似的厚度和掺杂浓度。
作为实际的示例，沉积了5个外延层N1-N5，其中每个外延层都有两个注入的p层。
在漏极侧，沟道层3与表面中的n+漏极注入连接在一起。在源极侧，沟道层3与表面中的n+漏极注入连接在一起。
JFET 2利用JFET的源极侧的深p型多晶硅沟槽(DPPT)22隔开。源极侧的DPPT 22具有以给定间隔连接p层p1-p10的指状件。
上部p10栅极层17将通过掩模中的开口30与DPPT层接触，从而形成一个区域，在该区域中，指状件17'从栅极层延伸，并且n+源极18、18'的接触中断。同一掩模将用于产生和接触所有其他栅极层。指状件17'将确保所有n层接触。
在隔开的n型区域内或部分地在隔开的n型区域内，第一导电类型(例如p型材料)的主体区域以每cm3内1*1017至1*1018原子进行掺杂。主体区域12通常延伸至器件表面以下1μm或更小的深度。
在MOS晶体管1的主体区域12内，第二导电类型(例如n+型材料)的源极区域13以每cm3内1*1018至1*1020原子进行掺杂。源极区域13在器件表面以下延伸例如0.4μm或更小。第一导电类型的源极区域左侧的主体区域12中的主体接触区域121以每cm3内1*1018至1*1020原子进行掺杂。主体接触区域121在器件表面以下延伸例如0.4μm或更小。通过将主体区域12和主体接触区域121延伸到凹槽区域之外，主体区域12和主体接触区域121两者可以电连接至衬底。
第二导电类型(例如n+型材料)的漏极的接触区域16以每cm3内1*1018至1*1020原子进行掺杂。漏极的接触区域16在表面以下延伸例如0.4μm或更小。
在JFET的隔开的区域3内布置以每cm3内1*1018至1*1020原子进行掺杂的第二导电类型(例如n+型材料)的源极区域18和漏极区域19。源极区域18和漏极区域19在表面以下延伸例如0.4μm或更小。
MOS晶体管1的漏极的接触区域16将与JFET2的源极18的接触区域电接触，从而构成与JFET2串联的MOS晶体管1。
器件的击穿电压将由漂移区域LD和衬底电阻率决定。
如前所述，使最上部较厚的层为p型而不是n型是有益的，这是本发明的目的。
也可以通过移除外延层N4中的p8、将外延层N4的厚度从2μm减小到1.5μm并且在顶部沉积掺杂浓度为1*1016/cm3的2.5μm厚的p外延层PX来修改图2所示的器件。在器件的顶部注入厚度为0.5μm、电荷量为每平方厘米1*1012的nx层31。这在图9中示出。表面下的p层的厚度现在为2μm，电荷量为每平方厘米2*1012，那么，对应于1*1016/cm3的掺杂浓度。p型区域4和5将具有相同的掺杂浓度，厚度为2.5μm，该掺杂浓度是目前的技术水平的CMOS的标准。也可以通过将p5外延层制作为夹在两个p层中间来容易地实现对于具有1*1015/cm3的起始p型材料掺杂浓度的CMOS的较旧标准，其中，第一个p层厚度为1μm，掺杂浓度为2*1016，另一个p层在顶部，厚度为1.5μm，掺杂浓度为1*1015。然后，掩蔽的nx层31应当覆盖p5层的顶部。在源极侧还添加了DNPT。
作为逻辑和模拟控制功能的示例，可以容易地制作若干隔开的区域5。
图2所示的器件工作的一个重要要求是JFET2中任一FET的夹断电压低于MOS晶体管1的击穿电压。夹断电压将出现在FET的共用源极18上，然后连接至隔开的MOS晶体管1的漏极16。以与图1所示的相同的方式，p型衬底11顶部的第一层n1更厚，这是为了满足高击穿电压的要求。对于大约800V的击穿电压，该层的厚度应当为大约6-7μm，夹断电压为50V或更高。这意味着MOS晶体管将以良好的裕度经受50V。此外，50V的MOS晶体管将比10V的MOS器件占用更多空间，性能更低。因此，首先建议将其余的n层设计为10V的夹断电压，并且第一层通过如图2所示的屏蔽层29来屏蔽JFET2的源极18。
然后，为了解决第一层的29和p1对电流和电阻没有贡献的问题，去除第一层的29和p1，如图10所示。那么p2下的厚度应当为6μm。这一层命名为n2。大致在所述厚度的中间布置新的p型区域pa，那么，产生了两个新的沟道，一个在pa的顶部，另一个在pa以下，这两个沟道都会在10V以下夹断。这两个短沟道将略微增大n2层从漏极到源极的电阻(10-15％)。对于需要更厚的n2层的更高的击穿电压，提出增加另一个p型区域pb和可能的更多的区域pc等等，直到达到所需的性能。
随着JFET的漏极19的电压增加(例如高达800V)，共用JFET的夹断电压(或者实际上是源极18的电压)应该很低并且恒定。因为当漏极电压升高时，源极电压升高，所以这种情况将不会发生。通过靠近JFET源极18增大栅极层p1-p10中的掺杂浓度而沿着栅极层p1-p10的边缘形成屏蔽区域17”，从而形成与超级结FET串联的传统FET，其中栅极层将永远不会完全耗尽。这将使得当JFET的漏极电压增大到800V时，JFET2的源极18的电压保持恒定。这将在数量级上进一步降低重要的密勒电容。由于所示区域中的掺杂浓度已经大幅增大，因此可以用于大大降低栅极层的接地频率并且增加JFET的有效宽度。屏蔽区域中的电荷量可以大约为每平方厘米2*1013。
图3示出了与JFET 2串联的MOS晶体管1，JFET2包括若干导电层、平行的JFET沟道(图中的n层n1-n5并且通过共用的p层p1-p4(栅极)隔开)。这些层在外延反应器中原位沉积在由p型衬底11承载的氧化物层10的顶部。在开始生长外延层n1-n5、p1-p4之前，在氧化物层10的顶部存在薄的晶种层。
所述层的厚度和掺杂浓度通过resurf原理确定，这意味着层的厚度和掺杂浓度的乘积应当为大约每平方厘米2*1012电荷，这意味着只要满足此条件，厚度和掺杂浓度可以改变。
在附图中，这些外延层以0.5μm的相等厚度和4*1016/cm3的掺杂浓度开始，并且实际上可以是与其类似的厚度和掺杂浓度。
作为实际的示例，外延层的数量在n5外延层之前停止，n5外延层制作为更厚，为4.5μm，并且具有作为上部栅极的掩蔽注入的px层17，其厚度为0.5μm并且电荷量为1*1012。注入的px层只是用作一个沟道的栅极，这使得沟道层厚度为4μm并且掺杂浓度为5*1015/cm3。
px栅极层17将通过指状件17'以与图1中的器件相同的方式与DPPT 22接触。
沟道层n1-n5在漏极侧利用深N型多晶硅沟槽(DNPT)20连接在一起，沟道层在源极侧也通过深N型多晶硅沟槽(DNPT)21连接在一起。JFET2由深p型多晶硅沟槽(DPPT)22隔开，同时连接通常将接地的p层p1-p4，并且以给定间隔中断源极DNPT21以在另一方向上接触p层p1-p4。除了隔开的区域3之外，另外的DPPT 23、24可以产生隔开的n岛，例如图中的4和5。
在隔开的n型区域4内或部分地在隔开的n型区域4内，第一导电类型(例如p型材料)的主体区域12以每cm3内1*1017至1*1018原子进行掺杂。主体区域12通常延伸至器件表面以下1μm或更小的深度。在MOS晶体管1的主体区域12内，第二导电类型(例如n+型材料)的源极区域13以每cm3内1*1018至1*1020原子进行掺杂。源极区域13在器件表面以下延伸例如0.4μm或更小。在第一导电类型的源极区域12的左侧布置主体区域12中的主体接触区域121，并且主体接触区域121以每cm3内1*1018至1*1020原子进行掺杂。主体接触区域121在器件表面以下延伸例如0.4μm或更小。通过将主体区域12和主体接触区域121延伸到凹槽区域之外，主体区域12和主体接触区域121两者可以电连接至衬底。
第二导电类型(例如n+型材料)的漏极的接触区域16以每cm3内1*1018至1*1020原子进行掺杂。漏极的接触区域16在器件表面以下延伸例如0.4μm或更小。
在JFET2的隔开的区域3内布置以每cm3内1*1018至1*1020个原子进行掺杂的第二导电类型(例如n+型材料)的源极区域18和漏极区域19。源极区域18和漏极区域19在器件表面以下延伸例如0.4μm或更小。
MOS晶体管1的漏极的接触区域16将与JFET2的源极18的接触区域电接触，从而构成与JFET2串联的MOS晶体管1。器件的击穿电压将由漂移区域LD决定。
作为逻辑和模拟控制功能的示例，可以容易地制作若干隔开的区域5。
在结合图3所示和描述的实施方案中，外延层位于氧化物层10的顶部。这种实现也可以与结合图2所示和描述的实施方案一起提供，其中p层被注入外延n层中。
可以容易地在内部实现与漏极并联并且接地的高压肖特基二极管。
图1中的px指状件17'被分成两部分(参见图4)，在中间产生n型表面区域27，与肖特基金属或硅化物28的这一接触将创建与PN结并联的肖特基二极管。在许多电机应用中，高性能二极管非常重要，其中二极管是正向偏置的，当切换回正常反向状态时，产生大量寄生功率。二极管太慢，而集成肖特基二极管将解决这个问题。将无需使用外部二极管。
通过利用图2中的器件并将P10的指状件分成两部分(参见图5)、在中间产生n型表面区域27来形成相应的器件，与肖特基金属或硅化物28的这一接触将创建与PN结并联的肖特基二极管。
横向LIGBT是MOS晶体管和横向PNP晶体管的组合，其中MOS晶体管驱动PNP晶体管的基极。该器件容易闭锁，这限制了其电流能力。在传统的器件中，MOS晶体管和横向pnp在同一个N阱(N型区域)中制成。通过将这些器件分开，可以生成具有大幅提高的电流能力的、无闭锁的LIGBT。参见美国专利No.US 8,264,015B2。
在图6中，图2中的器件在SOI上实现，其中漏极19的掺杂已经改变为p+，并且与DPPT 20接触。这将形成横向PNP晶体管，其中发射极是p+连接的DPPT 20，基极是与基极接触区域连接的所有导电n层。集电极是与DPPT 20连接的所有栅极层。由于基极由外部MOS晶体管馈电，因此产生了具有许多导电的N型区域的无闭锁的LIGBT，这将极大地提高电流能力。
在所有可以制作为对称的器件中，在图中右侧具有镜像，附图标记26表示对称线。
也可以修改本文所述的发明，以使所述的所有n层替换为p层，并且相应地，包括p型衬底的所有p层替换为n层。

Claims (18)

1.一种半导体器件，其包括：
绝缘栅场效应晶体管IGFET(1)，其与高压场效应晶体管JFET(2)串联，
其中，JFET(2)包括若干平行导电层(n1-n5，p1-p4)，
其特征在于，
第一导电类型的衬底(11)布置为半导体器件的基底，从而在两个晶体管(1，2)下方延伸，
第二导电类型的第一层(n1)布置为在衬底(11)上方延伸，
其中，在所述第一层(n1)的顶部布置有具有沟道的若干导电层，所述沟道由若干第二导电类型掺杂的外延层(n2-n4)形成，所述第二导电类型掺杂的外延层(n2-n4)的两侧具有第一导电类型的层(p1-p4)，
其中，所述器件的最上层(p5)优选地比直接位于下方的若干平行导电层(p1-p4，n1-n4)实质上更厚，
场效应晶体管JFET(2)在JFET的源极侧通过第二导电类型的深多晶硅沟槽DNPT(22)隔开，
绝缘栅场效应晶体管(1)通过两侧的第一导电类型的深多晶硅沟槽DPPT(22，23)隔开，
包括逻辑和模拟控制功能的另一隔开的区域(5)通过两侧的第一导电类型的深多晶硅沟槽DPPT(23，24)隔开。
2.根据权利要求1所述的半导体器件，
其特征在于，
最上部的导电层(p5)在器件的表面具有第二导电类型的掩蔽注入的层(nx)(31)。
3.根据权利要求1或2所述的半导体器件，
其特征在于，
包括掺杂的栅极的第一导电类型的层(p1-p5)在靠近JFET源极(18)的一侧包括屏蔽区域(17”)，所述屏蔽区域(17”)具有比包括掺杂的栅极的层(p1-p5)的另一部分更高的掺杂浓度。
4.根据前述权利要求中任一项所述的半导体器件，
其特征在于，
布置为在衬底(11)上方延伸的第二导电类型的第一层(n1)在靠近JFET源极(18)的一侧设置有第一导电类型的屏蔽层(29)，从而阻挡来自第二导电类型的第一层(n1)的任何电流经由第二导电类型的深多晶硅沟槽DNPT(21)到达源极(18)。
5.根据权利要求1-3中的任一项所述的半导体器件，
其特征在于，
布置为在衬底(11)上方延伸的第二导电类型的第一层(n1)在靠近JFET源极(18)的一侧设置有位于n1层的中部的至少一个p型区域(pa，pb)，从而在所述至少一个p型区域(pa，pb)的上方和下方产生新的沟道。
6.根据前述权利要求中任一项所述的半导体器件，
其特征在于，
开口(30，17'，30)布置在源极连接区域(21)中，使得所有栅极层(17)接触深多晶硅沟槽DPPT(22)。
7.根据权利要求3和6所述的半导体器件，
其特征在于，
第一导电类型的指状件(17')布置为延伸穿过源极连接区域(21)中的开口(30，17'，30)，从而将屏蔽区域(17”)与深多晶硅沟槽DPPT(22)连接。
8.根据权利要求3和6所述的半导体器件，
其特征在于，
DPPT材料的指状件(17')布置为延伸穿过源极连接区域(21)中的开口(30，17'，30)，从而靠近源极以规则的间隔将深多晶硅沟槽DPPT(22)与p层p1-p5连接。
9.根据前述权利要求中任一项所述的半导体器件，
其特征在于，
衬底(11)与DPPT(22-24)连接以用作第二导电类型的第一层(n1)的第二栅极。
10.根据前述权利要求中任一项所述的半导体器件，
其特征在于，
第一导电类型掺杂的栅极是以外延的方式形成的层(p1-p4)。
11.根据权利要求1-9中的任一项所述的半导体器件，
其特征在于，
第一导电类型掺杂的栅极(p1和p2)是在第二导电类型掺杂的外延层(N1)中注入离子形成的层，从而产生导电层(n1和n2)，然后在沉积接下来的第二导电类型掺杂的外延层(N2-N4)之后重复相同的步骤，最后沉积第一导电类型掺杂的外延层(PX)。
12.根据前述权利要求中任一项所述的半导体器件，
其特征在于，
沟道层(n1-n5)在JFET(2)的漏极侧(19)通过深n型多晶硅沟槽DNPT(20)连接在一起，沟道层(n1-n5)在JFET(2)的源极侧(18)通过深n型多晶硅沟槽DNPT(21)连接在一起。
13.根据前述权利要求中任一项所述的半导体器件，
其特征在于，
绝缘栅场效应晶体管(1)的漏极的接触区域(16)与场效应晶体管JFET(2)的源极(18)的接触区域电接触。
14.根据前述权利要求中任一项所述的半导体器件，
其特征在于，
绝缘栅场效应晶体管(1)是MOS晶体管(1)。
15.根据前述权利要求中任一项所述的半导体器件，
其特征在于，
集成的高速肖特基二极管并联连接在DNPT(21)和DPPT(22)之间，所述集成的高速肖特基二极管通过使n沟道层(27)与肖特基金属(28)接触而实现在与MOS晶体管(1)隔开的JFET的源极侧。
16.根据权利要求12所述的半导体器件，
其特征在于，
所述器件是无闭锁的LIGBT，其中，JFET(2)的漏极(19)的掺杂已经从第二导电类型改变为第一导电类型，从而创建横向PNP晶体管，其中PNP的基极由MOS晶体管(1)馈电。
17.根据前述权利要求中任一项所述的半导体器件，
其特征在于，
第一导电类型的层是p层，第二导电类型的层是n层。
18.根据权利要求1-16中的任一项所述的半导体器件，
其特征在于，
第一导电类型的层是n层，第二导电类型的层是p层。
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