CN114866077A - Driving circuit of power tube and electronic equipment - Google Patents

Driving circuit of power tube and electronic equipment Download PDF

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Publication number
CN114866077A
CN114866077A CN202210355295.9A CN202210355295A CN114866077A CN 114866077 A CN114866077 A CN 114866077A CN 202210355295 A CN202210355295 A CN 202210355295A CN 114866077 A CN114866077 A CN 114866077A
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CN
China
Prior art keywords
current
transistor
tube
monitoring
pmos
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Withdrawn
Application number
CN202210355295.9A
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Chinese (zh)
Inventor
王飞
郑鲲鲲
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Guangdong Hongyixin Automobile Electronic Technology Co ltd
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Guangdong Hongyixin Automobile Electronic Technology Co ltd
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Application filed by Guangdong Hongyixin Automobile Electronic Technology Co ltd filed Critical Guangdong Hongyixin Automobile Electronic Technology Co ltd
Priority to CN202210355295.9A priority Critical patent/CN114866077A/en
Publication of CN114866077A publication Critical patent/CN114866077A/en
Priority to CN202211386035.4A priority patent/CN115765694A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
    • H02H7/205—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment for controlled semi-conductors which are not included in a specific circuit arrangement
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H02H9/025—Current limitation using field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0027—Measuring means of, e.g. currents through or voltages across the switch
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0054—Gating switches, e.g. pass gates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)

Abstract

The invention provides a driving circuit and electronic equipment of a power tube, wherein the power tube is an NMOS tube, the drain electrode of the power tube is connected with a power supply, and the source electrode of the power tube is grounded through a load; the driving circuit includes: the monitoring system comprises a monitoring pipe, a monitoring module and a flow limiting control module; the monitoring tube is the same as the power tube in type; the monitoring tube is connected in series with the monitoring module and then connected in parallel between the source electrode and the drain electrode of the power tube; the monitoring module is configured to: when the current to be measured passing through the monitoring tube is larger than a preset current threshold value, triggering the current limiting control module; the current to be measured is adapted to the current of the power tube and changes; the current limiting control module is configured to: and reducing the current of the power tube in response to the trigger.

Description

Driving circuit of power tube and electronic equipment
Technical Field
The present invention relates to the field of driving power transistors, and in particular, to a driving circuit of a power transistor and an electronic device.
Background
In the prior art, an NMOS tube and a load can be connected in series between a power supply and a reference ground in sequence; the NMOS tube can be a high-side NMOS tube, the grid electrode of the NMOS tube is connected with the driving circuit, and the NMOS tube can be used for driving resistive and inductive loads.
In practical application, when the output is short-circuited and grounded, the current of the NMOS tube is too large, which brings potential safety hazard.
Disclosure of Invention
The invention provides a driving circuit of a power tube and electronic equipment, which aim to solve the problem of lack of means capable of effectively coping with short-circuit errors.
According to a first aspect of the present invention, a driving circuit of a power tube is provided, the power tube is an NMOS tube, a drain of the power tube is connected to a power supply, and a source of the power tube is grounded through a load;
the driving circuit includes: the monitoring system comprises a monitoring pipe, a monitoring module and a flow limiting control module; the monitoring tube is the same as the power tube in type; the monitoring tube is connected in series with the monitoring module and then connected in parallel between the source electrode and the drain electrode of the power tube;
the monitoring module is configured to:
when the current to be measured passing through the monitoring tube is larger than a preset current threshold value, triggering the current limiting control module; the current to be measured is adapted to the current of the power tube and changes;
the current limiting control module is configured to:
and reducing the current of the power tube in response to the trigger.
Optionally, the monitoring module includes a monitoring resistance and voltage drop monitoring unit;
the monitoring resistor is connected in series with the monitoring tube and then connected in parallel between the source electrode and the drain electrode of the power tube; the voltage drop monitoring unit is connected with the monitoring resistor and the current limiting control module;
the pressure drop monitoring unit is used for:
and monitoring the current to be detected by monitoring the voltage drop at two ends of the monitoring resistor, and triggering the current limiting control module when the current to be detected is greater than the current threshold value.
Optionally, the voltage drop monitoring unit includes a first transistor, a first current source, a second transistor, and a second current source;
the control end of the first transistor is connected with the control end of the second transistor, the first current source is connected with the first transistor in series, and the second current source is connected with the second transistor in series; the first transistor is connected with a first end of the monitoring resistor, the second transistor is connected with a second end of the monitoring resistor, and the second end of the monitoring resistor is one end of the monitoring resistor connected with the monitoring tube; the current limiting control module is connected between the first transistor and the first current source;
the pressure drop monitoring unit is configured to:
when the current to be measured is larger than the current threshold, a current difference is formed between the current flowing through the first transistor and the current of the first current source, and the current difference directly or indirectly acts on the current limiting control module to trigger the current limiting control module.
Optionally, the first transistor and the second transistor are both triodes;
the emitter of the first transistor is connected with the first end of the monitoring resistor, the collector of the first transistor is grounded through the first current source or connected with the input power supply of the driving circuit, and the collector of the first transistor is also connected with the current limiting control module so as to trigger the current limiting control module through the current difference;
the emitter of the second transistor is connected with the second end of the monitoring resistor, and the collector of the second transistor is grounded or connected with the input power supply through the second current source.
Optionally, the first transistor and the second transistor are both PNP triodes; the monitoring resistor is connected to the source electrode of the monitoring tube; the collector of the first transistor is grounded through the first current source; the collector of the second transistor is grounded via the second current source.
Optionally, the first transistor and the second transistor are both NPN triodes; the monitoring resistor is connected to the drain electrode of the monitoring tube; the collector of the first transistor is connected to the input power source via the first current source, and the collector of the second transistor is connected to the input power source via the second current source.
Optionally, the driving circuit further includes a main driving module, and an output end of the main driving module is connected to the gate of the power transistor to output a driving current and a driving voltage;
the current limiting control module is specifically configured to:
in response to the trigger, pulling down the drive voltage such that: the current of the power tube drops along with the pulling-down of the driving voltage.
Optionally, after the driving voltage is pulled down, the current of the power tube can be reduced to a specified current range or a specified current value under the cooperation of the main driving module.
Optionally, the current-limiting control module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor;
the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are both connected to an input power supply of the driving circuit, the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are connected with each other, and the drain electrode of the first PMOS tube is directly or indirectly connected with the monitoring module so as to directly or indirectly respond to the triggering of the monitoring module; the drain electrode and the grid electrode of the first PMOS tube are mutually connected;
the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are both connected with the source electrode of the power tube, the grid electrode of the first NMOS tube is mutually connected with the grid electrode of the second NMOS tube, the drain electrode of the second NMOS tube is connected with the grid electrode of the power tube so as to be conducted when the first PMOS tube responds to the current difference to pull down the driving voltage, and the drain electrode of the first NMOS tube is mutually connected with the grid electrode.
Optionally, the current limiting control module further includes a trigger response unit, and the trigger response unit is connected between the drain of the first PMOS transistor and the monitoring module;
the trigger response unit is used for:
and acquiring a current difference or current generated by the monitoring module because the current to be detected is greater than a current threshold, and forming corresponding current in the first PMOS tube so as to enable the first PMOS tube to respond to the trigger.
Optionally, the trigger response unit includes a third NMOS transistor and a fourth NMOS transistor;
the drain electrode of the third NMOS tube is connected with the monitoring module to obtain a current difference or current generated by the monitoring module because the current to be detected is greater than a current threshold value;
the source electrode of the third NMOS tube is grounded with the source electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the first PMOS tube.
Optionally, the flow limiting control module is further configured to:
controlling the main driving module to reduce the driving current in response to the trigger.
Optionally, the current-limiting control module includes a first PMOS transistor and a third PMOS transistor;
the source electrode of the first PMOS tube and the source electrode of the third PMOS tube are both connected to an input power supply of the driving circuit, the grid electrode of the first PMOS tube and the grid electrode of the third PMOS tube are connected with each other, the drain electrode of the third PMOS tube is connected with the main driving module, and when the first PMOS tube responds to the trigger, the main driving module is controlled to reduce the driving current; the drain electrode of the first PMOS tube is directly or indirectly connected with the monitoring module so as to directly or indirectly respond to the triggering of the monitoring module; and the drain electrode and the grid electrode of the first PMOS tube are mutually connected.
Optionally, the main driving module includes a current bias unit, a power tube driving unit, a floating voltage generating unit, and a power tube discharging unit for discharging a gate of the power tube;
the current bias unit is connected with a bias current source and used for generating bias current based on the current of the bias current source;
the floating voltage generating unit is directly or indirectly connected between the source electrode of the power tube and an input power supply of the driving circuit to generate a floating voltage, and the floating voltage and the voltage of the source electrode of the power tube are kept in a specified voltage difference or a specified voltage difference range;
the output end of the power tube driving unit is connected with the grid electrode of the power tube and the grid electrode of the monitoring tube;
the power tube driving unit is used for:
outputting the drive current based on the bias current;
outputting the driving voltage based on the floating voltage.
Optionally, the current bias unit includes a fourth PMOS transistor and a fifth PMOS transistor;
the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are connected with an input power supply of the driving circuit, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fifth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the bias current source, the drain electrode of the fifth PMOS tube is connected with the power tube driving unit so as to feed back the bias current to the power tube driving unit, and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the fourth PMOS tube.
Optionally, the current bias unit includes a fourth PMOS transistor and a sixth PMOS transistor;
the drain electrode of the fourth PMOS tube and the source electrode of the sixth PMOS tube are connected with an input power supply of the driving circuit, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the bias current source, and the drain electrode of the sixth PMOS tube is connected with the floating voltage generating unit so as to output bias current to the floating voltage generating unit, so that the floating voltage generating unit generates the bias voltage.
Optionally, the floating voltage generating unit includes a zener diode, an anode of the zener diode is connected to the source of the power transistor, a cathode of the zener diode is connected to the drain of the sixth PMOS transistor and the power transistor driving unit, and a reverse breakdown voltage of the zener diode is matched to the specified voltage difference or the specified voltage difference range.
Optionally, the power tube driving unit includes: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a seventh PMOS transistor and an eighth PMOS transistor;
the drain electrode of the fifth NMOS transistor is connected with the current bias unit to obtain the bias current, the source electrode of the fifth NMOS transistor and the source electrode of the sixth NMOS transistor are connected with the source electrode of the power transistor, the gate electrode of the fifth NMOS transistor is connected with the gate electrode of the sixth NMOS transistor, the drain electrodes of the sixth NMOS transistor are respectively connected with the source electrode of the seventh NMOS transistor and the source electrode of the eighth NMOS transistor, the drain electrode of the seventh NMOS transistor is connected with the input power supply of the driving circuit through the seventh PMOS transistor, the drain electrode of the eighth NMOS transistor is connected with the input power supply through the eighth PMOS transistor, the gate electrode of the seventh PMOS transistor is connected with the gate electrode of the eighth PMOS transistor, the gate electrode and the drain electrode of the seventh PMOS transistor are connected with each other, the gate electrode of the seventh NMOS transistor is connected with the floating voltage generation unit to obtain the bias voltage, and the gate electrode of the eighth NMOS transistor is connected with the gate electrodes of the power transistor and the monitoring transistor, to output the driving current and the driving voltage.
Optionally, after the current limiting control module pulls down the driving voltage, the current of the power tube may be fixed in a specified current range or at a specified current value under the combined action of the current of the second NMOS tube, the current of the eighth PMOS tube, and the current of the power tube discharging unit.
Optionally, in a case that the current limiting control module is further configured to control the main driving module to decrease the driving current in response to the trigger, the current of the seventh PMOS transistor can decrease under the control of the current limiting control module, so that the driving current decreases accordingly.
Optionally, the power tube discharge unit includes a discharge resistor connected between the gate and the source of the power tube.
Optionally, the size of the monitoring tube is smaller than that of the power tube.
Optionally, the power transistor is a high-side NMOS transistor.
According to a second aspect of the present invention, there is provided an electronic device including the driving circuit and the power transistor according to the first aspect and the optional aspects thereof.
In the driving circuit and the electronic equipment of the power tube, the monitoring module can be used for comparing the current to be detected of the monitoring tube with the current threshold, and further, when a short-circuit error occurs, the current to be detected is usually larger than the current threshold, so that the dangerous condition that the short-circuit error possibly occurs can be found in time through the monitoring of the monitoring module.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic circuit diagram of an electronic device in an exemplary embodiment of the invention;
FIG. 2 is a schematic circuit diagram of an electronic device in another exemplary embodiment of the invention;
FIG. 3 is a schematic circuit diagram of an electronic device in a further exemplary embodiment of the invention;
FIG. 4 is a schematic circuit diagram of an electronic device in yet another exemplary embodiment of the invention;
FIG. 5 is a circuit schematic of a driver circuit in an exemplary embodiment of the invention;
fig. 6 is a circuit schematic of a driver circuit in another exemplary embodiment of the invention.
Description of reference numerals:
100-a drive circuit; 110-a current limit control module; 111-trigger response unit; 120-a monitoring module; 121-pressure drop monitoring unit; 130-a main drive module; 131-a power tube driving unit; 132-a current bias unit; 133-a floating voltage generating unit; 134-power tube discharge unit;
m0-power tube; m1-monitoring tube;
r1-monitor resistance; rload-load; r0-discharge resistance;
MN 1-first NMOS transistor; MN 2-second NMOS transistor; MN 3-third NMOS transistor; MN 4-fourth NMOS transistor; MN 5-fifth NMOS transistor; MN 6-sixth NMOS transistor; MN 7-seventh NMOS transistor; MN 8-eighth NMOS transistor;
MP 1-first PMOS tube; MP 2-second PMOS tube; MP 3-third PMOS tube;
MP 4-fourth PMOS tube; MP 5-fifth PMOS tube; MP 6-sixth PMOS tube; MP 7-seventh PMOS tube; MP 8-eighth PMOS tube;
i1 — a first current source; i2 — second current source; ibias-a bias current source;
d0-zener diode.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "upper surface", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
In the description of the present invention, "a plurality" means a plurality, e.g., two, three, four, etc., unless specifically limited otherwise.
In the description of the present invention, unless otherwise explicitly specified or limited, the term "connected" and the like are to be understood broadly, and may be, for example, fixedly connected, detachably connected, or integrated; may be mechanically, electrically or otherwise in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Referring to fig. 1, an embodiment of the invention provides an electronic device, which includes a power transistor M0 and a driving circuit 100.
The power tube M0 is an NMOS tube, the drain of the power tube M0 is connected to a power supply, and the source of the power tube M0 is grounded via a load Rload; further, the power transistor M0 may be a high-side NMOS transistor that needs to be driven, and the high-side NMOS transistor is used for driving resistive and inductive loads. In practical application, when the output has a short-circuit ground fault, the high-side NMOS transistor needs to be turned off or the output current needs to be limited.
In order to implement current limiting, the driving circuit 100 includes: monitoring pipe M1, monitoring module 120, flow limiting control module 110.
The type of the monitoring tube M1 is the same as that of the power tube M0, further for example, the size of the monitoring tube M1 is smaller than that of the power tube M0, the specific size ratio can be arbitrarily set according to requirements without departing from the scope of the embodiment of the present invention, the current of the monitoring tube M1 can be understood as the current to be detected that needs to be monitored by the monitoring module 120, and further, the current to be detected is adapted to the current of the power tube M0 to change; specifically, the current reduction ratio between the power tube M0 and the monitor tube M1 is the size ratio between the power tube M0 and the monitor tube M1.
The monitoring tube M1 and the monitoring module 120 are connected in series and then connected in parallel between the source and the drain of the power tube M0; in the example shown in fig. 2 to 5, the monitor module 120 is connected to the drain of the monitor transistor M1 (specifically, the monitor resistor R1 is connected to the drain of the monitor transistor M1), and in the example shown in fig. 6, the monitor module 120 is connected to the source of the monitor transistor M1 (specifically, the monitor resistor R1 is connected to the source of the monitor transistor M1).
The monitoring module 120 is configured to:
when the current to be measured passing through the monitoring pipe M1 is greater than a preset current threshold, triggering the current limiting control module 110;
the current threshold may be any preset value, for example, may be designed with reference to a current that may be formed during a short-circuit error; in addition, the VGS voltage of the power transistor M0 at the miller stage can be determined according to the load condition in the application, and the current threshold should be designed to avoid affecting the operation of the miller stage of M0.
The flow limiting control module 110 is configured to:
and reducing the current of the power tube M0 in response to the trigger.
Any means capable of reducing the current of the power transistor M0 may be used as an alternative in the art.
In the above scheme, usable monitoring module realizes the comparison of the electric current that awaits measuring of monitoring pipe and current threshold value, and then, when taking place the short circuit error, the electric current that awaits measuring is greater than current threshold value usually, so, through monitoring of monitoring module, can in time discover the dangerous condition that probably takes place the short circuit error, on this basis, through the electric current reduction effect of current limiting control module, when the output takes place the short circuit ground error quick restriction output current, effective guarantee security.
In one embodiment, referring to fig. 4, 5 and 6, the monitoring module 120 includes a monitoring resistor R1 and a voltage drop monitoring unit 121;
the monitoring resistor R1 is connected in series with the monitoring tube M1 and then connected in parallel between the source and the drain of the power tube M0; the voltage drop monitoring unit 121 is connected with the monitoring resistor R1 and the current limiting control module 110;
the pressure drop monitoring unit 121 is configured to:
the current to be measured is monitored by monitoring the voltage drop across the monitoring resistor R1, and when the current to be measured is greater than the current threshold, the current limiting control module 110 is triggered.
In the above scheme, the accurate, effective and timely monitoring of the current to be detected can be realized by introducing the monitoring resistor and monitoring the voltage drop of the monitoring resistor.
In a further scheme, the voltage drop monitoring unit 121 includes a first transistor Q0, a first current source I1, a second transistor Q1, and a second current source I2;
a control end of the first transistor Q0 is connected with a control end of the second transistor Q1, the first current source I1 is connected in series with the first transistor Q0, and the second current source I2 is connected in series with the second transistor Q1; the first transistor Q0 is connected to a first end of the monitor resistor R1, the second transistor Q1 is connected to a second end of the monitor resistor R1, and a second end of the monitor resistor R1 is the end of the monitor resistor R1 connected to the monitor transistor M1; the current limiting control module 110 is connected between the first transistor Q0 and the first current source I1;
the pressure drop monitoring unit 121 is configured to:
when the current to be measured is greater than the current threshold, a current difference is formed between the current flowing through the first transistor Q0 and the current of the first current source I1, and the current difference directly or indirectly acts on the current limiting control module 110 to trigger the current limiting control module 110.
The first transistor Q0 and the second transistor Q1 are both triodes; in other examples, the first transistor and the second transistor may also be implemented by MOS transistors (for example, PMOS transistors).
In the case of using a triode, taking fig. 5 and fig. 6 as an example, an emitter of the first transistor Q0 is connected to the first end of the monitoring resistor R1, a collector of the first transistor Q0 is grounded via the first current source I1 or connected to the input power supply VCP of the driving circuit 100, and a collector of the first transistor Q0 is further connected to the current limiting control module 110, so as to trigger the current limiting control module 110 through the current difference;
the emitter of the second transistor Q1 is connected to the second terminal of the monitor resistor R1, and the collector of the second transistor Q1 is connected to ground or the input power source VCP via the second current source I2.
If the first transistor Q0 and the second transistor Q1 are both PNP transistors, then: for example, as shown in fig. 5, the monitor resistor R1 is connected to the source of the monitor transistor M1; the collector of the first transistor Q0 is connected to ground via the first current source I1; the collector of the second transistor Q1 is connected to ground via the second current source I2.
If the first transistor Q0 and the second transistor Q1 are both NPN transistors, then: taking fig. 6 as an example, the monitor resistor R1 is connected to the drain of the monitor transistor M1; the collector of the first transistor Q0 is connected to the input power source VCP via the first current source I1, and the collector of the second transistor Q1 is connected to the input power source VCP via the second current source I2.
In the scheme shown in fig. 5, the first current source I1 and the second current source I2 do not consume the power of the input power VCP when the current is not limited, while in the scheme shown in fig. 6, the current of the first current source I1 and the second current source I2 always consumes the power of VCP when the current is not limited, and in comparison, the scheme shown in fig. 5 can achieve lower power consumption.
The specific implementation process of the above scheme is as follows:
the first transistor Q0 and the second transistor Q1 monitor the current to be measured of the monitoring tube M1 through the voltage drop on the monitoring resistor R1;
wherein, VEB _ Q0 ═ VR1+ VEB _ Q1;
VEB _ Q0 is the voltage between the emitter and the base of the first transistor Q0;
VEB _ Q1 is the voltage between the emitter and the base of the second transistor Q1;
VR1 is the voltage drop of the monitoring resistor R1;
furthermore, the larger the current of the monitoring tube M1, the larger the voltage drop VR1 of the monitoring resistor, and the larger the current of the first transistor Q0 (which may be a proportional relationship, for example), when the current of the first transistor Q0 is larger than the current of the first current source I1, the current limiting may be started; wherein:
when the current of the monitoring transistor M1 (i.e., the current to be measured) is smaller than the preset current threshold, the current of the first transistor Q0 is smaller than the current of the first current source I1, at this time, the current-limiting control module 110 is not triggered (for example, the current mirror formed by the third NMOS transistor MN3 and the fourth NMOS transistor MN4 is turned off by the first current source I1), and the current-limiting control module does not consume the current of the input power supply VCP (for example, a charge pump);
when the current of the monitoring transistor M1 (i.e., the current to be measured) is greater than the preset current threshold, the current of the first transistor Q0 is greater than the current of the first current source I1, and the excess current (i.e., the current difference) can affect the driving action of the driving circuit (e.g., the driving action of the power transistor M0 is affected by the current mirror formed by the third NMOS transistor MN3 and the fourth NMOS transistor MN4, the current mirror formed by the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3, the current mirror formed by the first NMOS transistor MN1 and the second NMOS transistor MN 2), and further, the response of the current-limiting control module to the trigger can be interpreted as the acquisition and response of the excess current, and the trigger of the monitoring module to the current-limiting control module can be interpreted as the output of the excess current.
In other schemes, the function of the voltage drop monitoring unit 121 can also be implemented by using a comparator.
In one embodiment, the driving circuit 100 further includes a main driving module 130, wherein an output end of the main driving module 130 is connected to the gate of the power transistor M0 to output a driving current and a driving voltage;
the flow limiting control module 110 is specifically configured to:
in response to the trigger, pulling down the drive voltage such that: the current of the power tube M0 decreases as the driving voltage is pulled low.
In some embodiments, after the driving voltage is pulled down, the current of the power transistor M0 can be reduced to a specified current range or a specified current value under the cooperation of the main driving module 130, so that the current limiting effect can be effectively improved, and the safety can be guaranteed. In other embodiments, the current limiting control module 110 may only implement the current reduction of the power transistor M0 without reducing the current to be within a specified current range or a specified current value.
In a further example, referring to fig. 5 and fig. 6, the current limiting control module 110 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN 2;
the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are both connected to the input power VCP of the driving circuit 100, the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 are connected to each other, and the drain of the first PMOS transistor MP1 is directly or indirectly connected to the monitoring module 120, so as to directly or indirectly respond to the triggering of the monitoring module 120; the drain electrode and the gate electrode of the first PMOS tube MP1 are connected with each other;
the drain of the second PMOS transistor MP2 is connected to the drain of the first NMOS transistor MN1, the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are both connected to the source of the power transistor M0, the gate of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN2, the drain of the second NMOS transistor MN2 is connected to the gate of the power transistor M0, so that the first PMOS transistor MP1 is turned on when responding to the current difference to pull down the driving voltage, and the drain of the first NMOS transistor MN1 is connected to the gate.
Further, if the monitor resistor R1 is disposed at the drain of the monitor transistor M1, then: taking the circuit shown in fig. 5 as an example, the current limiting control module 110 further includes a trigger response unit 111, and the trigger response unit 111 is connected between the drain of the first PMOS transistor MP1 and the monitoring module 120;
the trigger response unit 111 is configured to:
obtaining a current difference or a current generated by the monitoring module 120 due to the current to be measured being greater than a current threshold, and forming a corresponding current in the first PMOS transistor MP1, so that the first PMOS transistor MP1 responds to the trigger.
For example, referring to fig. 5, the trigger response unit 111 includes a third NMOS transistor MN3 and a fourth NMOS transistor MN 4;
the drain of the third NMOS transistor MN3 is connected to the monitoring module 120, so as to obtain a current difference or a current generated by the monitoring module 120 due to the current to be measured being greater than a current threshold;
the source electrode of the third NMOS transistor MN3 is grounded to the source electrode of the fourth NMOS transistor MN4, the gate electrode of the third NMOS transistor MN3 is connected to the gate electrode of the fourth NMOS transistor MN4, and the drain electrode of the fourth NMOS transistor MN4 is connected to the drain electrode of the first PMOS transistor MP 1.
In some embodiments, in addition to the function of reducing the current of the power transistor M0, the current limiting control module 110 is further configured to: in response to the trigger, the main driving module 130 is controlled to reduce the driving current. By reducing the driving current (also understood as charging current) of the power tube M0, the gate of the power tube M0 can be pulled down quickly, the establishment time of the current limiting loop is shortened, and the current load of the input power supply (such as a charge pump) is reduced during the establishment of the current limiting loop, so that the power consumption of the driving current is reduced.
Further, the current limiting control module 110 further includes a third PMOS transistor MP 3;
a source of the third PMOS transistor MP3 is connected to an input power VCP of the driving circuit 100, a gate of the first PMOS transistor MP1 is connected to a gate of the third PMOS transistor MP3, a drain of the third PMOS transistor MP3 is connected to the main driving module 130, and when the first PMOS transistor MP1 responds to the trigger, the main driving module is controlled to reduce the driving current; the drain of the first PMOS transistor MP1 is directly or indirectly connected to the monitoring module 120 to directly or indirectly respond to the triggering of the monitoring module 120; the drain and the gate of the first PMOS transistor MP1 are connected to each other.
In one embodiment, referring to fig. 4, 5 and 6, the main driving module 130 includes a current bias unit 132, a power transistor driving unit 131, a floating voltage generating unit 133, and a power transistor discharging unit 134 for discharging the gate of the power transistor M0;
the current bias unit 132 is connected to a bias current source Ibias, and is configured to generate a bias current based on a current of the bias current source Ibias;
the floating voltage generating unit 133 is directly or indirectly connected between the source of the power transistor M0 and the input power VCP of the driving circuit 100 to generate a floating voltage, which is maintained at a specified voltage difference or within a specified voltage difference range from the voltage of the source of the power transistor M0;
the output end of the power tube driving unit 131 is connected with the gate of the power tube M0 and the gate of the monitoring tube M1;
the power tube driving unit 131 is configured to:
outputting the drive current based on the bias current;
outputting the driving voltage based on the floating voltage.
In a specific example, the current bias unit 132 includes a fourth PMOS transistor MP4 and a fifth PMOS transistor MP 5;
a source of the fourth PMOS transistor MP4 and a source of the fifth PMOS transistor MP5 are connected to an input power VCP of the driving circuit 100, a gate of the fourth PMOS transistor MP4 is connected to a gate of the fifth PMOS transistor MP5, a drain of the fourth PMOS transistor MP4 is connected to the bias current source, a drain of the fifth PMOS transistor MP5 is connected to the power transistor driving unit 131 to feed back the bias current to the power transistor driving unit 131, and a gate and a drain of the fourth PMOS transistor MP4 are connected to each other.
In addition, the generation of the bias voltage of the floating voltage generating unit may also be generated via a bias current, the current bias unit 132 includes a fourth PMOS transistor MP4 and a sixth PMOS transistor MP 6;
the drain of the fourth PMOS transistor MP4 and the source of the sixth PMOS transistor MP6 are connected to the input power VCP of the driving circuit 100, the gate of the fourth PMOS transistor MP4 and the gate of the sixth PMOS transistor MP6 are connected to each other, the drain of the fourth PMOS transistor MP4 is connected to the bias current source, and the drain of the sixth PMOS transistor MP6 is connected to the floating voltage generating unit 133 to output a bias current to the floating voltage generating unit 133, so that the floating voltage generating unit 133 generates the bias voltage.
In one implementation of the floating voltage generating unit 133, the floating voltage generating unit 133 includes a zener diode D0, an anode of the zener diode D0 is connected to the source of the power transistor M0, a cathode of the zener diode D0 is connected to the drain of the sixth PMOS transistor MP6 and the power transistor driving unit 131, and a reverse breakdown voltage of the zener diode D0 is matched to the specified voltage difference or the specified voltage difference range.
Correspondingly, the power tube driving unit 131 includes: a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a seventh PMOS transistor MP7, and an eighth PMOS transistor MP 8;
a drain of the fifth NMOS transistor MN5 is connected to the current bias unit 132 to obtain the bias current, a source of the fifth NMOS transistor MN5 and a source of the sixth NMOS transistor MN6 are connected to a source of the power transistor M0, a gate of the fifth NMOS transistor MN5 is connected to a gate of the sixth NMOS transistor MN6, drains of the sixth NMOS transistor MN6 are respectively connected to a source of the seventh NMOS transistor MN7 and a source of the eighth NMOS transistor MN8, a drain of the seventh NMOS transistor MN7 is connected to the input power VCP of the driving circuit 100 through the seventh PMOS transistor MP7, a drain of the eighth NMOS transistor MN8 is connected to the input power VCP through the eighth PMOS transistor MP8, a gate of the seventh NMOS transistor MP7 is connected to a gate of the eighth PMOS transistor MP8, a gate and a drain of the seventh PMOS transistor MP7 are connected to each other, a gate of the seventh NMOS transistor MN7 is connected to the VCP to generate the floating voltage, and the bias unit 133, the gate of the eighth NMOS transistor MN8 is connected to the gates of the power transistor M0 and the monitoring transistor M1, so as to output the driving current and the driving voltage.
The power tube discharge unit 134 comprises a discharge resistor R0 connected between the gate and the source of the power tube M0.
It can be seen that:
the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 provide the bias current required for driving. The current of the sixth PMOS transistor MP6 flows through the zener diode D0 to generate a SOURCE +5V bias voltage. The current mirror composed of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 is used for providing bias current for the input stages of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8, and the current mirror composed of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 is a load for the input stages of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN 8. The discharge resistor R0 can be used to turn off the power transistor M0.
When the power transistor M0 is turned on, the error amplifier actually capable of controlling the charging current drives the gate voltage of the power transistor, and at this time, the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 may be regarded as the common-source differential pair input electrodes of the error amplifier.
The specific working principle of the main driving module 130 is as follows:
when the power transistor M0 needs to be turned on, the current of the bias current source Ibias is provided to the fourth PMOS transistor MP4 for driving, the VGS voltage of the power transistor M0 is 0V, the charging current (i.e., the driving current) of the gate of the power transistor M0 is determined by the current mirror of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5, the current mirror of the fourth PMOS transistor MP4 and the sixth PMOS transistor MP6, the current mirror ratio of the current mirror of the fifth PMOS transistor MP5 and the current mirror of the sixth PMOS transistor MP6, the magnitude of the current of the bias current source Ibias, and the discharging resistor R0. When the gate voltage of the power tube M0 is charged to VS +5V, the charging is stopped.
In the case where the upper flow control module 110 is combined with the main drive module 130:
if the method is implemented: after the current limiting control module 110 pulls down the driving voltage, the current of the power tube M0 is fixed within a specified current range or at a specified current value, then:
after the current limiting control module 110 pulls down the driving voltage, the current of the power transistor M0 can be fixed within a specified current range or a specified current value under the combined action of the current of the second NMOS transistor MN2, the current of the eighth PMOS transistor MP8 and the current of the power transistor discharge unit 134; for example: the current mirrors of the first NMOS transistor MN1 and the second NMOS transistor MN2 directly pull down the gate voltage of the power transistor M0, and when the current of the second NMOS transistor MN2 passes through the current-limiting loop and matches the charging and discharging currents of the eighth PMOS transistor MP8 and the discharging resistor R0, the current of the power transistor M0 (or the monitoring transistor M1) is fixed at a preset value (i.e., a specified current value).
If the method is implemented: when the current limiting control module 110 controls the main driving module 130 to reduce the driving current in response to the trigger, then:
the current of the seventh PMOS transistor MP7 can be decreased under the control of the current limiting control module 110, so that the driving current is decreased accordingly. For example: the drain electrode of the third PMOS transistor MP3 may be connected to the drain electrode of the seventh PMOS transistor MP7, and the third PMOS transistor MP3 may reduce the current of the eighth PMOS transistor MP8 by reducing the current of the seventh PMOS transistor MP7 when a short circuit occurs and a current limiting loop is established.
In a specific example, the monitoring resistor R1 may be designed to be several tens of ohms, the only high-resistance point of the current-limiting loop is the gate of the power transistor M0, the product point of the gate of the power transistor M0 is the dominant pole, and the single product point in the bandwidth does not need to be compensated for the loop additionally.
In the description herein, reference to the terms "an implementation," "an embodiment," "a specific implementation," "an example" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (24)

1. A driving circuit of a power tube is characterized in that the power tube is an NMOS tube, a drain electrode of the power tube is connected with a power supply, and a source electrode of the power tube is grounded through a load;
it is characterized in that the preparation method is characterized in that,
the driving circuit includes: the monitoring system comprises a monitoring pipe, a monitoring module and a flow limiting control module; the monitoring tube is the same as the power tube in type; the monitoring tube is connected in series with the monitoring module and then connected in parallel between the source electrode and the drain electrode of the power tube;
the monitoring module is configured to:
when the current to be measured passing through the monitoring tube is larger than a preset current threshold value, triggering the current limiting control module; the current to be measured is adapted to the current of the power tube and changes;
the current limiting control module is configured to:
and reducing the current of the power tube in response to the trigger.
2. The driving circuit according to claim 1, wherein the monitoring module comprises a monitoring resistance and voltage drop monitoring unit;
the monitoring resistor is connected in series with the monitoring tube and then connected in parallel between the source electrode and the drain electrode of the power tube; the voltage drop monitoring unit is connected with the monitoring resistor and the current limiting control module;
the pressure drop monitoring unit is used for:
and monitoring the current to be detected by monitoring the voltage drop at two ends of the monitoring resistor, and triggering the current limiting control module when the current to be detected is greater than the current threshold value.
3. The driving circuit according to claim 2, wherein the voltage drop monitoring unit comprises a first transistor, a first current source, a second transistor and a second current source;
the control end of the first transistor is connected with the control end of the second transistor, the first current source is connected with the first transistor in series, and the second current source is connected with the second transistor in series; the first transistor is connected with a first end of the monitoring resistor, the second transistor is connected with a second end of the monitoring resistor, and the second end of the monitoring resistor is one end of the monitoring resistor connected with the monitoring tube; the current-limiting control module is connected between the first transistor and the first current source;
the pressure drop monitoring unit is configured to:
when the current to be measured is larger than the current threshold, a current difference is formed between the current flowing through the first transistor and the current of the first current source, and the current difference directly or indirectly acts on the current limiting control module to trigger the current limiting control module.
4. The driving circuit according to claim 3, wherein the first transistor and the second transistor are both triodes;
the emitter of the first transistor is connected with the first end of the monitoring resistor, the collector of the first transistor is grounded through the first current source or connected with the input power supply of the driving circuit, and the collector of the first transistor is also connected with the current limiting control module so as to trigger the current limiting control module through the current difference;
the emitter of the second transistor is connected with the second end of the monitoring resistor, and the collector of the second transistor is grounded or connected with the input power supply through the second current source.
5. The driving circuit according to claim 4, wherein the first transistor and the second transistor are both PNP transistors; the monitoring resistor is connected to the source electrode of the monitoring tube; the collector of the first transistor is grounded through the first current source; the collector of the second transistor is grounded via the second current source.
6. The driving circuit according to claim 4, wherein the first transistor and the second transistor are both NPN transistors; the monitoring resistor is connected to the drain electrode of the monitoring tube; the collector of the first transistor is connected to the input power source via the first current source, and the collector of the second transistor is connected to the input power source via the second current source.
7. The driving circuit according to claim 1, further comprising a main driving module, wherein an output terminal of the main driving module is connected to the gate of the power transistor to output a driving current and a driving voltage;
the current limiting control module is specifically configured to:
in response to the trigger, pulling down the drive voltage such that: the current of the power tube drops along with the pulling-down of the driving voltage.
8. The drive circuit according to claim 7,
after the driving voltage is pulled down, the current of the power tube can be reduced to a specified current range or a specified current value under the cooperation of the main driving module.
9. The driving circuit of claim 7, wherein the current limiting control module comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor;
the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are both connected to an input power supply of the driving circuit, the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube are connected with each other, and the drain electrode of the first PMOS tube is directly or indirectly connected with the monitoring module so as to directly or indirectly respond to the triggering of the monitoring module; the drain electrode and the grid electrode of the first PMOS tube are mutually connected;
the drain electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are both connected with the source electrode of the power tube, the grid electrode of the first NMOS tube is mutually connected with the grid electrode of the second NMOS tube, the drain electrode of the second NMOS tube is connected with the grid electrode of the power tube so as to be conducted when the first PMOS tube responds to the current difference to pull down the driving voltage, and the drain electrode of the first NMOS tube is mutually connected with the grid electrode.
10. The driving circuit of claim 9, wherein the current limiting control module further comprises a trigger response unit connected between the drain of the first PMOS transistor and the monitoring module;
the trigger response unit is used for:
and acquiring a current difference or current generated by the monitoring module because the current to be detected is greater than a current threshold, and forming corresponding current in the first PMOS tube so as to enable the first PMOS tube to respond to the trigger.
11. The driving circuit of claim 10, wherein the trigger response unit comprises a third NMOS transistor and a fourth NMOS transistor;
the drain electrode of the third NMOS tube is connected with the monitoring module to obtain a current difference or current generated by the monitoring module because the current to be detected is greater than a current threshold value;
the source electrode of the third NMOS tube is grounded with the source electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the first PMOS tube.
12. The drive circuit according to claim 8,
the flow limiting control module is further configured to:
and controlling the main driving module to reduce the driving current in response to the trigger.
13. The driving circuit of claim 12, wherein the current limiting control module comprises a first PMOS transistor and a third PMOS transistor;
the source electrode of the first PMOS tube and the source electrode of the third PMOS tube are both connected to an input power supply of the driving circuit, the grid electrode of the first PMOS tube and the grid electrode of the third PMOS tube are connected with each other, the drain electrode of the third PMOS tube is connected with the main driving module, and when the first PMOS tube responds to the trigger, the main driving module is controlled to reduce the driving current; the drain electrode of the first PMOS tube is directly or indirectly connected with the monitoring module so as to directly or indirectly respond to the triggering of the monitoring module; and the drain electrode and the grid electrode of the first PMOS tube are mutually connected.
14. The driving circuit according to claim 9, wherein the main driving module comprises a current bias unit, a power tube driving unit, a floating voltage generating unit, and a power tube discharging unit for discharging a gate of the power tube;
the current bias unit is connected with a bias current source and used for generating bias current based on the current of the bias current source;
the floating voltage generating unit is directly or indirectly connected between the source electrode of the power tube and an input power supply of the driving circuit to generate a floating voltage, and the floating voltage and the voltage of the source electrode of the power tube are kept in a specified voltage difference or a specified voltage difference range;
the output end of the power tube driving unit is connected with the grid electrode of the power tube and the grid electrode of the monitoring tube;
the power tube driving unit is used for:
outputting the drive current based on the bias current;
outputting the driving voltage based on the floating voltage.
15. The driving circuit of claim 14, wherein the current bias unit comprises a fourth PMOS transistor and a fifth PMOS transistor;
the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are connected with an input power supply of the driving circuit, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fifth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the bias current source, the drain electrode of the fifth PMOS tube is connected with the power tube driving unit so as to feed back the bias current to the power tube driving unit, and the grid electrode of the fourth PMOS tube is connected with the drain electrode of the fourth PMOS tube.
16. The driving circuit of claim 14, wherein the current bias unit comprises a fourth PMOS transistor and a sixth PMOS transistor;
the drain electrode of the fourth PMOS tube and the source electrode of the sixth PMOS tube are connected with an input power supply of the driving circuit, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the bias current source, and the drain electrode of the sixth PMOS tube is connected with the floating voltage generating unit so as to output bias current to the floating voltage generating unit, so that the floating voltage generating unit generates the bias voltage.
17. The driving circuit of claim 16, wherein the floating voltage generating unit comprises a zener diode, an anode of the zener diode is connected to the source of the power transistor, a cathode of the zener diode is connected to the drain of the sixth PMOS transistor and the power transistor driving unit, and a reverse breakdown voltage of the zener diode is matched to the specific voltage difference or the specific voltage difference range.
18. The driving circuit according to claim 14, wherein the power tube driving unit comprises: a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a seventh PMOS transistor and an eighth PMOS transistor;
the drain electrode of the fifth NMOS transistor is connected with the current bias unit to obtain the bias current, the source electrode of the fifth NMOS transistor and the source electrode of the sixth NMOS transistor are connected with the source electrode of the power transistor, the gate electrode of the fifth NMOS transistor is connected with the gate electrode of the sixth NMOS transistor, the drain electrodes of the sixth NMOS transistor are respectively connected with the source electrode of the seventh NMOS transistor and the source electrode of the eighth NMOS transistor, the drain electrode of the seventh NMOS transistor is connected with the input power supply of the driving circuit through the seventh PMOS transistor, the drain electrode of the eighth NMOS transistor is connected with the input power supply through the eighth PMOS transistor, the gate electrode of the seventh PMOS transistor is connected with the gate electrode of the eighth PMOS transistor, the gate electrode and the drain electrode of the seventh PMOS transistor are connected with each other, the gate electrode of the seventh NMOS transistor is connected with the floating voltage generation unit to obtain the bias voltage, and the gate electrode of the eighth NMOS transistor is connected with the gate electrodes of the power transistor and the monitoring transistor, to output the driving current and the driving voltage.
19. The drive circuit according to claim 18,
after the current limiting control module pulls down the driving voltage, the current of the power tube can be fixed in a specified current range or a specified current value under the combined action of the current of the second NMOS tube, the current of the eighth PMOS tube and the current of the discharge unit of the power tube.
20. The drive circuit according to claim 18,
in a case that the current limiting control module is further configured to control the main driving module to decrease the driving current in response to the trigger, the current of the seventh PMOS transistor can decrease under the control of the current limiting control module, so that the driving current decreases accordingly.
21. The driving circuit according to any of claims 14 to 20, wherein the power tube discharge unit comprises a discharge resistor connected between the gate and the source of the power tube.
22. The driver circuit according to any of claims 1 to 20, wherein the monitor tube is smaller in size than the power tube.
23. The driving circuit according to any of claims 1 to 20, wherein the power transistor is a high side NMOS transistor.
24. An electronic device comprising the driving circuit of any one of claims 1 to 23 and the power transistor.
CN202210355295.9A 2022-04-02 2022-04-02 Driving circuit of power tube and electronic equipment Withdrawn CN114866077A (en)

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CN115864343A (en) * 2023-03-03 2023-03-28 珠海智融科技股份有限公司 Current limiting circuit

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CN100589058C (en) * 2007-12-27 2010-02-10 北京中星微电子有限公司 Current limitation circuit as well as voltage regulator and DC-DC converter including the same
CN203251283U (en) * 2013-03-18 2013-10-23 意法半导体研发（上海）有限公司 Circuit for discharging gate of driving transistor having drain and source, and circuit for driver
CN103645765B (en) * 2013-12-20 2016-01-13 嘉兴中润微电子有限公司 A kind of for the high-voltage great-current control circuit in high-voltage power MOSFET circuit
CN106788357B (en) * 2017-01-23 2020-03-13 上海贝岭股份有限公司 Driving circuit
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CN111478300A (en) * 2020-05-09 2020-07-31 上海维安半导体有限公司 Foldback overcurrent protection circuit
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CN115842330A (en) * 2022-12-30 2023-03-24 杭州朋声科技有限公司 Overcurrent protection circuit and chip
CN115842330B (en) * 2022-12-30 2024-04-05 杭州朋声科技有限公司 Overcurrent protection circuit and chip
CN115864343A (en) * 2023-03-03 2023-03-28 珠海智融科技股份有限公司 Current limiting circuit

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