CN114866054A - Low-pass filter chip based on IPD technology - Google Patents
Low-pass filter chip based on IPD technology Download PDFInfo
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- CN114866054A CN114866054A CN202210609255.2A CN202210609255A CN114866054A CN 114866054 A CN114866054 A CN 114866054A CN 202210609255 A CN202210609255 A CN 202210609255A CN 114866054 A CN114866054 A CN 114866054A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
- H03H1/0007—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network of radio frequency interference filters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/17—Structural details of sub-circuits of frequency selective networks
- H03H7/1741—Comprising typical LC combinations, irrespective of presence and location of additional resistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/17—Structural details of sub-circuits of frequency selective networks
- H03H7/1741—Comprising typical LC combinations, irrespective of presence and location of additional resistors
- H03H7/1758—Series LC in shunt or branch path
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
- H03H2001/0021—Constructional details
- H03H2001/0085—Multilayer, e.g. LTCC, HTCC, green sheets
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Abstract
The invention belongs to the technical field of filters, and particularly relates to a low-pass filter chip based on IPD technology, which comprises a medium substrate, and an input electrode, an output electrode, a plurality of grounding electrodes, a plurality of grounding through holes, a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a first capacitor, a second capacitor, a third capacitor and a plurality of transmission lines which are grown on the medium substrate to form a seven-order series elliptic function response low-pass filter circuit, so that the filtering processing of radio-frequency signals is realized, all components are integrated on the same chip by adopting the IPD technology process, and the low-pass filter chip has the characteristics of high integration level, small layout area, high out-band rejection, wide band and steep frequency cut-off characteristic.
Description
Technical Field
The invention belongs to the technical field of filters, and particularly relates to a low-pass filter chip based on IPD technology.
Background
In modern Wireless communication systems, such as Virtual Reality (VR), Wireless Local Area Network (WLAN), satellite communication, etc., which are rapidly developing, the need for low pass filters is increasing. In these systems, low pass filters are applied in the rf front end receiver to suppress image frequencies, local oscillator frequencies and harmonics.
Among them, compact size, steep frequency cutoff characteristics, and high out-of-band rejection transmission characteristics are important requirements for low-pass filters. To meet these requirements, system-in-a-package (SiP) technology is widely used in rf systems.
Most of the conventional low-pass filters adopt a low temperature co-fired ceramic (LTCC) technology, but the size of the ceramic substrate is limited on the development road of miniaturization.
Therefore, the miniaturization, high out-of-band rejection, wide band and steep frequency cut-off characteristics of the low-pass filter are the difficulties in the development of the low-pass filter.
Disclosure of Invention
The invention aims to provide a low-pass filter chip based on IPD technology, aiming at realizing the purposes that a low-pass filter has small size, high out-of-band rejection, wide frequency band and steep frequency cut-off characteristic.
The embodiment of the invention provides a low-pass filter chip based on IPD technology, which comprises:
a dielectric substrate;
the input electrode, the output electrode, the grounding electrodes, the grounding through holes, the first inductor, the second inductor, the third inductor, the fourth inductor, the fifth inductor, the sixth inductor, the first capacitor, the second capacitor, the third capacitor and the transmission lines are grown on the dielectric substrate;
the input electrode, the first inductor, the second inductor, the third inductor, the fourth inductor and the output electrode are sequentially connected through the transmission line;
the first inductor and the second inductor are respectively connected with the first end of the first capacitor in parallel through a transmission line, and the second end of the first capacitor is connected with one grounding through hole through the transmission line;
the second inductor and the third inductor are respectively connected with the first end of the fifth inductor in parallel through a transmission line, the second end of the fifth inductor is connected with the first end of the second capacitor, and the second end of the second capacitor is connected with one grounding through hole through a transmission line;
the third inductor and the fourth inductor are respectively connected with the first end of the sixth inductor in parallel through a transmission line, the second end of the sixth inductor is connected with the first end of the third capacitor, and the second end of the third capacitor is connected with one grounding through hole through a transmission line;
and the corresponding grounding electrodes are connected with the corresponding grounding through holes through transmission lines, and the grounding through holes are grounded in a coplanar manner.
In one embodiment, the ground electrode comprises a first ground electrode, a second ground electrode, a third ground electrode, and a fourth ground electrode;
the input electrode and the output electrode are oppositely arranged on two sides of the dielectric substrate along the length direction of the dielectric substrate;
the first grounding electrode and the second grounding electrode are symmetrically arranged on two sides of the input electrode along the width direction of the dielectric substrate to form a GSG coplanar port;
the third grounding electrode and the fourth grounding electrode are symmetrically arranged on two sides of the output electrode along the width direction of the dielectric substrate to form GSG coplanar ports;
the first grounding electrode, the second grounding electrode, the third grounding electrode and the fourth grounding electrode are grounded through a grounding through hole respectively.
In one embodiment, the first inductor, the second inductor, the third inductor, the fourth inductor, the fifth inductor and the sixth inductor are all planar inductors with a square ring structure, each inductor comprises n coils, and n is greater than or equal to 1.
In one embodiment, the first capacitor, the second capacitor and the third capacitor are all double-layer planar plate capacitors.
In one embodiment, the first inductor, the first capacitor, the second inductor, the fifth inductor, the third inductor, the sixth inductor and the fourth inductor are sequentially arranged on two sides of the dielectric substrate in the width direction in a crossed manner along the length direction of the dielectric substrate;
the first capacitor and the grounding through hole are sequentially arranged along the width direction of the dielectric substrate;
the fifth inductor, the second capacitor and the grounding through hole are sequentially arranged along the width direction of the dielectric substrate;
the sixth inductor, the third capacitor and the grounding through hole are sequentially arranged along the width direction of the dielectric substrate.
In one embodiment, a corresponding grounding electrode and a corresponding grounding through hole are sequentially arranged along the length direction of the dielectric substrate.
In one embodiment, the dielectric substrate comprises a circuit structure layer, a substrate layer and an equivalent large ground layer which are arranged from top to bottom in sequence;
the input electrode, the output electrode, the grounding electrode, the first inductor, the second inductor, the third inductor, the fourth inductor, the first capacitor, the second capacitor, the third capacitor and the plurality of transmission lines are grown on the circuit structure layer;
the equivalent ground layer is a metal conductor layer formed on the lower surface of the substrate layer through electroplating;
a plurality of the ground vias are co-planarly connected to the equivalent large ground layer.
In one embodiment, the input electrode, the output electrode, and the ground electrode are all square electrodes or circular electrodes;
the grounding through hole is a square through hole or a round through hole.
In one embodiment, the input electrode, the output electrode, and the ground electrode are each 100um by 100um in size, and the ground vias are 84um by 84um in size.
In one embodiment, the material of the dielectric substrate is a gallium arsenide material.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the low-pass filter chip forms a seven-order series elliptic function response low-pass filter circuit by a dielectric substrate, and an input electrode, an output electrode, a plurality of grounding electrodes, a plurality of grounding through holes, a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, a first capacitor, a second capacitor, a third capacitor and a plurality of transmission lines which are grown on the dielectric substrate, so that the filtering processing of radio-frequency signals is realized, all components are integrated on the same chip by adopting an IPD (orthogonal frequency division multiplexing) technology, and the low-pass filter chip has the characteristics of high integration level, small layout area, high out-of-band rejection, wide frequency band and steep frequency cut-off characteristic.
Drawings
Fig. 1 is a schematic structural diagram of a low pass filter chip based on IPD technology according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a low pass filter chip based on IPD technology according to an embodiment of the present invention;
fig. 3 is a schematic diagram of test curves of an input return loss S11 and an output return loss S22 of a low-pass filter chip based on IPD technology according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a test curve of the stop band rejection S21 of the low pass filter chip based on the IPD technology according to the embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
The embodiment of the invention provides a low-pass filter chip based on IPD technology, which is used for completing low-pass filtering of radio frequency signals, namely, only radio frequency signals lower than cut-off frequency are passed, and radio frequency signals higher than the cut-off frequency cannot be passed.
As shown in fig. 1 and fig. 2, the low pass filter chip based on the IPD technology includes:
a dielectric substrate;
an input electrode RFIN, an output electrode RFOUT, a plurality of grounding electrodes G, a plurality of grounding through holes Via, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a plurality of transmission lines P which are grown on the dielectric substrate;
the input electrode RFIN, the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4 and the output electrode RFOUT are connected in sequence through a transmission line P;
the first inductor L1 and the second inductor L2 are respectively connected in parallel with a first end of the first capacitor C1 through a transmission line P, and a second end of the first capacitor C1 is connected with a ground Via through the transmission line P;
the second inductor L2 and the third inductor L3 are respectively connected in parallel with a first end of a fifth inductor L5 through a transmission line P, a second end of the fifth inductor L5 is connected with a first end of a second capacitor C2, and a second end of the second capacitor C2 is connected with a grounding through hole Via through the transmission line P;
the third inductor L3 and the fourth inductor L4 are respectively connected in parallel with a first end of a sixth inductor L6 through a transmission line P, a second end of the sixth inductor L6 is connected with a first end of a third capacitor C3, and a second end of the third capacitor C3 is connected with a grounding through hole Via through the transmission line P;
the corresponding grounding electrode G is connected with the corresponding grounding through hole Via through a transmission line P, and each grounding through hole Via is grounded in a coplanar manner.
In this embodiment, the low-pass filter chip uses ADS circuit simulation software to debug and optimize the circuit element values, so as to obtain the required bandwidth, center frequency, and out-of-band rejection.
And IPD (Integrated Passive Devices) process is adopted, a dielectric substrate is adopted as a substrate, the whole low-pass filter circuit is grown on the substrate through thin film processes such as exposure, development, coating, diffusion, etching and the like, the low-pass filter circuit comprises an input electrode RFIN, an output electrode RFOUT, a plurality of grounding electrodes G, a plurality of grounding through holes Via, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a plurality of transmission lines P, wherein the input electrode RFIN, the output electrode RFOUT and the grounding electrode G form a signal pin of the low-pass filter chip for signal input, signal output and grounding, the input electrode RFIN is used for connecting a signal source, the output electrode RFOUT is used for connecting a back-end circuit or a load, and the ground electrode G is used for grounding.
The seven-order series elliptic function response low-pass filter circuit is composed of a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a first capacitor C1, a second capacitor C2 and a third capacitor C3, the low-pass filter function is achieved by the characteristics of high-frequency-pass low-frequency of inductor resistance and high-frequency-pass low-frequency of capacitor resistance, radio-frequency signals input by an input electrode RFIN are subjected to low-pass filtering and output from an output electrode RFOUT, signal conversion and impedance matching are achieved, and therefore the low-pass filter chip with impedance matching and small reflection loss is obtained.
Meanwhile, an IPD (inverse diode direct current) technical process is adopted, and the low-pass filter chip achieves high integration and miniaturization.
The seven-order series elliptic function response low-pass filter circuit comprises four series resonance units and three parallel resonance units, as shown in fig. 2, wherein a first inductor L1, a second inductor L2, a third inductor L3 and a fourth inductor L4 are respectively four series resonance units connected in series, a first capacitor C1 forms a parallel resonance unit, a fifth inductor L5 and a second capacitor C2 are connected to form a second parallel resonance unit, a sixth inductor L6 and a third capacitor C3 are connected to form a third parallel resonance unit, and the series resonance unit and the parallel resonance unit filter the frequency of an input radio frequency signal to output the radio frequency signal with a preset passband frequency.
As shown in FIG. 3 and FIG. 4, through simulation design, the input return loss S11 of the low-pass filter chip is less than-16.0 dB in the whole DC 0 Hz-12 GHz frequency band, which shows that the loss of the radio-frequency signal reflected back is small, and the low-pass filter achieves impedance matching.
The stop band rejection S21 of the low-pass filter chip is larger than-2.5 dB in the whole DC 0 Hz-12 GHz frequency band, which shows that the low-pass filter chip has small insertion loss and good transmission characteristic.
At 15GHz, S21 < -20dB, which shows that the rectangular coefficient of the low-pass filter chip is good and has a steep cut-off frequency, and at 16.5 GHz-40 GHz, S21 is less than-40 dB, which shows that the low-pass filter chip has high out-of-band rejection characteristics.
The dielectric substrate can be a single-layer substrate or a multi-layer substrate, when the single-layer substrate is used, the dielectric substrate comprises a first layer and a second layer opposite to the first layer, each grounding through hole Via is connected with the first layer and the second layer of the dielectric substrate in a Via hole mode, a grounding electrode G, an input electrode RFIN, an output electrode RFOUT, a plurality of inductors and a plurality of capacitors are formed on the first layer, and the low-pass filter chip is connected with a grounding signal through one or a plurality of corresponding grounding electrodes G, so that each capacitor is grounded through the corresponding grounding through hole Via to form a parallel resonant circuit.
When the dielectric substrate is a multilayer substrate, the dielectric substrate comprises a first layer to an nth layer, wherein a grounding electrode G, an input electrode RFIN, an output electrode RFOUT, a plurality of inductors and a plurality of capacitors are formed on the first layer, a grounding through hole Via is connected to any one of the 2 nd layer to the nth layer of the dielectric substrate in a Via hole mode, and a low-pass filter chip is connected to a grounding signal through one or a plurality of corresponding grounding electrodes G, so that each capacitor is grounded through the corresponding grounding through hole Via to form a parallel resonant circuit.
Optionally, in order to further achieve miniaturization of the low pass filter chip, the dielectric substrate is a single-layer substrate, and the dielectric substrate is formed by using a corresponding material type, such as silicon, gallium arsenide, and the like, wherein, in order to achieve high integration and comply with the current trend of radio frequency passive devices, in one embodiment, the material of the dielectric substrate is a gallium arsenide (GaAs) material.
Meanwhile, when a single-layer substrate is adopted, in order to simplify the process of coplanar connection of a plurality of grounding through holes Via, in one embodiment, the dielectric substrate comprises a circuit structure layer, a base layer and an equivalent ground layer which are sequentially arranged from top to bottom;
the input electrode RFIN, the output electrode RFOUT, the ground electrode G, the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the first capacitor C1, the second capacitor C2, the third capacitor C3 and the plurality of transmission lines P are grown and formed in the circuit structure layer.
The equivalent large ground layer is a metal conductor layer formed on the lower surface of the substrate layer through electroplating, and the plurality of grounding through holes Via are connected to the equivalent large ground layer in a coplanar manner, so that the first capacitor C1, the second capacitor C2 and the third capacitor C3 are connected to the equivalent large ground layer and the grounding through holes Via corresponding grounding through holes Via, and grounding work is completed.
The input electrode RFIN, the output electrode RFOUT, and the ground electrode G may be of corresponding shape structures, such as regular circles, squares, or irregular structures, wherein, in order to facilitate the formation of the electrode and simplify the process, optionally, the input electrode RFIN, the output electrode RFOUT, and the ground electrode G are all square electrodes or circular electrodes, and meanwhile, the ground Via may be correspondingly configured as a square Via or a circular Via corresponding to the structure of the ground electrode G.
In order to achieve miniaturization while matching the size of the dielectric substrate, in one embodiment, the input electrode RFIN, the output electrode RFOUT, and the ground electrode G are all square electrodes with a size of 100um × 100um, and the ground vias Via are all square vias with a size of 84um × 84 um.
One or more grounding electrodes G can be arranged, wherein in order to facilitate the probe station to carry out symmetry test on the low-pass filter chip and perform grounding function, in one embodiment, the grounding electrodes G comprise a first grounding electrode G, a second grounding electrode G, a third grounding electrode G and a fourth grounding electrode G;
the input electrode RFIN and the output electrode RFOUT are oppositely arranged on two sides of the dielectric substrate along the length direction X of the dielectric substrate;
the first grounding electrode G and the second grounding electrode G are symmetrically arranged on two sides of the input electrode RFIN along the width direction Y of the dielectric substrate to form GSG coplanar ports;
the third grounding electrode G and the fourth grounding electrode G are symmetrically arranged on two sides of the output electrode RFOUT along the width direction Y of the dielectric substrate to form GSG coplanar ports;
the first grounding electrode G, the second grounding electrode G, the third grounding electrode G and the fourth grounding electrode G are respectively grounded through a grounding through hole Via.
The grounding electrodes G are symmetrically arranged on two sides of the input electrode RFIN and the output electrode RFOUT, so that the probe station can conveniently carry out symmetric test on the low-pass filter chip, wherein the grounding electrodes G and the input electrode RFIN or the output electrode RFOUT can be correspondingly arranged according to the miniaturization size requirement of the low-pass filter chip, for example, between 140um and 160 um.
In order to achieve the effects of matching impedance and improving voltage standing wave ratio performance, the transmission lines P between the multiple inductors and the multiple capacitors are in linear connection.
The transmission line P between the first inductor L1 and the input electrode RFIN may be correspondingly configured according to the size of the first inductor L1 and the size of the input electrode RFIN, for example, as shown in fig. 1, the transmission line P with gradually increased thickness may be used for connection, and similarly, the transmission line P between the fourth inductor L4 and the output electrode RFOUT may be correspondingly configured according to the size of the fourth inductor L4 and the size of the output electrode RFOUT, and the transmission line P with gradually increased thickness may be used for connection.
The shapes, thicknesses and turns of the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5 and the sixth inductor L6 can be correspondingly set according to the requirements of low-pass filtering, the size of a low-pass filter chip and a simulation result, and the inductors can be in circular or square ring structures, correspond to the thicknesses and the turns, and are not limited to specific shapes, thicknesses and turns.
In one embodiment, the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, the fifth inductor L5, and the sixth inductor L6 are all planar inductors in a square ring structure, each inductor includes n coils, where n is greater than or equal to 1, the square ring structure facilitates manufacturing of the inductor, and simultaneously, adjustment of an inductor Q value, the inductor Q value, also called a quality factor of the inductor, according to a requirement of a preset pass band frequency is facilitated, which is a main parameter for measuring an inductor device. The Q value of the inductance is the ratio of the inductance presented by the inductor when the inductor is operated at an ac voltage of a certain frequency to its equivalent loss resistance. The higher the Q value of the inductor, the lower its losses and the higher the efficiency.
The area of each inductor can be correspondingly set according to the loss and the efficiency of the low-pass filter chip, wherein the planar inductor has the characteristics that the smaller the area is, the worse the inductance Q value is generally, the larger the area is, the better the inductance Q value is generally, the higher the Q value of the inductor is, the smaller the loss of the filter is, and the higher the efficiency is.
In one embodiment, the first capacitor C1, the second capacitor C2 and the third capacitor C3 are all double-layer planar plate capacitors, and are produced and formed on a dielectric substrate by using an IPD technology process, and each capacitor is composed of a top metal layer, a bottom metal layer, a top metal layer and a middle insulating layer, the middle insulating layer may be but is not limited to a silicon nitride middle insulating layer, and the first capacitor C1, the second capacitor C2 and the third capacitor C3 form a passive capacitor. High integration is achieved, as well as reduced capacitance and low pass filter chip size.
In order to further realize the size miniaturization of the low pass filter chip, as shown in fig. 1, in one embodiment, the first inductor L1, the first capacitor C1, the second inductor L2, the fifth inductor L5, the third inductor L3, the sixth inductor L6 and the fourth inductor L4 are sequentially arranged on both sides of the dielectric substrate in the width direction Y in a crossing manner along the length direction X of the dielectric substrate, the first capacitor C1 and the ground Via are sequentially arranged along the width direction Y of the dielectric substrate, the fifth inductor L5, the second capacitor C2 and the ground Via are sequentially arranged along the width direction Y of the dielectric substrate, the sixth inductor L6, the third capacitor C3 and the ground Via are sequentially arranged along the width direction Y of the dielectric substrate, the area occupied by the low pass filter circuit is reduced by correspondingly arranging the positions of the inductors and the capacitors, and the sizes of the length and the width of the low pass filter chip can be further reduced, further realizing the miniaturization of the low-pass filter chip.
In order to further realize the size miniaturization of the low-pass filter chip, in one embodiment, a corresponding ground electrode G and a corresponding ground Via are sequentially arranged along the length direction X of the dielectric substrate, so that the width size of the low-pass filter chip can be further reduced, and the miniaturization of the low-pass filter chip is further realized.
The miniaturization of the low-pass filter chip is realized by correspondingly arranging the position relations of the inductors, the capacitors, the input electrode RFIN, the output electrode RFOUT and the grounding through hole Via, and in one embodiment, the length range of the low-pass filter chip is 1.3 +/-0.05 mm; the width range of the low-pass filter chip is 0.6 +/-0.05 mm; the height range of the low-pass filter chip is 0.1 +/-0.05 mm.
The low-pass filter chip with the corresponding size formed based on the IPD technology realizes the microminiaturization of the low-pass filter chip and is convenient to be applied to various electronic devices needing patches.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the low-pass filter chip comprises a dielectric substrate, and an input electrode RFIN, an output electrode RFOUT, a plurality of grounding electrodes G, a plurality of grounding through holes Via, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a plurality of transmission lines P which are grown on the dielectric substrate, form a seven-order series elliptic function response low-pass filter circuit, so that the filtering processing of radio-frequency signals is realized, all components are integrated on the same chip by adopting an IPD (orthogonal phase-division multiplexing) technology, and the low-pass filter chip has the characteristics of high integration level, small layout area, high out-of-band rejection, wide band and steep frequency cut-off characteristics.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. An IPD technology based low pass filter chip, comprising:
a dielectric substrate;
the input electrode, the output electrode, the grounding electrodes, the grounding through holes, the first inductor, the second inductor, the third inductor, the fourth inductor, the fifth inductor, the sixth inductor, the first capacitor, the second capacitor, the third capacitor and the transmission lines are grown on the dielectric substrate;
the input electrode, the first inductor, the second inductor, the third inductor, the fourth inductor and the output electrode are sequentially connected through the transmission line;
the first inductor and the second inductor are respectively connected with the first end of the first capacitor in parallel through a transmission line, and the second end of the first capacitor is connected with one grounding through hole through the transmission line;
the second inductor and the third inductor are respectively connected with the first end of the fifth inductor in parallel through a transmission line, the second end of the fifth inductor is connected with the first end of the second capacitor, and the second end of the second capacitor is connected with one grounding through hole through a transmission line;
the third inductor and the fourth inductor are respectively connected with the first end of the sixth inductor in parallel through a transmission line, the second end of the sixth inductor is connected with the first end of the third capacitor, and the second end of the third capacitor is connected with one grounding through hole through a transmission line;
and the corresponding grounding electrodes are connected with the corresponding grounding through holes through transmission lines, and the grounding through holes are grounded in a coplanar manner.
2. The IPD technology based low pass filter chip of claim 1, wherein said ground electrodes comprise a first ground electrode, a second ground electrode, a third ground electrode and a fourth ground electrode;
the input electrode and the output electrode are oppositely arranged on two sides of the dielectric substrate along the length direction of the dielectric substrate;
the first grounding electrode and the second grounding electrode are symmetrically arranged on two sides of the input electrode along the width direction of the dielectric substrate to form a GSG coplanar port;
the third grounding electrode and the fourth grounding electrode are symmetrically arranged on two sides of the output electrode along the width direction of the dielectric substrate to form GSG coplanar ports;
the first grounding electrode, the second grounding electrode, the third grounding electrode and the fourth grounding electrode are grounded through a grounding through hole respectively.
3. The IPD-based low pass filter chip of claim 1, wherein the first inductor, the second inductor, the third inductor, the fourth inductor, the fifth inductor and the sixth inductor are all planar inductors having a square ring structure, each inductor comprises n turns of coils, and n is greater than or equal to 1.
4. The IPD technology based low pass filter chip of claim 1, wherein said first capacitor, said second capacitor and said third capacitor are all double layer planar plate capacitors.
5. The IPD technology-based low-pass filter chip of claim 1, wherein the first inductor, the first capacitor, the second inductor, the fifth inductor, the third inductor, the sixth inductor and the fourth inductor are sequentially disposed across two sides of the dielectric substrate in a width direction along a length direction of the dielectric substrate;
the first capacitor and the grounding through hole are sequentially arranged along the width direction of the dielectric substrate;
the fifth inductor, the second capacitor and the grounding through hole are sequentially arranged along the width direction of the dielectric substrate;
the sixth inductor, the third capacitor and the grounding through hole are sequentially arranged along the width direction of the dielectric substrate.
6. The IPD technology based low pass filter chip according to claim 2, wherein a corresponding ground electrode and a corresponding ground via are sequentially disposed along a length direction of said dielectric substrate.
7. The IPD technology based low pass filter chip according to claim 1, wherein said dielectric substrate comprises a circuit structure layer, a substrate layer and an equivalent ground layer arranged in sequence from top to bottom;
the input electrode, the output electrode, the grounding electrode, the first inductor, the second inductor, the third inductor, the fourth inductor, the first capacitor, the second capacitor, the third capacitor and the plurality of transmission lines are grown on the circuit structure layer;
the equivalent ground layer is a metal conductor layer formed on the lower surface of the substrate layer through electroplating;
a plurality of the ground vias are co-planarly connected to the equivalent large ground layer.
8. The IPD technology based low pass filter chip of claim 1, wherein said input electrode, said output electrode and said ground electrode are all square electrodes or circular electrodes;
the grounding through hole is a square through hole or a round through hole.
9. The IPD technology based low pass filter chip of claim 8, wherein the input electrode, the output electrode and the ground electrode are all 100um x 100um in size, and the ground vias are 84um x 84um in size.
10. The IPD technology based low pass filter chip according to claim 1, wherein the material of the dielectric substrate is a gallium arsenide material.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115412043A (en) * | 2022-10-31 | 2022-11-29 | 成都科谱达信息技术有限公司 | Symmetrical lumped parameter low-pass filter for improving far-end rejection performance |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115412043A (en) * | 2022-10-31 | 2022-11-29 | 成都科谱达信息技术有限公司 | Symmetrical lumped parameter low-pass filter for improving far-end rejection performance |
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