CN114864553A - Integrated circuit package and integrated circuit packaging method - Google Patents

Integrated circuit package and integrated circuit packaging method Download PDF

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Publication number
CN114864553A
CN114864553A CN202210620999.4A CN202210620999A CN114864553A CN 114864553 A CN114864553 A CN 114864553A CN 202210620999 A CN202210620999 A CN 202210620999A CN 114864553 A CN114864553 A CN 114864553A
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China
Prior art keywords
integrated circuit
product
noise reduction
circuit product
package
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Pending
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CN202210620999.4A
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Chinese (zh)
Inventor
姜赋升
赵冬冬
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Riyuexin Semiconductor Suzhou Co ltd
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Riyuexin Semiconductor Suzhou Co ltd
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Priority to CN202210620999.4A priority Critical patent/CN114864553A/en
Publication of CN114864553A publication Critical patent/CN114864553A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

The present application provides an integrated circuit package. The integrated circuit package includes: the noise reduction device comprises a carrier plate, a first integrated circuit product, a second integrated circuit product and a noise reduction component. The first integrated circuit product and the second integrated circuit product are arranged on the carrier plate. The first integrated circuit product and the second integrated circuit product are electrically connected. The noise reduction component is arranged on the carrier plate and surrounds the first integrated circuit product and the second integrated circuit product. The noise reduction component is configured to reduce noise or to transmit a vibration signal. The application also provides an integrated circuit packaging method. The integrated circuit packaging method comprises the following steps: arranging a first integrated circuit product and a second integrated circuit product on a carrier plate; electrically connecting the first integrated circuit product and the second integrated circuit product; and arranging a noise reduction component on the carrier plate so as to surround the first integrated circuit product and the second integrated circuit product.

Description

Integrated circuit package and integrated circuit packaging method
Technical Field
The present application relates generally to semiconductors, and more particularly to integrated circuit packages and methods of packaging integrated circuits.
Background
Currently, bone sensing technology is beginning to be widely used. However, the related packaging technology of integrated circuits using bone sensing technology has not provided good signal-to-noise ratio, resulting in poor user experience.
Disclosure of Invention
The present application provides an integrated circuit package and an integrated circuit packaging method to solve the above problems.
According to an embodiment of the present application, an integrated circuit package is provided. The integrated circuit package includes: the noise reduction device comprises a carrier plate, a first integrated circuit product, a second integrated circuit product and a noise reduction component. The first integrated circuit product and the second integrated circuit product are arranged on the carrier plate of the carrier plate. The first integrated circuit product and the second integrated circuit product are electrically connected. The noise reduction component is arranged on the carrier plate and surrounds the first integrated circuit product and the second integrated circuit product. The noise reduction component is configured to reduce noise or to transmit a vibration signal.
According to an embodiment of the application, the integrated circuit package further comprises a vibrating member. The vibration component is connected to the noise reduction component and encapsulates the first integrated circuit product and the second integrated circuit product.
According to an embodiment of the present application, the vibration member includes a vibration plate, a vibration mass, and a vibration ring. The vibrating mass is disposed at the center of the first surface of the vibrating plate. The vibration ring is disposed on an edge of the first surface of the vibration plate. The vibration ring is arranged on the noise reduction part.
According to an embodiment of the present application, the vibration block and the vibration ring include metal.
According to an embodiment of the present application, the integrated circuit package further includes a bottom plate and a lid. The carrier plate is welded on the bottom plate. The cover is disposed over the base plate. The cover member surrounds and covers the carrier plate, the first integrated circuit product, the second integrated circuit product, and the noise reduction feature.
According to an embodiment of the present application, the top of the lid has a hole.
According to an embodiment of the present application, the carrier includes a hole, wherein two ends of the first ic product cross the hole.
According to an embodiment of the application, the first integrated circuit product comprises a microelectromechanical structure.
According to an embodiment of the present application, a silicone gel is disposed between the first integrated circuit product and the carrier.
According to an embodiment of the application, the noise reduction features are ring-shaped structures.
According to an embodiment of the present application, the noise reduction member includes an upper cover portion and an annular portion. The ring portion surrounds the first integrated circuit product and the second integrated circuit product. The upper cover part is arranged on the annular part and partially covers the first integrated circuit product and the second integrated circuit product.
According to an embodiment of the present application, a method for packaging an integrated circuit is provided. The integrated circuit packaging method comprises the following steps: arranging a first integrated circuit product and a second integrated circuit product on a carrier plate; electrically connecting the first integrated circuit product and the second integrated circuit product; and arranging a noise reduction component on the carrier plate so as to surround the first integrated circuit product and the second integrated circuit product.
According to an embodiment of the present application, the integrated circuit packaging method further includes: a vibration component is attached to the noise reduction component and encapsulates the first and second integrated circuit products.
According to an embodiment of the present application, the integrated circuit packaging method further includes: arranging the carrier plate on the bottom plate; disposing a cover over the base plate to surround and cover the carrier plate, the first integrated circuit product, the second integrated circuit product, and the noise reduction feature.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:
FIG. 1 illustrates a block diagram of an integrated circuit package according to an embodiment of the present application.
Fig. 2 illustrates a schematic diagram of an integrated circuit package according to an embodiment of the present application.
Fig. 3A-3G illustrate a flow chart of a fabrication process of an integrated circuit package according to an embodiment of the present application.
Fig. 4 illustrates a schematic diagram of an integrated circuit package according to another embodiment of the present application.
Fig. 5 illustrates a first partial flow chart of a method of packaging an integrated circuit according to an embodiment of the present application.
Fig. 6 illustrates a second partial flow diagram of a method of packaging an integrated circuit according to an embodiment of the present application.
Fig. 7 illustrates a third partial flow diagram of a method of packaging an integrated circuit according to an embodiment of the present application.
Detailed Description
The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the following description, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms, such as "under," "below," "over," "above," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. These spatially relative terms are intended to encompass a variety of different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Although numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain standard deviations found in their respective testing measurements. As used herein, "about" generally refers to actual values within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within the acceptable standard error of the mean, subject to consideration by those of ordinary skill in the art to which this application pertains. It is understood that all ranges, amounts, values and percentages used herein (e.g., to describe amounts of materials, length of time, temperature, operating conditions, quantitative ratios, and the like) are modified by the term "about" in addition to the experimental examples or unless otherwise expressly stated. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained. At the very least, these numerical parameters are to be understood as meaning the number of significant digits recited and the number resulting from applying ordinary carry notation. Herein, numerical ranges are expressed from one end to the other or between the two ends; unless otherwise indicated, all numerical ranges set forth herein are inclusive of the endpoints.
Fig. 1 illustrates a block diagram of an integrated circuit package 1 according to an embodiment of the present application. In some embodiments, the integrated circuit package 1 may be applied to a sensor. In some embodiments, the integrated circuit package 1 may be applied to a bone conduction technology sensor. In some embodiments, the integrated circuit package 1 comprises a carrier plate 11, a first integrated circuit product 12, a second integrated circuit product 13, and a noise reduction feature 14. In some embodiments, the first integrated circuit product 12 and the second integrated circuit product 13 are disposed on the carrier 11. In some embodiments, the first integrated circuit product 12 and the second integrated circuit product 13 are electrically connected. In some embodiments, the noise reduction features 14 are disposed on the carrier plate 11, and the noise reduction features 14 surround the first integrated circuit product 12 and the second integrated circuit product 13. In certain embodiments, the noise reduction features 14 are configured to reduce noise or transmit vibration signals.
Fig. 2 illustrates a schematic diagram of an integrated circuit package 2 according to an embodiment of the present application. In some embodiments, the integrated circuit package 2 may be used to implement the integrated circuit package 1 of the embodiment of fig. 1. In some embodiments, the integrated circuit package 2 comprises a carrier plate 21, a first integrated circuit product 22, a second integrated circuit product 23, and a noise reduction feature 24.
In some embodiments, the first integrated circuit product 22 and the second integrated circuit product 23 are disposed on the carrier 21. In some embodiments, the first integrated circuit product 22 and the second integrated circuit product 23 are soldered on the carrier plate 21 by solder. In some embodiments, the first integrated circuit product 22 and the second integrated circuit product 23 are electrically connected. In some embodiments, the first integrated circuit product 22 and the second integrated circuit product 23 are electrically connected by a conductive line WR. In some embodiments, a conductive line WR may be used to pass signals between the first integrated circuit product 22 and the second integrated circuit product 23. In some embodiments, the connection between the conductive line WR and the second integrated circuit product 23 can be protected by sputtering a protective material M1 on the second integrated circuit product 23. In some embodiments, the conductive line WR may be a gold line, a copper line, or other material.
In some embodiments, the noise reduction features 24 are disposed on the carrier plate 21. In some embodiments, the noise reduction features 24 surround the first and second integrated circuit products 22, 23. In certain embodiments, the noise reduction features 24 are configured to reduce noise or transmit vibration signals. In certain embodiments, the noise reduction features 24 comprise metal. In certain embodiments, the noise reduction features 24 are ring-shaped structures. In some embodiments, the noise reduction features 24 surround the first and second integrated circuit products 22, 23 and filter noise received by the first and second integrated circuit products 22, 23 through a masking effect.
In some embodiments, carrier plate 21 includes hole H21. In some embodiments, both ends of the first integrated circuit product 22 span the hole H21. In some embodiments, the first integrated circuit product 22 includes a microelectromechanical structure. In some embodiments, a silicone is disposed between the first ic product 22 and the carrier 21, and the first ic product 22 is adhered to the carrier 21 by using the silicone, so as to reduce the influence of the hard force of the silicone on the mems. In some embodiments, the second integrated circuit product 23 comprises an application specific integrated circuit. In some embodiments, the first ic product 22 receives the vibration of the air to generate the electromechanical conversion signal, and the second ic product 23 receives the electromechanical conversion signal and performs signal processing. The placement of the holes H21 may allow the shock of air to be transmitted from beneath the first integrated circuit product 22 to the first integrated circuit product 22 through the holes H21.
In some embodiments, the integrated circuit package 2 may further include a first adhesive layer 25. In some embodiments, the first adhesive layer 25 is coated on the carrier 21. In some embodiments, the layout of the first adhesive layer 25 on the carrier 21 may be a ring-shaped layout surrounding the first integrated circuit product 22 and the second integrated circuit product 23. In some embodiments, the layout of the first adhesive layer 25 on the carrier 21 may be a plurality of dot-shaped layouts surrounding the first integrated circuit product 22 and the second integrated circuit product 23. In some embodiments, the noise reduction features 25 are disposed on the carrier plate 21 by a first adhesive layer 25.
In some embodiments, the integrated circuit package 2 may also include other components to improve or enhance the bone sensing experience for the user. In some embodiments, the integrated circuit package 2 may also include a vibration member 27. In some embodiments, the vibration part 27 includes a vibration plate 271, a vibration block 272, and a vibration ring 273. In some embodiments, the vibration mass 272 is disposed at the center of the first face S271 of the vibration plate 272. In some embodiments, the vibration ring 273 is disposed at the edge of the first face S271 of the vibration plate 271. In some embodiments, the vibration ring 273 surrounds the vibration plate 272 located at the center of the first face S271 at the edge of the first face S271. The vibration ring 273 is disposed above the noise reduction member 24. In some embodiments, the vibrating mass 272 and the vibrating ring 273 comprise metal. The first and second integrated circuit products 22 and 23 are encapsulated by the vibration member 27, the shielding response can be enhanced, thereby enhancing the filtering effect of noise, and at the same time, the vibration plate 271 can transmit the vibration of air to the first integrated circuit product 22 as a medium. The signal-to-noise ratio can be effectively improved by the vibration member 27.
In some embodiments, the integrated circuit package 2 may further include a second adhesive layer 26. In some embodiments, the second adhesive layer 26 is applied over the noise reduction features 24. In some embodiments, the placement of the second adhesive layer 26 over the noise reduction features 24 may be a ring-like placement that fills the upper surface of the noise reduction features 24. In some embodiments, the placement of the second adhesive layer 26 over the noise reduction features 24 may be a plurality of dot-like placements applied to the upper surface of the noise reduction features 24. In some embodiments, the vibration ring 273 is disposed over the noise reduction features 24 by the second adhesive layer 26.
In some embodiments, the integrated circuit package 2 may also include other components to improve or enhance the bone sensing experience for the user. In some embodiments, the integrated circuit package 2 may further include a bottom plate 28 and a lid 29. In some embodiments, the carrier plate 21 is soldered on the bottom plate 28. In some embodiments, carrier plate 21 and base plate 28 may be made of the same material. In some embodiments, the cover 29 is disposed above the base plate 28. In some embodiments, the cover 29 is welded to the base 28. In some embodiments, a cover 29 surrounds and covers carrier plate 21, first integrated circuit product 22, second integrated circuit product 23, and noise reduction features 24. In some embodiments, the top of the lid 29 defines a hole H29. In certain embodiments, the cover 29 comprises a metal. By using a lid 29 comprising metal to enclose the carrier plate 21, the first integrated circuit product 22, the second integrated circuit product 23 and the noise reduction feature 24, the shielding effect may be further enhanced and noise reduced. Also, the lid 29 with the hole H29 can help the air of vibration to enter the ic package 2.
Fig. 3A-3G illustrate a process flow for manufacturing an integrated circuit package 2 according to an embodiment of the present application. As shown in fig. 3A, a solder paste is applied on the base plate 28. Next, as shown in fig. 3B, the carrier board 21 is placed on the bottom board 28. Next, as shown in fig. 3C, the first integrated circuit product 22 and the second integrated circuit product 23 are disposed on the carrier 21 by soldering. Next, as shown in fig. 3D, the first integrated circuit product 22 and the second integrated circuit product 23 are electrically connected by a wire WR, and a connection point of the second integrated circuit product 23 and the wire WR is protected by a protection material M1. Next, as shown in fig. 3E, a first adhesive layer 25 is coated on the carrier plate 21, and the noise reduction part 24 is placed on the first adhesive layer 25. Next, as shown in fig. 3F, a second adhesive layer 26 is coated on the noise reduction part 24, and the vibration part 27 is placed on the second adhesive layer 26. Next, as shown in FIG. 3G, the cover 29 is placed over the base plate 28 by solder paste. Thereby, the manufacturing process of the integrated circuit package 2 is completed.
Fig. 4 illustrates a schematic diagram of an integrated circuit package 3 according to an embodiment of the present application. In some embodiments, the integrated circuit package 3 may be used to implement the integrated circuit package 1 of the embodiment of fig. 1. The integrated circuit package 3 is substantially the same as the integrated circuit package 2, and differs only in the noise reduction member 34. Accordingly, the same portions of the integrated circuit package 3 as the integrated circuit package 2 will be omitted here for brevity. In certain embodiments, the noise reduction features 34 include an annular portion 341 and an upper cover portion 342. The ring portion 341 surrounds the first integrated circuit product 22 and the second integrated circuit product 23. In some embodiments, the upper cover portion 342 is disposed over the ring portion 341 and portions of the upper cover portion 342 cover the first and second integrated circuit products 22 and 23. Partially covering the first and second integrated circuit products 22, 23 with the upper cover portion 342 may enhance the shielding response and reduce noise.
Fig. 5 illustrates a first partial flow diagram of an integrated circuit packaging method 5 according to an embodiment of the present application. If substantially the same structure is obtained, the present application is not limited to being performed entirely in accordance with the process steps shown in fig. 5. In some embodiments, the first part of the integrated circuit packaging method 5 can be summarized as follows:
step 51: arranging a first integrated circuit product and a second integrated circuit product on a carrier plate;
step 52: electrically connecting the first integrated circuit product with the second integrated circuit product; and
step 53: the noise reduction component is arranged on the carrier plate to surround the first integrated circuit product and the second integrated circuit product.
Fig. 6 illustrates a second partial flow diagram of an integrated circuit packaging method 5 according to an embodiment of the present application. If substantially the same structure is obtained, the present application is not limited to being performed entirely in accordance with the process steps shown in fig. 6. In some embodiments, the second portion of the integrated circuit packaging method 5 is performed subsequent to the first portion of the integrated circuit packaging method 5. In some embodiments, the second part of the integrated circuit packaging method 5 can be summarized as follows:
step 54: the vibration component is attached to the noise reduction component and encapsulates the first integrated circuit product and the second integrated circuit product.
Fig. 7 illustrates a third partial flow diagram of an integrated circuit packaging method 5 according to an embodiment of the present application. If substantially the same structure is obtained, the present application is not limited to being performed entirely in accordance with the process steps shown in fig. 7. In some embodiments, the third portion of the integrated circuit packaging method 5 is performed subsequent to the first portion of the integrated circuit packaging method 5. In some embodiments, the third part of the integrated circuit packaging method 5 can be summarized as follows:
step 55: the carrier plate is arranged on the bottom plate.
Step 56: the cover member is disposed on the bottom plate to surround and cover the carrier plate, the first integrated circuit product, the second integrated circuit product and the noise reduction component.
One skilled in the art will understand the details of the integrated circuit packaging method 5 shown in fig. 5-7 after reading the embodiments of fig. 3A-3G. The detailed description is omitted here for brevity.
As used herein, the terms "approximately," "substantially," "essentially," and "about" are used to describe and account for minor variations. When used in conjunction with an event or circumstance, the terms can refer to an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity. As used herein with respect to a given value or range, the term "about" generally means within ± 10%, ± 5%, ± 1% or ± 0.5% of the given value or range. Ranges may be expressed herein as from one end point to another end point or between two end points. Unless otherwise specified, all ranges disclosed herein are inclusive of the endpoints. The term "substantially coplanar" may refer to two surfaces located within a few micrometers (μm) along the same plane, e.g., within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm located along the same plane. When referring to "substantially" the same numerical value or property, the term can refer to values that are within ± 10%, ± 5%, ± 1%, or ± 0.5% of the mean of the stated values.
As used herein, the terms "approximately," "substantially," "essentially," and "about" are used to describe and explain minor variations. When used in conjunction with an event or circumstance, the terms can refer to an instance in which the event or circumstance occurs precisely as well as an instance in which the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the terms can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are considered to be "substantially" or "about" the same if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values. For example, "substantially" parallel may refer to a range of angular variation of less than or equal to ± 10 ° from 0 °, e.g., less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °. For example, "substantially" perpendicular may refer to a range of angular variation of less than or equal to ± 10 ° from 90 °, e.g., less than or equal to ± 5 °, less than or equal to ± 4 °, less than or equal to ± 3 °, less than or equal to ± 2 °, less than or equal to ± 1 °, less than or equal to ± 0.5 °, less than or equal to ± 0.1 °, or less than or equal to ± 0.05 °.
For example, two surfaces may be considered coplanar or substantially coplanar if the displacement between the two surfaces is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm. A surface may be considered planar or substantially planar if the displacement of the surface relative to the plane between any two points on the surface is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm.
As used herein, the singular terms "a" and "the" can include the plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass the case where the preceding component is directly on (e.g., in physical contact with) the succeeding component, as well as the case where one or more intervening components are located between the preceding and succeeding components.
As used herein, spatially relative terms, such as "below," "lower," "above," "upper," "lower," "left," "right," and the like, may be used herein for ease of description to describe one component or feature's relationship to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present.
The foregoing summarizes features of several embodiments and detailed aspects of the present disclosure. The embodiments described in this disclosure may be readily used as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and/or obtaining the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure and various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure.

Claims (14)

1. An integrated circuit package, comprising:
a carrier plate;
the integrated circuit device comprises a first integrated circuit product and a second integrated circuit product which are arranged on a carrier plate, wherein the first integrated circuit product is electrically connected with the second integrated circuit product; and
a noise reduction feature disposed on the carrier plate and surrounding the first and second integrated circuit products, the noise reduction feature configured to reduce noise or transmit a vibration signal.
2. The integrated circuit package of claim 1, further comprising:
a vibration component connected to the noise reduction component and enclosing the first and second integrated circuit products.
3. The integrated circuit package of claim 2, wherein the vibrating member comprises:
a vibrating plate;
a vibrating mass disposed at the center of the first surface of the vibrating plate; and
and a vibration ring disposed at an edge of the first surface of the vibration plate, wherein the vibration ring is disposed above the noise reduction part.
4. The integrated circuit package of claim 3, wherein the vibrating mass and the vibrating ring comprise metal.
5. The integrated circuit package of claim 1, further comprising:
the carrier plate is arranged on the bottom plate;
a cover disposed over the bottom plate, the cover surrounding and covering the carrier, the first integrated circuit product, the second integrated circuit product, and the noise reduction feature.
6. The integrated circuit package of claim 5, wherein a top portion of the lid is perforated.
7. The integrated circuit package of claim 1, wherein the carrier includes a hole, wherein the two ends of the first integrated circuit product cross the hole.
8. The integrated circuit package of claim 7, wherein the first integrated circuit product comprises a microelectromechanical structure.
9. The ic package of claim 8, wherein a silicone gel is disposed between the first ic product and the carrier.
10. The integrated circuit package of claim 1, wherein the noise reduction feature is a ring structure.
11. The integrated circuit package of claim 1, wherein the noise reduction feature comprises an upper cover portion and a ring portion, the ring portion surrounding the first and second integrated circuit products, the upper cover portion disposed over and partially covering the first and second integrated circuit products.
12. A method of packaging an integrated circuit, comprising:
arranging a first integrated circuit product and a second integrated circuit product on a carrier plate;
electrically connecting the first integrated circuit product and the second integrated circuit product; and
and arranging a noise reduction component on the carrier plate so as to surround the first integrated circuit product and the second integrated circuit product.
13. The integrated circuit packaging method of claim 12, further comprising:
a vibration component is attached to the noise reduction component and encapsulates the first and second integrated circuit products.
14. The integrated circuit packaging method of claim 12, further comprising:
arranging the carrier plate on the bottom plate; and
disposing a cover over the base plate to surround and cover the carrier plate, the first integrated circuit product, the second integrated circuit product, and the noise reduction feature.
CN202210620999.4A 2022-06-01 2022-06-01 Integrated circuit package and integrated circuit packaging method Pending CN114864553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210620999.4A CN114864553A (en) 2022-06-01 2022-06-01 Integrated circuit package and integrated circuit packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210620999.4A CN114864553A (en) 2022-06-01 2022-06-01 Integrated circuit package and integrated circuit packaging method

Publications (1)

Publication Number Publication Date
CN114864553A true CN114864553A (en) 2022-08-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210620999.4A Pending CN114864553A (en) 2022-06-01 2022-06-01 Integrated circuit package and integrated circuit packaging method

Country Status (1)

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CN (1) CN114864553A (en)

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